| blob | 93340845175c93780e869d8af1e3df99a3336657 |
1 /*
2 * linux/arch/arm/mm/proc-sa110.S: MMU functions for SA110
3 *
4 * (C) 1997-1999 Russell King
5 *
6 * These are the low level assembler for performing cache and TLB
7 * functions on the StrongARM-110 and StrongARM-1100
8 */
9 #include <linux/linkage.h>
10 #include <asm/assembler.h>
11 #include <asm/procinfo.h>
12 #include <asm/hardware.h>
13 #include "../lib/constants.h"
15 /* This is the maximum size of an area which will be flushed. If the area
16 * is larger than this, then we flush the whole cache
17 */
18 #define MAX_AREA_SIZE 32768
19 #define FLUSH_OFFSET 32768
21 .macro flush_110_dcache rd, ra, re
22 add \re, \ra, #16384 @ only necessary for 16k
23 1001: ldr \rd, [\ra], #32
24 teq \re, \ra
25 bne 1001b
26 .endm
28 .macro flush_1100_dcache rd, ra, re
29 add \re, \ra, #8192 @ only necessary for 8k
30 1001: ldr \rd, [\ra], #32
31 teq \re, \ra
32 bne 1001b
33 #ifdef FLUSH_BASE_MINICACHE
34 add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
35 add \re, \ra, #512 @ only 512 bytes
36 1002: ldr \rd, [\ra], #32
37 teq \re, \ra
38 bne 1002b
39 #endif
40 .endm
42 .data
43 Lclean_switch: .long 0
44 .text
46 /*
47 * Function: sa110_flush_cache_all (void)
48 * Purpose : Flush all cache lines
49 */
50 .align 5
51 ENTRY(cpu_sa110_flush_cache_all) @ preserves r0
52 mov r2, #1
53 cpu_sa110_flush_cache_all_r2:
54 ldr r3, =Lclean_switch
55 ldr ip, =FLUSH_BASE
56 ldr r1, [r3]
57 ands r1, r1, #1
58 eor r1, r1, #1
59 str r1, [r3]
60 addne ip, ip, #FLUSH_OFFSET
61 flush_110_dcache r3, ip, r1
62 mov ip, #0
63 teq r2, #0
64 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
65 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mov pc, lr
68 .align 5
69 ENTRY(cpu_sa1100_flush_cache_all) @ preserves r0
70 mov r2, #1
71 cpu_sa1100_flush_cache_all_r2:
72 ldr r3, =Lclean_switch
73 ldr ip, =FLUSH_BASE
74 ldr r1, [r3]
75 ands r1, r1, #1
76 eor r1, r1, #1
77 str r1, [r3]
78 addne ip, ip, #FLUSH_OFFSET
79 flush_1100_dcache r3, ip, r1
80 mov ip, #0
81 teq r2, #0
82 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
84 mov pc, lr
86 /*
87 * Function: sa110_flush_cache_area (unsigned long address, int end, int flags)
88 * Params : address Area start address
89 * : end Area end address
90 * : flags b0 = I cache as well
91 * Purpose : clean & flush all cache lines associated with this area of memory
92 */
93 .align 5
94 ENTRY(cpu_sa110_flush_cache_area)
95 sub r3, r1, r0
96 cmp r3, #MAX_AREA_SIZE
97 bgt cpu_sa110_flush_cache_all_r2
98 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
99 mcr p15, 0, r0, c7, c6, 1 @ flush D entry
100 add r0, r0, #32
101 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
102 mcr p15, 0, r0, c7, c6, 1 @ flush D entry
103 add r0, r0, #32
104 cmp r0, r1
105 blt 1b
106 teq r2, #0
107 movne r0, #0
108 mcrne p15, 0, r0, c7, c5, 0 @ flush I cache
109 mov pc, lr
111 ENTRY(cpu_sa1100_flush_cache_area)
112 sub r3, r1, r0
113 cmp r3, #MAX_AREA_SIZE
114 bgt cpu_sa1100_flush_cache_all_r2
115 b 1b
117 /*
118 * Function: sa110_cache_wback_area(unsigned long address, unsigned long end)
119 * Params : address Area start address
120 * : end Area end address
121 * Purpose : ensure all dirty cachelines in the specified area have been
122 * written out to memory (for DMA)
123 */
124 .align 5
125 ENTRY(cpu_sa110_cache_wback_area)
126 sub r3, r1, r0
127 cmp r3, #MAX_AREA_SIZE
128 mov r2, #0
129 bgt cpu_sa110_flush_cache_all_r2
130 bic r0, r0, #31
131 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
132 add r0, r0, #32
133 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
134 add r0, r0, #32
135 cmp r0, r1
136 blt 1b
137 mcr p15, 0, r2, c7, c10, 4 @ drain WB
138 mov pc, lr
140 ENTRY(cpu_sa1100_cache_wback_area)
141 sub r3, r1, r0
142 cmp r3, #MAX_AREA_SIZE
143 mov r2, #0
144 bgt cpu_sa1100_flush_cache_all_r2
145 bic r0, r0, #31
146 b 1b
147 /*
148 * Function: sa110_cache_purge_area(unsigned long address, unsigned long end)
149 * Params : address Area start address
150 * : end Area end address
151 * Purpose : throw away all D-cached data in specified region without
152 * an obligation to write it back.
153 * Note : Must clean the D-cached entries around the boundaries if the
154 * start and/or end address are not cache aligned.
155 */
156 .align 5
157 ENTRY(cpu_sa110_cache_purge_area)
158 ENTRY(cpu_sa1100_cache_purge_area)
159 tst r0, #31
160 bic r0, r0, #31
161 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
162 tst r1, #31
163 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
164 1: mcr p15, 0, r0, c7, c6, 1 @ flush D entry
165 add r0, r0, #32
166 cmp r0, r1
167 blt 1b
168 mov pc, lr
170 /*
171 * Function: sa110_flush_cache_entry (unsigned long address)
172 * Params : address Address of cache line to flush
173 * Purpose : clean & flush an entry
174 */
175 .align 5
176 ENTRY(cpu_sa110_flush_cache_entry)
177 ENTRY(cpu_sa1100_flush_cache_entry)
178 mov r1, #0
179 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
180 mcr p15, 0, r1, c7, c10, 4 @ drain WB
181 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
182 mov pc, lr
184 /*
185 * Function: sa110_clean_cache_area(unsigned long start, unsigned long size)
186 * Params : address Address of cache line to clean
187 * Purpose : Ensure that physical memory reflects cache at this location
188 * for page table purposes.
189 */
190 ENTRY(cpu_sa110_clean_cache_area)
191 ENTRY(cpu_sa1100_clean_cache_area)
192 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry (drain is done by TLB fns)
193 add r0, r0, #32
194 subs r1, r1, #32
195 bhi 1b
196 mov pc, lr
198 /*
199 * Function: sa110_flush_ram_page (unsigned long page)
200 * Params : page Area start address
201 * Purpose : clean all cache lines associated with this area of memory
202 */
203 .align 5
204 ENTRY(cpu_sa110_flush_ram_page)
205 ENTRY(cpu_sa1100_flush_ram_page)
206 mov r1, #4096
207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 add r0, r0, #32
209 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 add r0, r0, #32
211 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
212 add r0, r0, #32
213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
214 add r0, r0, #32
215 subs r1, r1, #128
216 bne 1b
217 mov r0, #0
218 mcr p15, 0, r0, c7, c10, 4 @ drain WB
219 mov pc, lr
221 /*
222 * Function: sa110_flush_tlb_all (void)
223 * Purpose : flush all TLB entries in all caches
224 */
225 .align 5
226 ENTRY(cpu_sa110_flush_tlb_all)
227 ENTRY(cpu_sa1100_flush_tlb_all)
228 mov r0, #0
229 mcr p15, 0, r0, c7, c10, 4 @ drain WB
230 mcr p15, 0, r0, c8, c7, 0 @ flush I & D tlbs
231 mov pc, lr
233 /*
234 * Function: sa110_flush_tlb_area (unsigned long address, unsigned long end, int flags)
235 * Params : address Area start address
236 * : end Area end address
237 * : flags b0 = I-TLB as well
238 * Purpose : flush a TLB entry
239 */
240 .align 5
241 ENTRY(cpu_sa110_flush_tlb_area)
242 ENTRY(cpu_sa1100_flush_tlb_area)
243 mov r3, #0
244 mcr p15, 0, r3, c7, c10, 4 @ drain WB
245 1: cmp r0, r1
246 mcrlt p15, 0, r0, c8, c6, 1 @ flush D TLB entry
247 addlt r0, r0, #4096
248 cmp r0, r1
249 mcrlt p15, 0, r0, c8, c6, 1 @ flush D TLB entry
250 addlt r0, r0, #4096
251 blt 1b
252 teq r2, #0
253 mcrne p15, 0, r3, c8, c5, 0 @ flush I TLB
254 mov pc, lr
256 /*
257 * Function: sa110_flush_tlb_page (unsigned long address, int flags)
258 * Params : address Address to flush
259 * : flags b0 = I-TLB as well
260 * Purpose : flush a TLB entry
261 */
262 .align 5
263 ENTRY(cpu_sa110_flush_tlb_page)
264 ENTRY(cpu_sa1100_flush_tlb_page)
265 mov r3, #0
266 mcr p15, 0, r3, c7, c10, 4 @ drain WB
267 mcr p15, 0, r0, c8, c6, 1 @ flush D TLB entry
268 teq r1, #0
269 mcrne p15, 0, r3, c8, c5, 0 @ flush I TLB
270 mov pc, lr
272 /*
273 * Function: sa110_flush_icache_area (unsigned long address, unsigned long size)
274 * Params : address Address of area to flush
275 * : size Size of area to flush
276 * Purpose : flush an area from the Icache
277 */
278 .align 5
279 ENTRY(cpu_sa110_flush_icache_area)
280 ENTRY(cpu_sa1100_flush_icache_area)
281 1: mcr p15, 0, r0, c7, c10, 1 @ Clean D entry
282 add r0, r0, #32
283 subs r1, r1, #32
284 bhi 1b
285 mov r0, #0
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
287 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
288 mov pc, lr
290 .align 5
291 ENTRY(cpu_sa110_flush_icache_page)
292 ENTRY(cpu_sa1100_flush_icache_page)
293 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
294 mov pc, lr
296 /*
297 * Function: sa110_data_abort ()
298 * Params : r0 = address of aborted instruction
299 * Purpose : obtain information about current aborted instruction
300 * Returns : r0 = address of abort
301 * : r1 = FSR
302 * : r2 != 0 if writing
303 */
304 .align 5
305 ENTRY(cpu_sa110_data_abort)
306 ENTRY(cpu_sa1100_data_abort)
307 ldr r2, [r0] @ read instruction causing problem
308 mrc p15, 0, r0, c6, c0, 0 @ get FAR
309 mov r2, r2, lsr #19 @ b1 = L
310 and r3, r2, #0x69 << 2
311 and r2, r2, #2
312 mrc p15, 0, r1, c5, c0, 0 @ get FSR
313 and r1, r1, #255
314 mov pc, lr
316 .align 5
317 /*
318 * Function: sa110_set_pgd(unsigned long pgd_phys)
319 * Params : pgd_phys Physical address of page table
320 * Purpose : Perform a task switch, saving the old processes state, and restoring
321 * the new.
322 */
323 .align 5
324 ENTRY(cpu_sa110_set_pgd)
325 ldr r3, =Lclean_switch
326 ldr ip, =FLUSH_BASE
327 ldr r2, [r3]
328 ands r2, r2, #1
329 eor r2, r2, #1
330 str r2, [r3]
331 addne ip, ip, #FLUSH_OFFSET
332 flush_110_dcache r3, ip, r1
333 mov r1, #0
334 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
335 mcr p15, 0, r1, c7, c10, 4 @ drain WB
336 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
337 mcr p15, 0, r1, c8, c7, 0 @ flush TLBs
338 mov pc, lr
340 .align 5
341 ENTRY(cpu_sa1100_set_pgd)
342 ldr r3, =Lclean_switch
343 ldr ip, =FLUSH_BASE
344 ldr r2, [r3]
345 ands r2, r2, #1
346 eor r2, r2, #1
347 str r2, [r3]
348 addne ip, ip, #FLUSH_OFFSET
349 flush_1100_dcache r3, ip, r1
350 mov r1, #0
351 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
352 mcr p15, 0, r1, c7, c10, 4 @ drain WB
353 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
354 mcr p15, 0, r1, c8, c7, 0 @ flush TLBs
355 mov pc, lr
357 /*
358 * Function: sa110_set_pmd(pmd_t *pmdp, pmd_t pmd)
359 * Params : r0 = Address to set
360 * : r1 = value to set
361 * Purpose : Set a PMD and flush it out
362 */
363 .align 5
364 ENTRY(cpu_sa110_set_pmd)
365 ENTRY(cpu_sa1100_set_pmd)
366 str r1, [r0]
367 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
368 mcr p15, 0, r0, c7, c10, 4 @ drain WB
369 mov pc, lr
371 /*
372 * Function: sa110_set_pte(pte_t *ptep, pte_t pte)
373 * Params : r0 = Address to set
374 * : r1 = value to set
375 * Purpose : Set a PTE and flush it out
376 */
377 .align 5
378 ENTRY(cpu_sa110_set_pte)
379 ENTRY(cpu_sa1100_set_pte)
380 str r1, [r0], #-1024 @ linux version
382 eor r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
384 bic r2, r1, #0xff0
385 bic r2, r2, #3
386 orr r2, r2, #HPTE_TYPE_SMALL
388 tst r1, #LPTE_USER | LPTE_EXEC @ User or Exec?
389 orrne r2, r2, #HPTE_AP_READ
391 tst r1, #LPTE_WRITE | LPTE_DIRTY @ Write and Dirty?
392 orreq r2, r2, #HPTE_AP_WRITE
394 tst r1, #LPTE_PRESENT | LPTE_YOUNG @ Present and Young?
395 movne r2, #0
397 str r2, [r0] @ hardware version
398 mov r0, r0
399 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
400 mcr p15, 0, r0, c7, c10, 4 @ drain WB
401 mov pc, lr
403 /*
404 * Function: sa110_check_bugs (void)
405 * : sa110_proc_init (void)
406 * : sa110_proc_fin (void)
407 * Notes : This processor does not require these
408 */
409 ENTRY(cpu_sa110_check_bugs)
410 ENTRY(cpu_sa1100_check_bugs)
411 mrs ip, cpsr
412 bic ip, ip, #F_BIT
413 msr cpsr, ip
414 mov pc, lr
416 ENTRY(cpu_sa110_proc_init)
417 ENTRY(cpu_sa1100_proc_init)
418 mov r0, #0
419 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
420 mov pc, lr
422 ENTRY(cpu_sa110_proc_fin)
423 ENTRY(cpu_sa1100_proc_fin)
424 mrs r0, cpsr
425 orr r0, r0, #F_BIT | I_BIT
426 msr cpsr, r0
427 mov r0, #0
428 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
429 mrc p15, 0, r0, c1, c0, 0
430 bic r0, r0, #0x1100 @ ...i...s........
431 bic r0, r0, #0x000e @ ............wca.
432 mcr p15, 0, r0, c1, c0, 0 @ disable caches
433 mov pc, lr
435 .align 5
436 ENTRY(cpu_sa110_do_idle)
437 ENTRY(cpu_sa1100_do_idle)
438 mov r0, #0
439 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
440 ldr r1, =FLUSH_BASE+FLUSH_OFFSET*2 @ load from uncacheable loc
441 ldr r1, [r1, #0]
442 b 1f
444 .align 5
445 1: mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt
446 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
447 mov pc, lr
449 /*
450 * Function: sa110_reset
451 * Notes : This sets up everything for a reset
452 */
453 ENTRY(cpu_sa110_reset)
454 ENTRY(cpu_sa1100_reset)
455 stmfd sp!, {r1, lr}
456 bl cpu_sa110_flush_cache_all
457 bl cpu_sa110_flush_tlb_all
458 mcr p15, 0, ip, c7, c7, 0 @ flush I,D caches
459 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
460 bic r0, r0, #0x000f @ ............wcam
461 bic r0, r0, #0x1100 @ ...i...s........
462 ldmfd sp!, {r1, pc}
463 /*
464 * Purpose : Function pointers used to access above functions - all calls
465 * come through these
466 */
468 cpu_manu_name: .asciz "Intel"
469 ENTRY(cpu_sa110_name)
470 .asciz "StrongARM-110"
471 ENTRY(cpu_sa1100_name)
472 .asciz "StrongARM-1100"
473 .align
475 .section ".text.init", #alloc, #execinstr
477 __sa110_setup: mov r0, #0
478 mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4
479 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
480 mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4
481 mcr p15, 0, r4, c2, c0 @ load page table pointer
482 mov r0, #0x1f @ Domains 0, 1 = client
483 mcr p15, 0, r0, c3, c0 @ load domain access register
484 mrc p15, 0, r0, c1, c0 @ get control register v4
485 bic r0, r0, #0x0e00 @ ....??r.........
486 bic r0, r0, #0x0002 @ ..............a.
487 orr r0, r0, #0x003d @ ..........DPWC.M
488 orr r0, r0, #0x1100 @ ...I...S........
489 mov pc, lr
491 .type sa110_processor_functions, #object
492 ENTRY(sa110_processor_functions)
493 .word cpu_sa110_data_abort
494 .word cpu_sa110_check_bugs
495 .word cpu_sa110_proc_init
496 .word cpu_sa110_proc_fin
497 .word cpu_sa110_flush_cache_all
498 .word cpu_sa110_flush_cache_area
499 .word cpu_sa110_flush_cache_entry
500 .word cpu_sa110_clean_cache_area
501 .word cpu_sa110_flush_ram_page
502 .word cpu_sa110_flush_tlb_all
503 .word cpu_sa110_flush_tlb_area
504 .word cpu_sa110_set_pgd
505 .word cpu_sa110_set_pmd
506 .word cpu_sa110_set_pte
507 .word cpu_sa110_reset
508 .word cpu_sa110_flush_icache_area
509 .word cpu_sa110_cache_wback_area
510 .word cpu_sa110_cache_purge_area
511 .word cpu_sa110_flush_tlb_page
512 .word cpu_sa110_do_idle
513 .word cpu_sa110_flush_icache_page
514 .size sa110_processor_functions, . - sa110_processor_functions
516 .type cpu_sa110_info, #object
517 cpu_sa110_info:
518 .long cpu_manu_name
519 .long cpu_sa110_name
520 .size cpu_sa110_info, . - cpu_sa110_info
523 .type sa1100_processor_functions, #object
524 ENTRY(sa1100_processor_functions)
525 .word cpu_sa1100_data_abort
526 .word cpu_sa1100_check_bugs
527 .word cpu_sa1100_proc_init
528 .word cpu_sa1100_proc_fin
529 .word cpu_sa1100_flush_cache_all
530 .word cpu_sa1100_flush_cache_area
531 .word cpu_sa1100_flush_cache_entry
532 .word cpu_sa1100_clean_cache_area
533 .word cpu_sa1100_flush_ram_page
534 .word cpu_sa1100_flush_tlb_all
535 .word cpu_sa1100_flush_tlb_area
536 .word cpu_sa1100_set_pgd
537 .word cpu_sa1100_set_pmd
538 .word cpu_sa1100_set_pte
539 .word cpu_sa1100_reset
540 .word cpu_sa1100_flush_icache_area
541 .word cpu_sa1100_cache_wback_area
542 .word cpu_sa1100_cache_purge_area
543 .word cpu_sa1100_flush_tlb_page
544 .word cpu_sa1100_do_idle
545 .word cpu_sa1100_flush_icache_page
546 .size sa1100_processor_functions, . - sa1100_processor_functions
548 cpu_sa1100_info:
549 .long cpu_manu_name
550 .long cpu_sa1100_name
551 .size cpu_sa1100_info, . - cpu_sa1100_info
553 .type cpu_arch_name, #object
554 cpu_arch_name: .asciz "armv4"
555 .size cpu_arch_name, . - cpu_arch_name
557 .type cpu_elf_name, #object
558 cpu_elf_name: .asciz "v4"
559 .size cpu_elf_name, . - cpu_elf_name
560 .align
562 .section ".proc.info", #alloc, #execinstr
564 .type __sa110_proc_info,#object
565 __sa110_proc_info:
566 .long 0x4401a100
567 .long 0xfffffff0
568 .long 0x00000c02
569 b __sa110_setup
570 .long cpu_arch_name
571 .long cpu_elf_name
572 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
573 .long cpu_sa110_info
574 .long sa110_processor_functions
575 .size __sa110_proc_info, . - __sa110_proc_info
577 .type __sa1100_proc_info,#object
578 __sa1100_proc_info:
579 .long 0x4401a110
580 .long 0xfffffff0
581 .long 0x00000c02
582 b __sa110_setup
583 .long cpu_arch_name
584 .long cpu_elf_name
585 .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
586 .long cpu_sa1100_info
587 .long sa1100_processor_functions
588 .size __sa1100_proc_info, . - __sa1100_proc_info