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Import 2.3.47pre4
[davej-history.git] / arch / alpha / kernel / sys_dp264.c
blob70bb674dae56e6141f3f5637add23e3514a6bd06
1 /*
2 * linux/arch/alpha/kernel/sys_dp264.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Code supporting the DP264 (EV6+TSUNAMI).
9 */
10
11 #include <linux/config.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19
20 #include <asm/ptrace.h>
21 #include <asm/system.h>
22 #include <asm/dma.h>
23 #include <asm/irq.h>
24 #include <asm/bitops.h>
25 #include <asm/mmu_context.h>
26 #include <asm/io.h>
27 #include <asm/pgtable.h>
28 #include <asm/core_tsunami.h>
29 #include <asm/hwrpb.h>
30
31 #include "proto.h"
32 #include <asm/hw_irq.h>
33 #include "pci_impl.h"
34 #include "machvec_impl.h"
35
36
37 /*
38 * HACK ALERT! only the boot cpu is used for interrupts.
39 */
40
41 static void enable_tsunami_irq(unsigned int irq);
42 static void disable_tsunami_irq(unsigned int irq);
43 static void enable_clipper_irq(unsigned int irq);
44 static void disable_clipper_irq(unsigned int irq);
45
46 #define end_tsunami_irq enable_tsunami_irq
47 #define shutdown_tsunami_irq disable_tsunami_irq
48 #define mask_and_ack_tsunami_irq disable_tsunami_irq
49
50 #define end_clipper_irq enable_clipper_irq
51 #define shutdown_clipper_irq disable_clipper_irq
52 #define mask_and_ack_clipper_irq disable_clipper_irq
53
54
55 static unsigned int
56 startup_tsunami_irq(unsigned int irq)
57 {
58 enable_tsunami_irq(irq);
59 return 0; /* never anything pending */
60 }
61
62 static unsigned int
63 startup_clipper_irq(unsigned int irq)
64 {
65 enable_clipper_irq(irq);
66 return 0; /* never anything pending */
67 }
68
69 static struct hw_interrupt_type tsunami_irq_type = {
70 "TSUNAMI",
71 startup_tsunami_irq,
72 shutdown_tsunami_irq,
73 enable_tsunami_irq,
74 disable_tsunami_irq,
75 mask_and_ack_tsunami_irq,
76 end_tsunami_irq
77 };
78
79 static struct hw_interrupt_type clipper_irq_type = {
80 "CLIPPER",
81 startup_clipper_irq,
82 shutdown_clipper_irq,
83 enable_clipper_irq,
84 disable_clipper_irq,
85 mask_and_ack_clipper_irq,
86 end_clipper_irq
87 };
88
89 static unsigned long cached_irq_mask;
90
91 #define TSUNAMI_SET_IRQ_MASK(cpu, value) \
92 do { \
93 volatile unsigned long *csr; \
94 \
95 csr = &TSUNAMI_cchip->dim##cpu##.csr; \
96 *csr = (value); \
97 mb(); \
98 *csr; \
99 } while(0)
100
101 static inline void
102 do_flush_irq_mask(unsigned long value)
103 {
104 switch (TSUNAMI_bootcpu)
105 {
106 case 0:
107 TSUNAMI_SET_IRQ_MASK(0, value);
108 break;
109 case 1:
110 TSUNAMI_SET_IRQ_MASK(1, value);
111 break;
112 case 2:
113 TSUNAMI_SET_IRQ_MASK(2, value);
114 break;
115 case 3:
116 TSUNAMI_SET_IRQ_MASK(3, value);
117 break;
118 }
119 }
120
121 #ifdef CONFIG_SMP
122 static inline void
123 do_flush_smp_irq_mask(unsigned long value)
124 {
125 extern unsigned long cpu_present_mask;
126 unsigned long other_cpus = cpu_present_mask & ~(1L << TSUNAMI_bootcpu);
127
128 if (other_cpus & 1)
129 TSUNAMI_SET_IRQ_MASK(0, value);
130 if (other_cpus & 2)
131 TSUNAMI_SET_IRQ_MASK(1, value);
132 if (other_cpus & 4)
133 TSUNAMI_SET_IRQ_MASK(2, value);
134 if (other_cpus & 8)
135 TSUNAMI_SET_IRQ_MASK(3, value);
136 }
137 #endif
138
139 static void
140 dp264_flush_irq_mask(unsigned long mask)
141 {
142 unsigned long value;
143
144 #ifdef CONFIG_SMP
145 do_flush_smp_irq_mask(mask);
146 #endif
147
148 value = mask | (1UL << 55) | 0xffff; /* isa irqs always enabled */
149 do_flush_irq_mask(value);
150 }
151
152 static void
153 enable_tsunami_irq(unsigned int irq)
154 {
155 cached_irq_mask |= 1UL << irq;
156 dp264_flush_irq_mask(cached_irq_mask);
157 }
158
159 static void
160 disable_tsunami_irq(unsigned int irq)
161 {
162 cached_irq_mask &= ~(1UL << irq);
163 dp264_flush_irq_mask(cached_irq_mask);
164 }
165
166 static void
167 clipper_flush_irq_mask(unsigned long mask)
168 {
169 unsigned long value;
170
171 value = mask >> 16;
172 #ifdef CONFIG_SMP
173 do_flush_smp_irq_mask(value);
174 #endif
175
176 value = value | (1UL << 55); /* master ISA enable */
177 do_flush_irq_mask(value);
178 }
179
180 static void
181 enable_clipper_irq(unsigned int irq)
182 {
183 cached_irq_mask |= 1UL << irq;
184 clipper_flush_irq_mask(cached_irq_mask);
185 }
186
187 static void
188 disable_clipper_irq(unsigned int irq)
189 {
190 cached_irq_mask &= ~(1UL << irq);
191 clipper_flush_irq_mask(cached_irq_mask);
192 }
193
194 static void
195 dp264_device_interrupt(unsigned long vector, struct pt_regs * regs)
196 {
197 #if 1
198 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!! \n");
199 #else
200 unsigned long pld;
201 unsigned int i;
202
203 /* Read the interrupt summary register of TSUNAMI */
204 pld = TSUNAMI_cchip->dir0.csr;
205
206 /*
207 * Now for every possible bit set, work through them and call
208 * the appropriate interrupt handler.
209 */
210 while (pld) {
211 i = ffz(~pld);
212 pld &= pld - 1; /* clear least bit set */
213 if (i == 55)
214 isa_device_interrupt(vector, regs);
215 else
216 handle_irq(16 + i, 16 + i, regs);
217 #if 0
218 TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
219 tmp = TSUNAMI_cchip->dir0.csr;
220 #endif
221 }
222 #endif
223 }
224
225 static void
226 dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
227 {
228 int irq;
229
230 irq = (vector - 0x800) >> 4;
231
232 /*
233 * The SRM console reports PCI interrupts with a vector calculated by:
234 *
235 * 0x900 + (0x10 * DRIR-bit)
236 *
237 * So bit 16 shows up as IRQ 32, etc.
238 *
239 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
240 * that many of the low order bits of the DRIR are not used, and
241 * so we don't count them.
242 */
243 if (irq >= 32)
244 irq -= 16;
245
246 handle_irq(irq, regs);
247 }
248
249 static void
250 clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
251 {
252 int irq;
253
254 irq = (vector - 0x800) >> 4;
255
256 /*
257 * The SRM console reports PCI interrupts with a vector calculated by:
258 *
259 * 0x900 + (0x10 * DRIR-bit)
260 *
261 * So bit 16 shows up as IRQ 32, etc.
262 *
263 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
264 * to scale down the vector reported, we just use it.
265 *
266 * Eg IRQ 24 is DRIR bit 8, etc, etc
267 */
268 handle_irq(irq, regs);
269 }
270
271 static void __init
272 init_TSUNAMI_irqs(struct hw_interrupt_type * ops)
273 {
274 int i;
275
276 for (i = 0; i < NR_IRQS; i++) {
277 if (i == RTC_IRQ)
278 continue;
279 if (i < 16)
280 continue;
281 /* only irqs between 16 and 47 are tsunami irqs */
282 if (i >= 48)
283 break;
284 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
285 irq_desc[i].handler = ops;
286 }
287 }
288
289 static void __init
290 dp264_init_irq(void)
291 {
292 outb(0, DMA1_RESET_REG);
293 outb(0, DMA2_RESET_REG);
294 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
295 outb(0, DMA2_MASK_REG);
296
297 if (alpha_using_srm)
298 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
299
300 init_ISA_irqs();
301 init_RTC_irq();
302 init_TSUNAMI_irqs(&tsunami_irq_type);
303
304 dp264_flush_irq_mask(0UL);
305 }
306
307 static void __init
308 clipper_init_irq(void)
309 {
310 outb(0, DMA1_RESET_REG);
311 outb(0, DMA2_RESET_REG);
312 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
313 outb(0, DMA2_MASK_REG);
314
315 if (alpha_using_srm)
316 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
317
318 init_ISA_irqs();
319 init_RTC_irq();
320 init_TSUNAMI_irqs(&clipper_irq_type);
321
322 clipper_flush_irq_mask(0UL);
323 }
324
325
326 /*
327 * PCI Fixup configuration.
328 *
329 * Summary @ TSUNAMI_CSR_DIM0:
330 * Bit Meaning
331 * 0-17 Unused
332 *18 Interrupt SCSI B (Adaptec 7895 builtin)
333 *19 Interrupt SCSI A (Adaptec 7895 builtin)
334 *20 Interrupt Line D from slot 2 PCI0
335 *21 Interrupt Line C from slot 2 PCI0
336 *22 Interrupt Line B from slot 2 PCI0
337 *23 Interrupt Line A from slot 2 PCI0
338 *24 Interrupt Line D from slot 1 PCI0
339 *25 Interrupt Line C from slot 1 PCI0
340 *26 Interrupt Line B from slot 1 PCI0
341 *27 Interrupt Line A from slot 1 PCI0
342 *28 Interrupt Line D from slot 0 PCI0
343 *29 Interrupt Line C from slot 0 PCI0
344 *30 Interrupt Line B from slot 0 PCI0
345 *31 Interrupt Line A from slot 0 PCI0
346 *
347 *32 Interrupt Line D from slot 3 PCI1
348 *33 Interrupt Line C from slot 3 PCI1
349 *34 Interrupt Line B from slot 3 PCI1
350 *35 Interrupt Line A from slot 3 PCI1
351 *36 Interrupt Line D from slot 2 PCI1
352 *37 Interrupt Line C from slot 2 PCI1
353 *38 Interrupt Line B from slot 2 PCI1
354 *39 Interrupt Line A from slot 2 PCI1
355 *40 Interrupt Line D from slot 1 PCI1
356 *41 Interrupt Line C from slot 1 PCI1
357 *42 Interrupt Line B from slot 1 PCI1
358 *43 Interrupt Line A from slot 1 PCI1
359 *44 Interrupt Line D from slot 0 PCI1
360 *45 Interrupt Line C from slot 0 PCI1
361 *46 Interrupt Line B from slot 0 PCI1
362 *47 Interrupt Line A from slot 0 PCI1
363 *48-52 Unused
364 *53 PCI0 NMI (from Cypress)
365 *54 PCI0 SMI INT (from Cypress)
366 *55 PCI0 ISA Interrupt (from Cypress)
367 *56-60 Unused
368 *61 PCI1 Bus Error
369 *62 PCI0 Bus Error
370 *63 Reserved
371 *
372 * IdSel
373 * 5 Cypress Bridge I/O
374 * 6 SCSI Adaptec builtin
375 * 7 64 bit PCI option slot 0 (all busses)
376 * 8 64 bit PCI option slot 1 (all busses)
377 * 9 64 bit PCI option slot 2 (all busses)
378 * 10 64 bit PCI option slot 3 (not bus 0)
379 */
380
381 static int __init
382 dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
383 {
384 static char irq_tab[6][5] __initlocaldata = {
385 /*INT INTA INTB INTC INTD */
386 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
387 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
388 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
389 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
390 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
391 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
392 };
393 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
394
395 struct pci_controler *hose = dev->sysdata;
396 int irq = COMMON_TABLE_LOOKUP;
397
398 if (irq > 0) {
399 irq += 16 * hose->index;
400 } else {
401 /* ??? The Contaq IDE controler on the ISA bridge uses
402 "legacy" interrupts 14 and 15. I don't know if anything
403 can wind up at the same slot+pin on hose1, so we'll
404 just have to trust whatever value the console might
405 have assigned. */
406
407 u8 irq8;
408 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
409 irq = irq8;
410 }
411
412 return irq;
413 }
414
415 static int __init
416 monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
417 {
418 static char irq_tab[13][5] __initlocaldata = {
419 /*INT INTA INTB INTC INTD */
420 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
421 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
422 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
423 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
424 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
425 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
426 #if 1
427 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
428 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
429 #else
430 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
431 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
432 #endif
433 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
434 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
435 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
436 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
437 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
438 };
439 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
440 return COMMON_TABLE_LOOKUP;
441 }
442
443 static u8 __init
444 monet_swizzle(struct pci_dev *dev, u8 *pinp)
445 {
446 struct pci_controler *hose = dev->sysdata;
447 int slot, pin = *pinp;
448
449 if (hose->first_busno == dev->bus->number) {
450 slot = PCI_SLOT(dev->devfn);
451 }
452 /* Check for the built-in bridge on hose 1. */
453 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
454 slot = PCI_SLOT(dev->devfn);
455 } else {
456 /* Must be a card-based bridge. */
457 do {
458 /* Check for built-in bridge on hose 1. */
459 if (hose->index == 1 &&
460 PCI_SLOT(dev->bus->self->devfn) == 8) {
461 slot = PCI_SLOT(dev->devfn);
462 break;
463 }
464 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
465
466 /* Move up the chain of bridges. */
467 dev = dev->bus->self;
468 /* Slot of the next bridge. */
469 slot = PCI_SLOT(dev->devfn);
470 } while (dev->bus->self);
471 }
472 *pinp = pin;
473 return slot;
474 }
475
476 static int __init
477 webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
478 {
479 static char irq_tab[13][5] __initlocaldata = {
480 /*INT INTA INTB INTC INTD */
481 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
482 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
483 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
484 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
485 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
486 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
487 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
488 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
489 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
490 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
491 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
492 };
493 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
494 return COMMON_TABLE_LOOKUP;
495 }
496
497 static int __init
498 clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
499 {
500 static char irq_tab[7][5] __initlocaldata = {
501 /*INT INTA INTB INTC INTD */
502 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
503 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
504 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
505 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
506 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
507 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
508 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
509 };
510 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
511
512 struct pci_controler *hose = dev->sysdata;
513 int irq = COMMON_TABLE_LOOKUP;
514
515 if (irq > 0)
516 irq += 16 * hose->index;
517
518 return irq;
519 }
520
521 static void __init
522 dp264_init_pci(void)
523 {
524 common_init_pci();
525 SMC669_Init(0);
526 }
527
528 static void __init
529 monet_init_pci(void)
530 {
531 common_init_pci();
532 SMC669_Init(1);
533 es1888_init();
534 }
535
536
537 /*
538 * The System Vectors
539 */
540
541 struct alpha_machine_vector dp264_mv __initmv = {
542 vector_name: "DP264",
543 DO_EV6_MMU,
544 DO_DEFAULT_RTC,
545 DO_TSUNAMI_IO,
546 DO_TSUNAMI_BUS,
547 machine_check: tsunami_machine_check,
548 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
549 min_io_address: DEFAULT_IO_BASE,
550 min_mem_address: DEFAULT_MEM_BASE,
551
552 nr_irqs: 64,
553 device_interrupt: dp264_device_interrupt,
554
555 init_arch: tsunami_init_arch,
556 init_irq: dp264_init_irq,
557 init_pit: common_init_pit,
558 init_pci: dp264_init_pci,
559 kill_arch: tsunami_kill_arch,
560 pci_map_irq: dp264_map_irq,
561 pci_swizzle: common_swizzle,
562 };
563 ALIAS_MV(dp264)
564
565 struct alpha_machine_vector monet_mv __initmv = {
566 vector_name: "Monet",
567 DO_EV6_MMU,
568 DO_DEFAULT_RTC,
569 DO_TSUNAMI_IO,
570 DO_TSUNAMI_BUS,
571 machine_check: tsunami_machine_check,
572 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
573 min_io_address: DEFAULT_IO_BASE,
574 min_mem_address: DEFAULT_MEM_BASE,
575
576 nr_irqs: 64,
577 device_interrupt: dp264_device_interrupt,
578
579 init_arch: tsunami_init_arch,
580 init_irq: dp264_init_irq,
581 init_pit: common_init_pit,
582 init_pci: monet_init_pci,
583 kill_arch: tsunami_kill_arch,
584 pci_map_irq: monet_map_irq,
585 pci_swizzle: monet_swizzle,
586 };
587
588 struct alpha_machine_vector webbrick_mv __initmv = {
589 vector_name: "Webbrick",
590 DO_EV6_MMU,
591 DO_DEFAULT_RTC,
592 DO_TSUNAMI_IO,
593 DO_TSUNAMI_BUS,
594 machine_check: tsunami_machine_check,
595 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
596 min_io_address: DEFAULT_IO_BASE,
597 min_mem_address: DEFAULT_MEM_BASE,
598
599 nr_irqs: 64,
600 device_interrupt: dp264_device_interrupt,
601
602 init_arch: tsunami_init_arch,
603 init_irq: dp264_init_irq,
604 init_pit: common_init_pit,
605 init_pci: common_init_pci,
606 kill_arch: tsunami_kill_arch,
607 pci_map_irq: webbrick_map_irq,
608 pci_swizzle: common_swizzle,
609 };
610
611 struct alpha_machine_vector clipper_mv __initmv = {
612 vector_name: "Clipper",
613 DO_EV6_MMU,
614 DO_DEFAULT_RTC,
615 DO_TSUNAMI_IO,
616 DO_TSUNAMI_BUS,
617 machine_check: tsunami_machine_check,
618 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
619 min_io_address: DEFAULT_IO_BASE,
620 min_mem_address: DEFAULT_MEM_BASE,
621
622 nr_irqs: 64,
623 device_interrupt: dp264_device_interrupt,
624
625 init_arch: tsunami_init_arch,
626 init_irq: clipper_init_irq,
627 init_pit: common_init_pit,
628 init_pci: common_init_pci,
629 kill_arch: tsunami_kill_arch,
630 pci_map_irq: clipper_map_irq,
631 pci_swizzle: common_swizzle,
632 };
633
634 /* No alpha_mv alias for webbrick/monet/clipper, since we compile them
635 in unconditionally with DP264; setup_arch knows how to cope. */
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux