include/asm-sparc/cache.h

   1 /* $Id: cache.h,v 1.8 1999/03/11 00:14:45 davem Exp $
   2  * cache.h:  Cache specific code for the Sparc.  These include flushing
   3  *           and direct tag/data line access.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef _SPARC_CACHE_H
   9 #define _SPARC_CACHE_H
  10
  11 #include <asm/asi.h>
  12
  13 #define L1_CACHE_BYTES 32
  14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
  15
  16 #define SMP_CACHE_BYTES 32
  17
  18 /* Direct access to the instruction cache is provided through and
  19  * alternate address space.  The IDC bit must be off in the ICCR on
  20  * HyperSparcs for these accesses to work.  The code below does not do
  21  * any checking, the caller must do so.  These routines are for
  22  * diagnostics only, but could end up being useful.  Use with care.
  23  * Also, you are asking for trouble if you execute these in one of the
  24  * three instructions following a %asr/%psr access or modification.
  25  */
  26
  27 /* First, cache-tag access. */
  28 extern __inline__ unsigned int get_icache_tag(int setnum, int tagnum)
  29 {
  30         unsigned int vaddr, retval;
  31
  32         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  33         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
  34                              "=r" (retval) :
  35                              "r" (vaddr), "i" (ASI_M_TXTC_TAG));
  36         return retval;
  37 }
  38
  39 extern __inline__ void put_icache_tag(int setnum, int tagnum, unsigned int entry)
  40 {
  41         unsigned int vaddr;
  42
  43         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  44         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
  45                              "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
  46                              "memory");
  47 }
  48
  49 /* Second cache-data access.  The data is returned two-32bit quantities
  50  * at a time.
  51  */
  52 extern __inline__ void get_icache_data(int setnum, int tagnum, int subblock,
  53                                        unsigned int *data)
  54 {
  55         unsigned int value1, value2, vaddr;
  56
  57         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  58                 ((subblock&0x3) << 3);
  59         __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
  60                              "or %%g0, %%g2, %0\n\t"
  61                              "or %%g0, %%g3, %1\n\t" :
  62                              "=r" (value1), "=r" (value2) :
  63                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  64                              "g2", "g3");
  65         data[0] = value1; data[1] = value2;
  66 }
  67
  68 extern __inline__ void put_icache_data(int setnum, int tagnum, int subblock,
  69                                        unsigned int *data)
  70 {
  71         unsigned int value1, value2, vaddr;
  72
  73         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  74                 ((subblock&0x3) << 3);
  75         value1 = data[0]; value2 = data[1];
  76         __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
  77                              "or %%g0, %1, %%g3\n\t"
  78                              "stda %%g2, [%2] %3\n\t" : :
  79                              "r" (value1), "r" (value2),
  80                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  81                              "g2", "g3", "memory" /* no joke */);
  82 }
  83
  84 /* Different types of flushes with the ICACHE.  Some of the flushes
  85  * affect both the ICACHE and the external cache.  Others only clear
  86  * the ICACHE entries on the cpu itself.  V8's (most) allow
  87  * granularity of flushes on the packet (element in line), whole line,
  88  * and entire cache (ie. all lines) level.  The ICACHE only flushes are
  89  * ROSS HyperSparc specific and are in ross.h
  90  */
  91
  92 /* Flushes which clear out both the on-chip and external caches */
  93 extern __inline__ void flush_ei_page(unsigned int addr)
  94 {
  95         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
  96                              "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
  97                              "memory");
  98 }
  99
 100 extern __inline__ void flush_ei_seg(unsigned int addr)
 101 {
 102         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 103                              "r" (addr), "i" (ASI_M_FLUSH_SEG) :
 104                              "memory");
 105 }
 106
 107 extern __inline__ void flush_ei_region(unsigned int addr)
 108 {
 109         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 110                              "r" (addr), "i" (ASI_M_FLUSH_REGION) :
 111                              "memory");
 112 }
 113
 114 extern __inline__ void flush_ei_ctx(unsigned int addr)
 115 {
 116         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 117                              "r" (addr), "i" (ASI_M_FLUSH_CTX) :
 118                              "memory");
 119 }
 120
 121 extern __inline__ void flush_ei_user(unsigned int addr)
 122 {
 123         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 124                              "r" (addr), "i" (ASI_M_FLUSH_USER) :
 125                              "memory");
 126 }
 127
 128 #endif /* !(_SPARC_CACHE_H) */