1 /* $Id: hfc_2bds0.c,v 1.8 1998/11/15 23:54:40 keil Exp $
3 * specific routines for CCD's HFC 2BDS0
5 * Author Karsten Keil (keil@temic-ech.spacenet.de)
8 * $Log: hfc_2bds0.c,v $
9 * Revision 1.8 1998/11/15 23:54:40 keil
12 * Revision 1.7 1998/09/30 22:24:45 keil
13 * Fix missing line in setstack*
15 * Revision 1.6 1998/08/13 23:36:26 keil
16 * HiSax 3.1 - don't work stable with current LinkLevel
18 * Revision 1.5 1998/06/27 22:52:58 keil
19 * make 16.3c working with 3.0
21 * Revision 1.4 1998/05/25 12:57:52 keil
22 * HiSax golden code from certification, Don't use !!!
23 * No leased lines, no X75, but many changes.
25 * Revision 1.3 1998/02/12 23:07:22 keil
26 * change for 2.1.86 (removing FREE_READ/FREE_WRITE from [dev]_kfree_skb()
28 * Revision 1.2 1998/02/02 13:26:13 keil
34 #define __NO_VERSION__
36 #include "hfc_2bds0.h"
38 #include <linux/interrupt.h>
44 #define byteout(addr,val) outb(val,addr)
45 #define bytein(addr) inb(addr)
48 dummyf(struct IsdnCardState
*cs
, u_char
* data
, int size
)
50 printk(KERN_WARNING
"HiSax: hfcd dummy fifo called\n");
54 ReadReg(struct IsdnCardState
*cs
, int data
, u_char reg
)
59 if (cs
->hw
.hfcD
.cip
!= reg
) {
60 cs
->hw
.hfcD
.cip
= reg
;
61 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
63 ret
= bytein(cs
->hw
.hfcD
.addr
);
65 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= 2))
66 debugl1(cs
, "t3c RD %02x %02x", reg
, ret
);
69 ret
= bytein(cs
->hw
.hfcD
.addr
| 1);
74 WriteReg(struct IsdnCardState
*cs
, int data
, u_char reg
, u_char value
)
76 if (cs
->hw
.hfcD
.cip
!= reg
) {
77 cs
->hw
.hfcD
.cip
= reg
;
78 byteout(cs
->hw
.hfcD
.addr
| 1, reg
);
81 byteout(cs
->hw
.hfcD
.addr
, value
);
83 if (cs
->debug
& L1_DEB_HSCX_FIFO
&& (data
!= HFCD_DATA_NODEB
))
84 debugl1(cs
, "t3c W%c %02x %02x", data
? 'D' : 'C', reg
, value
);
88 /* Interface functions */
91 readreghfcd(struct IsdnCardState
*cs
, u_char offset
)
93 return(ReadReg(cs
, HFCD_DATA
, offset
));
97 writereghfcd(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
99 WriteReg(cs
, HFCD_DATA
, offset
, value
);
103 set_cs_func(struct IsdnCardState
*cs
)
105 cs
->readisac
= &readreghfcd
;
106 cs
->writeisac
= &writereghfcd
;
107 cs
->readisacfifo
= &dummyf
;
108 cs
->writeisacfifo
= &dummyf
;
109 cs
->BC_Read_Reg
= &ReadReg
;
110 cs
->BC_Write_Reg
= &WriteReg
;
114 WaitForBusy(struct IsdnCardState
*cs
)
118 while (!(ReadReg(cs
, HFCD_DATA
, HFCD_STAT
) & HFCD_BUSY
) && to
) {
123 printk(KERN_WARNING
"HiSax: WaitForBusy timeout\n");
128 WaitNoBusy(struct IsdnCardState
*cs
)
133 while ((ReadReg(cs
, HFCD_STATUS
, HFCD_STATUS
) & HFCD_BUSY
) && to
) {
138 restore_flags(flags
);
141 printk(KERN_WARNING
"HiSax: WaitNoBusy timeout\n");
146 SelFiFo(struct IsdnCardState
*cs
, u_char FiFo
)
152 if (cs
->hw
.hfcD
.fifo
== FiFo
)
157 case 0: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B1
;
159 case 1: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B1
;
161 case 2: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_B2
;
163 case 3: cip
= HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_B2
;
165 case 4: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
;
167 case 5: cip
= HFCD_FIFO
| HFCD_Z1
| HFCD_REC
;
170 restore_flags(flags
);
171 debugl1(cs
, "SelFiFo Error");
174 cs
->hw
.hfcD
.fifo
= FiFo
;
176 cs
->BC_Write_Reg(cs
, HFCD_DATA
, cip
, 0);
179 restore_flags(flags
);
183 GetFreeFifoBytes_B(struct BCState
*bcs
)
187 if (bcs
->hw
.hfc
.f1
== bcs
->hw
.hfc
.f2
)
188 return (bcs
->cs
->hw
.hfcD
.bfifosize
);
189 s
= bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] - bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f2
];
191 s
+= bcs
->cs
->hw
.hfcD
.bfifosize
;
192 s
= bcs
->cs
->hw
.hfcD
.bfifosize
- s
;
197 GetFreeFifoBytes_D(struct IsdnCardState
*cs
)
201 if (cs
->hw
.hfcD
.f1
== cs
->hw
.hfcD
.f2
)
202 return (cs
->hw
.hfcD
.dfifosize
);
203 s
= cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] - cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f2
];
205 s
+= cs
->hw
.hfcD
.dfifosize
;
206 s
= cs
->hw
.hfcD
.dfifosize
- s
;
211 ReadZReg(struct IsdnCardState
*cs
, u_char reg
)
216 val
= 256 * ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_HIGH
);
218 val
+= ReadReg(cs
, HFCD_DATA
, reg
| HFCB_Z_LOW
);
223 hfc_sched_event(struct BCState
*bcs
, int event
)
225 bcs
->event
|= 1 << event
;
226 queue_task(&bcs
->tqueue
, &tq_immediate
);
227 mark_bh(IMMEDIATE_BH
);
230 static struct sk_buff
231 *hfc_empty_fifo(struct BCState
*bcs
, int count
)
235 struct IsdnCardState
*cs
= bcs
->cs
;
241 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
242 debugl1(cs
, "hfc_empty_fifo");
245 if (count
> HSCX_BUFMAX
+ 3) {
246 if (cs
->debug
& L1_DEB_WARN
)
247 debugl1(cs
, "hfc_empty_fifo: incoming packet too large");
248 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
249 while (idx
++ < count
) {
252 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
256 } else if (count
< 4) {
257 if (cs
->debug
& L1_DEB_WARN
)
258 debugl1(cs
, "hfc_empty_fifo: incoming packet too small");
259 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
261 while ((idx
++ < count
) && WaitNoBusy(cs
))
262 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
264 } else if (!(skb
= dev_alloc_skb(count
- 3)))
265 printk(KERN_WARNING
"HFC: receive out of memory\n");
267 ptr
= skb_put(skb
, count
- 3);
269 cip
= HFCB_FIFO
| HFCB_FIFO_OUT
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
271 while (idx
< (count
- 3)) {
275 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
280 if (idx
!= count
- 3) {
282 debugl1(cs
, "RFIFO BUSY error");
283 printk(KERN_WARNING
"HFC FIFO channel %d BUSY Error\n", bcs
->channel
);
289 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
291 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
293 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
295 if (cs
->debug
& L1_DEB_HSCX
)
296 debugl1(cs
, "hfc_empty_fifo %d chksum %x stat %x",
297 bcs
->channel
, chksum
, stat
);
299 debugl1(cs
, "FIFO CRC error");
309 stat
= ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F2_INC
|
310 HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
313 restore_flags(flags
);
318 hfc_fill_fifo(struct BCState
*bcs
)
320 struct IsdnCardState
*cs
= bcs
->cs
;
328 if (bcs
->tx_skb
->len
<= 0)
332 SelFiFo(cs
, HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
333 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
335 bcs
->hw
.hfc
.f1
= ReadReg(cs
, HFCD_DATA
, cip
);
337 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
339 bcs
->hw
.hfc
.f2
= ReadReg(cs
, HFCD_DATA
, cip
);
340 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
] = ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
342 if (cs
->debug
& L1_DEB_HSCX
)
343 debugl1(cs
, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
344 bcs
->channel
, bcs
->hw
.hfc
.f1
, bcs
->hw
.hfc
.f2
,
345 bcs
->hw
.hfc
.send
[bcs
->hw
.hfc
.f1
]);
346 fcnt
= bcs
->hw
.hfc
.f1
- bcs
->hw
.hfc
.f2
;
350 if (cs
->debug
& L1_DEB_HSCX
)
351 debugl1(cs
, "hfc_fill_fifo more as 30 frames");
352 restore_flags(flags
);
355 count
= GetFreeFifoBytes_B(bcs
);
356 if (cs
->debug
& L1_DEB_HSCX
)
357 debugl1(cs
, "hfc_fill_fifo %d count(%ld/%d),%lx",
358 bcs
->channel
, bcs
->tx_skb
->len
,
359 count
, current
->state
);
360 if (count
< bcs
->tx_skb
->len
) {
361 if (cs
->debug
& L1_DEB_HSCX
)
362 debugl1(cs
, "hfc_fill_fifo no fifo mem");
363 restore_flags(flags
);
366 cip
= HFCB_FIFO
| HFCB_FIFO_IN
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
);
371 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
++]);
372 while (idx
< bcs
->tx_skb
->len
) {
376 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, bcs
->tx_skb
->data
[idx
]);
380 if (idx
!= bcs
->tx_skb
->len
) {
382 debugl1(cs
, "FIFO Send BUSY error");
383 printk(KERN_WARNING
"HFC S FIFO channel %d BUSY Error\n", bcs
->channel
);
385 bcs
->tx_cnt
-= bcs
->tx_skb
->len
;
386 if (bcs
->st
->lli
.l1writewakeup
&&
387 (PACKET_NOACK
!= bcs
->tx_skb
->pkt_type
))
388 bcs
->st
->lli
.l1writewakeup(bcs
->st
, bcs
->tx_skb
->len
);
389 dev_kfree_skb(bcs
->tx_skb
);
395 ReadReg(cs
, HFCD_DATA
, HFCB_FIFO
| HFCB_F1_INC
| HFCB_SEND
| HFCB_CHANNEL(bcs
->channel
));
398 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
399 restore_flags(flags
);
404 hfc_send_data(struct BCState
*bcs
)
406 struct IsdnCardState
*cs
= bcs
->cs
;
408 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
410 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
412 debugl1(cs
,"send_data %d blocked", bcs
->channel
);
416 main_rec_2bds0(struct BCState
*bcs
)
419 struct IsdnCardState
*cs
= bcs
->cs
;
422 int receive
, count
= 5;
429 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
430 debugl1(cs
,"rec_data %d blocked", bcs
->channel
);
431 restore_flags(flags
);
434 SelFiFo(cs
, HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
435 cip
= HFCB_FIFO
| HFCB_F1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
437 f1
= ReadReg(cs
, HFCD_DATA
, cip
);
438 cip
= HFCB_FIFO
| HFCB_F2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
);
440 f2
= ReadReg(cs
, HFCD_DATA
, cip
);
443 if (cs
->debug
& L1_DEB_HSCX
)
444 debugl1(cs
, "hfc rec %d f1(%d) f2(%d)",
445 bcs
->channel
, f1
, f2
);
447 z1
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z1
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
448 z2
= ReadZReg(cs
, HFCB_FIFO
| HFCB_Z2
| HFCB_REC
| HFCB_CHANNEL(bcs
->channel
));
452 rcnt
+= cs
->hw
.hfcD
.bfifosize
;
454 if (cs
->debug
& L1_DEB_HSCX
)
455 debugl1(cs
, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
456 bcs
->channel
, z1
, z2
, rcnt
);
457 if ((skb
= hfc_empty_fifo(bcs
, rcnt
))) {
459 skb_queue_tail(&bcs
->rqueue
, skb
);
461 hfc_sched_event(bcs
, B_RCVBUFREADY
);
472 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
473 if (count
&& receive
)
475 restore_flags(flags
);
480 mode_2bs0(struct BCState
*bcs
, int mode
, int bc
)
482 struct IsdnCardState
*cs
= bcs
->cs
;
484 if (cs
->debug
& L1_DEB_HSCX
)
485 debugl1(cs
, "HFCD bchannel mode %d bchan %d/%d",
486 mode
, bc
, bcs
->channel
);
492 cs
->hw
.hfcD
.conn
|= 0x18;
493 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B2_ENA
;
495 cs
->hw
.hfcD
.conn
|= 0x3;
496 cs
->hw
.hfcD
.sctrl
&= ~SCTRL_B1_ENA
;
499 case (L1_MODE_TRANS
):
501 cs
->hw
.hfcD
.ctmt
|= 2;
502 cs
->hw
.hfcD
.conn
&= ~0x18;
503 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
505 cs
->hw
.hfcD
.ctmt
|= 1;
506 cs
->hw
.hfcD
.conn
&= ~0x3;
507 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
512 cs
->hw
.hfcD
.ctmt
&= ~2;
513 cs
->hw
.hfcD
.conn
&= ~0x18;
514 cs
->hw
.hfcD
.sctrl
|= SCTRL_B2_ENA
;
516 cs
->hw
.hfcD
.ctmt
&= ~1;
517 cs
->hw
.hfcD
.conn
&= ~0x3;
518 cs
->hw
.hfcD
.sctrl
|= SCTRL_B1_ENA
;
522 WriteReg(cs
, HFCD_DATA
, HFCD_SCTRL
, cs
->hw
.hfcD
.sctrl
);
523 WriteReg(cs
, HFCD_DATA
, HFCD_CTMT
, cs
->hw
.hfcD
.ctmt
);
524 WriteReg(cs
, HFCD_DATA
, HFCD_CONN
, cs
->hw
.hfcD
.conn
);
528 hfc_l2l1(struct PStack
*st
, int pr
, void *arg
)
530 struct sk_buff
*skb
= arg
;
534 case (PH_DATA
| REQUEST
):
537 if (st
->l1
.bcs
->tx_skb
) {
538 skb_queue_tail(&st
->l1
.bcs
->squeue
, skb
);
539 restore_flags(flags
);
541 st
->l1
.bcs
->tx_skb
= skb
;
542 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
543 */ st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
544 restore_flags(flags
);
547 case (PH_PULL
| INDICATION
):
548 if (st
->l1
.bcs
->tx_skb
) {
549 printk(KERN_WARNING
"hfc_l2l1: this shouldn't happen\n");
554 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
555 */ st
->l1
.bcs
->tx_skb
= skb
;
556 st
->l1
.bcs
->cs
->BC_Send_Data(st
->l1
.bcs
);
557 restore_flags(flags
);
559 case (PH_PULL
| REQUEST
):
560 if (!st
->l1
.bcs
->tx_skb
) {
561 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
562 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
564 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
566 case (PH_ACTIVATE
| REQUEST
):
567 test_and_set_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
568 mode_2bs0(st
->l1
.bcs
, st
->l1
.mode
, st
->l1
.bc
);
569 l1_msg_b(st
, pr
, arg
);
571 case (PH_DEACTIVATE
| REQUEST
):
572 l1_msg_b(st
, pr
, arg
);
574 case (PH_DEACTIVATE
| CONFIRM
):
575 test_and_clear_bit(BC_FLG_ACTIV
, &st
->l1
.bcs
->Flag
);
576 test_and_clear_bit(BC_FLG_BUSY
, &st
->l1
.bcs
->Flag
);
577 mode_2bs0(st
->l1
.bcs
, 0, st
->l1
.bc
);
578 st
->l1
.l1l2(st
, PH_DEACTIVATE
| CONFIRM
, NULL
);
584 close_2bs0(struct BCState
*bcs
)
586 mode_2bs0(bcs
, 0, bcs
->channel
);
587 if (test_and_clear_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
588 discard_queue(&bcs
->rqueue
);
589 discard_queue(&bcs
->squeue
);
591 dev_kfree_skb(bcs
->tx_skb
);
593 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
599 open_hfcstate(struct IsdnCardState
*cs
, struct BCState
*bcs
)
601 if (!test_and_set_bit(BC_FLG_INIT
, &bcs
->Flag
)) {
602 skb_queue_head_init(&bcs
->rqueue
);
603 skb_queue_head_init(&bcs
->squeue
);
606 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
613 setstack_2b(struct PStack
*st
, struct BCState
*bcs
)
615 bcs
->channel
= st
->l1
.bc
;
616 if (open_hfcstate(st
->l1
.hardware
, bcs
))
619 st
->l2
.l2l1
= hfc_l2l1
;
620 setstack_manager(st
);
627 hfcd_bh(struct IsdnCardState
*cs
)
629 /* struct PStack *stptr;
634 if (test_and_clear_bit(D_CLEARBUSY
, &cs
->event
)) {
636 debugl1(cs
, "D-Channel Busy cleared");
638 while (stptr
!= NULL
) {
639 stptr
->l1
.l1l2(stptr
, PH_PAUSE
| CONFIRM
, NULL
);
644 if (test_and_clear_bit(D_L1STATECHANGE
, &cs
->event
)) {
645 switch (cs
->ph_state
) {
647 l1_msg(cs
, HW_RESET
| INDICATION
, NULL
);
650 l1_msg(cs
, HW_DEACTIVATE
| INDICATION
, NULL
);
653 l1_msg(cs
, HW_RSYNC
| INDICATION
, NULL
);
656 l1_msg(cs
, HW_INFO2
| INDICATION
, NULL
);
659 l1_msg(cs
, HW_INFO4_P8
| INDICATION
, NULL
);
665 if (test_and_clear_bit(D_RCVBUFREADY
, &cs
->event
))
666 DChannel_proc_rcv(cs
);
667 if (test_and_clear_bit(D_XMTBUFREADY
, &cs
->event
))
668 DChannel_proc_xmt(cs
);
672 sched_event_D(struct IsdnCardState
*cs
, int event
)
674 test_and_set_bit(event
, &cs
->event
);
675 queue_task(&cs
->tqueue
, &tq_immediate
);
676 mark_bh(IMMEDIATE_BH
);
680 int receive_dmsg(struct IsdnCardState
*cs
)
686 u_char stat
, cip
, f1
, f2
;
693 if (test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
694 debugl1(cs
, "rec_dmsg blocked");
695 restore_flags(flags
);
698 SelFiFo(cs
, 4 | HFCD_REC
);
699 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_REC
;
701 f1
= cs
->readisac(cs
, cip
) & 0xf;
702 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
704 f2
= cs
->readisac(cs
, cip
) & 0xf;
705 while ((f1
!= f2
) && count
--) {
706 z1
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_REC
);
707 z2
= ReadZReg(cs
, HFCD_FIFO
| HFCD_Z2
| HFCD_REC
);
710 rcnt
+= cs
->hw
.hfcD
.dfifosize
;
712 if (cs
->debug
& L1_DEB_ISAC
)
713 debugl1(cs
, "hfcd recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
714 f1
, f2
, z1
, z2
, rcnt
);
717 cip
= HFCD_FIFO
| HFCD_FIFO_OUT
| HFCD_REC
;
718 if (rcnt
> MAX_DFRAME_LEN
+ 3) {
719 if (cs
->debug
& L1_DEB_WARN
)
720 debugl1(cs
, "empty_fifo d: incoming packet too large");
723 if (!(WaitNoBusy(cs
)))
725 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
729 } else if (rcnt
< 4) {
730 if (cs
->debug
& L1_DEB_WARN
)
731 debugl1(cs
, "empty_fifo d: incoming packet too small");
733 while ((idx
++ < rcnt
) && WaitNoBusy(cs
))
734 ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
735 } else if ((skb
= dev_alloc_skb(rcnt
- 3))) {
736 ptr
= skb_put(skb
, rcnt
- 3);
737 while (idx
< (rcnt
- 3)) {
739 if (!(WaitNoBusy(cs
)))
741 *ptr
= ReadReg(cs
, HFCD_DATA_NODEB
, cip
);
746 if (idx
!= (rcnt
- 3)) {
748 debugl1(cs
, "RFIFO D BUSY error");
749 printk(KERN_WARNING
"HFC DFIFO channel BUSY Error\n");
755 chksum
= (ReadReg(cs
, HFCD_DATA
, cip
) << 8);
757 chksum
+= ReadReg(cs
, HFCD_DATA
, cip
);
759 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
761 if (cs
->debug
& L1_DEB_ISAC
)
762 debugl1(cs
, "empty_dfifo chksum %x stat %x",
765 debugl1(cs
, "FIFO CRC error");
769 skb_queue_tail(&cs
->rq
, skb
);
770 sched_event_D(cs
, D_RCVBUFREADY
);
774 printk(KERN_WARNING
"HFC: D receive out of memory\n");
777 cip
= HFCD_FIFO
| HFCD_F2_INC
| HFCD_REC
;
780 stat
= ReadReg(cs
, HFCD_DATA
, cip
);
783 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_REC
;
786 f2
= cs
->readisac(cs
, cip
) & 0xf;
788 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
789 restore_flags(flags
);
794 hfc_fill_dfifo(struct IsdnCardState
*cs
)
803 if (cs
->tx_skb
->len
<= 0)
808 SelFiFo(cs
, 4 | HFCD_SEND
);
809 cip
= HFCD_FIFO
| HFCD_F1
| HFCD_SEND
;
811 cs
->hw
.hfcD
.f1
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
813 cip
= HFCD_FIFO
| HFCD_F2
| HFCD_SEND
;
814 cs
->hw
.hfcD
.f2
= ReadReg(cs
, HFCD_DATA
, cip
) & 0xf;
815 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
] = ReadZReg(cs
, HFCD_FIFO
| HFCD_Z1
| HFCD_SEND
);
817 if (cs
->debug
& L1_DEB_ISAC
)
818 debugl1(cs
, "hfc_fill_Dfifo f1(%d) f2(%d) z1(%x)",
819 cs
->hw
.hfcD
.f1
, cs
->hw
.hfcD
.f2
,
820 cs
->hw
.hfcD
.send
[cs
->hw
.hfcD
.f1
]);
821 fcnt
= cs
->hw
.hfcD
.f1
- cs
->hw
.hfcD
.f2
;
825 if (cs
->debug
& L1_DEB_HSCX
)
826 debugl1(cs
, "hfc_fill_Dfifo more as 14 frames");
827 restore_flags(flags
);
830 count
= GetFreeFifoBytes_D(cs
);
831 if (cs
->debug
& L1_DEB_ISAC
)
832 debugl1(cs
, "hfc_fill_Dfifo count(%ld/%d)",
833 cs
->tx_skb
->len
, count
);
834 if (count
< cs
->tx_skb
->len
) {
835 if (cs
->debug
& L1_DEB_ISAC
)
836 debugl1(cs
, "hfc_fill_Dfifo no fifo mem");
837 restore_flags(flags
);
840 cip
= HFCD_FIFO
| HFCD_FIFO_IN
| HFCD_SEND
;
845 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
++]);
846 while (idx
< cs
->tx_skb
->len
) {
848 if (!(WaitNoBusy(cs
)))
850 WriteReg(cs
, HFCD_DATA_NODEB
, cip
, cs
->tx_skb
->data
[idx
]);
854 if (idx
!= cs
->tx_skb
->len
) {
856 debugl1(cs
, "DFIFO Send BUSY error");
857 printk(KERN_WARNING
"HFC S DFIFO channel BUSY Error\n");
862 ReadReg(cs
, HFCD_DATA
, HFCD_FIFO
| HFCD_F1_INC
| HFCD_SEND
);
863 dev_kfree_skb(cs
->tx_skb
);
867 restore_flags(flags
);
872 struct BCState
*Sel_BCS(struct IsdnCardState
*cs
, int channel
)
874 if (cs
->bcs
[0].mode
&& (cs
->bcs
[0].channel
== channel
))
876 else if (cs
->bcs
[1].mode
&& (cs
->bcs
[1].channel
== channel
))
883 hfc2bds0_interrupt(struct IsdnCardState
*cs
, u_char val
)
890 if (cs
->debug
& L1_DEB_ISAC
)
891 debugl1(cs
, "HFCD irq %x %s", val
,
892 test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
) ?
893 "locked" : "unlocked");
894 val
&= cs
->hw
.hfcD
.int_m1
;
895 if (val
& 0x40) { /* TE state machine irq */
896 exval
= cs
->readisac(cs
, HFCD_STATES
) & 0xf;
897 if (cs
->debug
& L1_DEB_ISAC
)
898 debugl1(cs
, "ph_state chg %d->%d", cs
->ph_state
,
900 cs
->ph_state
= exval
;
901 sched_event_D(cs
, D_L1STATECHANGE
);
907 if (test_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
908 cs
->hw
.hfcD
.int_s1
|= val
;
909 restore_flags(flags
);
912 if (cs
->hw
.hfcD
.int_s1
& 0x18) {
914 val
= cs
->hw
.hfcD
.int_s1
;
915 cs
->hw
.hfcD
.int_s1
= exval
;
918 if (!(bcs
=Sel_BCS(cs
, 0))) {
920 debugl1(cs
, "hfcd spurious 0x08 IRQ");
925 if (!(bcs
=Sel_BCS(cs
, 1))) {
927 debugl1(cs
, "hfcd spurious 0x10 IRQ");
932 if (!(bcs
=Sel_BCS(cs
, 0))) {
934 debugl1(cs
, "hfcd spurious 0x01 IRQ");
937 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
939 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
941 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
943 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
944 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
946 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
948 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
950 hfc_sched_event(bcs
, B_XMTBUFREADY
);
956 if (!(bcs
=Sel_BCS(cs
, 1))) {
958 debugl1(cs
, "hfcd spurious 0x02 IRQ");
961 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
963 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
965 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
967 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
968 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
970 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
972 debugl1(cs
,"fill_data %d blocked", bcs
->channel
);
974 hfc_sched_event(bcs
, B_XMTBUFREADY
);
979 if (val
& 0x20) { /* receive dframe */
982 if (val
& 0x04) { /* dframe transmitted */
983 if (test_and_clear_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
))
984 del_timer(&cs
->dbusytimer
);
985 if (test_and_clear_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
))
986 sched_event_D(cs
, D_CLEARBUSY
);
988 if (cs
->tx_skb
->len
) {
989 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
991 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
993 debugl1(cs
, "hfc_fill_dfifo irq blocked");
997 dev_kfree_skb(cs
->tx_skb
);
1001 if ((cs
->tx_skb
= skb_dequeue(&cs
->sq
))) {
1003 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
1005 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
1007 debugl1(cs
, "hfc_fill_dfifo irq blocked");
1010 sched_event_D(cs
, D_XMTBUFREADY
);
1013 if (cs
->hw
.hfcD
.int_s1
&& count
--) {
1014 val
= cs
->hw
.hfcD
.int_s1
;
1015 cs
->hw
.hfcD
.int_s1
= 0;
1016 if (cs
->debug
& L1_DEB_ISAC
)
1017 debugl1(cs
, "HFCD irq %x loop %d", val
, 15-count
);
1020 restore_flags(flags
);
1025 HFCD_l1hw(struct PStack
*st
, int pr
, void *arg
)
1027 struct IsdnCardState
*cs
= (struct IsdnCardState
*) st
->l1
.hardware
;
1028 struct sk_buff
*skb
= arg
;
1031 case (PH_DATA
| REQUEST
):
1032 if (cs
->debug
& DEB_DLOG_HEX
)
1033 LogFrame(cs
, skb
->data
, skb
->len
);
1034 if (cs
->debug
& DEB_DLOG_VERBOSE
)
1035 dlogframe(cs
, skb
, 0);
1037 skb_queue_tail(&cs
->sq
, skb
);
1038 #ifdef L2FRAME_DEBUG /* psa */
1039 if (cs
->debug
& L1_DEB_LAPD
)
1040 Logl2Frame(cs
, skb
, "PH_DATA Queued", 0);
1045 #ifdef L2FRAME_DEBUG /* psa */
1046 if (cs
->debug
& L1_DEB_LAPD
)
1047 Logl2Frame(cs
, skb
, "PH_DATA", 0);
1049 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
1051 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
1053 debugl1(cs
, "hfc_fill_dfifo blocked");
1057 case (PH_PULL
| INDICATION
):
1059 if (cs
->debug
& L1_DEB_WARN
)
1060 debugl1(cs
, " l2l1 tx_skb exist this shouldn't happen");
1061 skb_queue_tail(&cs
->sq
, skb
);
1064 if (cs
->debug
& DEB_DLOG_HEX
)
1065 LogFrame(cs
, skb
->data
, skb
->len
);
1066 if (cs
->debug
& DEB_DLOG_VERBOSE
)
1067 dlogframe(cs
, skb
, 0);
1070 #ifdef L2FRAME_DEBUG /* psa */
1071 if (cs
->debug
& L1_DEB_LAPD
)
1072 Logl2Frame(cs
, skb
, "PH_DATA_PULLED", 0);
1074 if (!test_and_set_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
)) {
1076 test_and_clear_bit(FLG_LOCK_ATOMIC
, &cs
->HW_Flags
);
1078 debugl1(cs
, "hfc_fill_dfifo blocked");
1080 case (PH_PULL
| REQUEST
):
1081 #ifdef L2FRAME_DEBUG /* psa */
1082 if (cs
->debug
& L1_DEB_LAPD
)
1083 debugl1(cs
, "-> PH_REQUEST_PULL");
1086 test_and_clear_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
1087 st
->l1
.l1l2(st
, PH_PULL
| CONFIRM
, NULL
);
1089 test_and_set_bit(FLG_L1_PULL_REQ
, &st
->l1
.Flags
);
1091 case (HW_RESET
| REQUEST
):
1092 cs
->writeisac(cs
, HFCD_STATES
, HFCD_LOAD_STATE
| 3); /* HFC ST 3 */
1094 cs
->writeisac(cs
, HFCD_STATES
, 3); /* HFC ST 2 */
1095 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
1096 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
1097 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
1098 l1_msg(cs
, HW_POWERUP
| CONFIRM
, NULL
);
1100 case (HW_ENABLE
| REQUEST
):
1101 cs
->writeisac(cs
, HFCD_STATES
, HFCD_ACTIVATE
| HFCD_DO_ACTION
);
1103 case (HW_DEACTIVATE
| REQUEST
):
1104 cs
->hw
.hfcD
.mst_m
&= ~HFCD_MASTER
;
1105 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
1107 case (HW_INFO3
| REQUEST
):
1108 cs
->hw
.hfcD
.mst_m
|= HFCD_MASTER
;
1109 cs
->writeisac(cs
, HFCD_MST_MODE
, cs
->hw
.hfcD
.mst_m
);
1112 case (HW_TESTLOOP
| REQUEST
):
1118 if (test_bit(HW_IOM1
, &cs
->HW_Flags
)) {
1121 cs
->writeisac(cs
, ISAC_SPCR
, 0xa);
1122 cs
->writeisac(cs
, ISAC_ADF1
, 0x2);
1124 cs
->writeisac(cs
, ISAC_SPCR
, val
);
1125 cs
->writeisac(cs
, ISAC_ADF1
, 0xa);
1129 cs
->writeisac(cs
, ISAC_SPCR
, val
);
1131 cs
->writeisac(cs
, ISAC_ADF1
, 0x8);
1133 cs
->writeisac(cs
, ISAC_ADF1
, 0x0);
1138 if (cs
->debug
& L1_DEB_WARN
)
1139 debugl1(cs
, "hfcd_l1hw unknown pr %4x", pr
);
1145 setstack_hfcd(struct PStack
*st
, struct IsdnCardState
*cs
)
1147 st
->l1
.l1hw
= HFCD_l1hw
;
1151 hfc_dbusy_timer(struct IsdnCardState
*cs
)
1154 struct PStack
*stptr
;
1155 if (test_bit(FLG_DBUSY_TIMER
, &cs
->HW_Flags
)) {
1157 debugl1(cs
, "D-Channel Busy");
1158 test_and_set_bit(FLG_L1_DBUSY
, &cs
->HW_Flags
);
1161 while (stptr
!= NULL
) {
1162 stptr
->l1
.l1l2(stptr
, PH_PAUSE
| INDICATION
, NULL
);
1163 stptr
= stptr
->next
;
1169 __initfunc(unsigned int
1170 *init_send_hfcd(int cnt
))
1174 if (!(send
= kmalloc(cnt
* sizeof(unsigned int), GFP_ATOMIC
))) {
1176 "HiSax: No memory for hfcd.send\n");
1179 for (i
= 0; i
< cnt
; i
++)
1185 init2bds0(struct IsdnCardState
*cs
))
1187 cs
->setstack_d
= setstack_hfcd
;
1188 cs
->dbusytimer
.function
= (void *) hfc_dbusy_timer
;
1189 cs
->dbusytimer
.data
= (long) cs
;
1190 init_timer(&cs
->dbusytimer
);
1191 cs
->tqueue
.routine
= (void *) (void *) hfcd_bh
;
1192 if (!cs
->hw
.hfcD
.send
)
1193 cs
->hw
.hfcD
.send
= init_send_hfcd(16);
1194 if (!cs
->bcs
[0].hw
.hfc
.send
)
1195 cs
->bcs
[0].hw
.hfc
.send
= init_send_hfcd(32);
1196 if (!cs
->bcs
[1].hw
.hfc
.send
)
1197 cs
->bcs
[1].hw
.hfc
.send
= init_send_hfcd(32);
1198 cs
->BC_Send_Data
= &hfc_send_data
;
1199 cs
->bcs
[0].BC_SetStack
= setstack_2b
;
1200 cs
->bcs
[1].BC_SetStack
= setstack_2b
;
1201 cs
->bcs
[0].BC_Close
= close_2bs0
;
1202 cs
->bcs
[1].BC_Close
= close_2bs0
;
1203 mode_2bs0(cs
->bcs
, 0, 0);
1204 mode_2bs0(cs
->bcs
+ 1, 0, 1);
1208 release2bds0(struct IsdnCardState
*cs
)
1210 if (cs
->bcs
[0].hw
.hfc
.send
) {
1211 kfree(cs
->bcs
[0].hw
.hfc
.send
);
1212 cs
->bcs
[0].hw
.hfc
.send
= NULL
;
1214 if (cs
->bcs
[1].hw
.hfc
.send
) {
1215 kfree(cs
->bcs
[1].hw
.hfc
.send
);
1216 cs
->bcs
[1].hw
.hfc
.send
= NULL
;
1218 if (cs
->hw
.hfcD
.send
) {
1219 kfree(cs
->hw
.hfcD
.send
);
1220 cs
->hw
.hfcD
.send
= NULL
;