drivers/isdn/act2000/act2000_isa.h

   1 /* $Id: act2000_isa.h,v 1.2 1998/11/05 22:12:43 fritz Exp $
   2  *
   3  * ISDN lowlevel-module for the IBM ISDN-S0 Active 2000 (ISA-Version).
   4  *
   5  * Copyright 1998 by Fritz Elfert (fritz@isdn4linux.de)
   6  * Thanks to Friedemann Baitinger and IBM Germany
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * $Log: act2000_isa.h,v $
  23  * Revision 1.2  1998/11/05 22:12:43  fritz
  24  * Changed mail-address.
  25  *
  26  * Revision 1.1  1997/09/23 18:00:07  fritz
  27  * New driver for IBM Active 2000.
  28  *
  29  */
  30
  31 #ifndef act2000_isa_h
  32 #define act2000_isa_h
  33
  34 #define ISA_POLL_LOOP 40        /* Try to read-write before give up */
  35
  36 typedef enum {
  37         INT_NO_CHANGE = 0,      /* Do not change the Mask */
  38         INT_ON = 1,             /* Set to Enable */
  39         INT_OFF = 2,            /* Set to Disable */
  40 } ISA_INT_T;
  41
  42 /**************************************************************************/
  43 /*      Configuration Register COR (RW)                                   */
  44 /**************************************************************************/
  45 /*    7    |   6    |    5   |   4    |    3   |    2   |    1   |    0   */
  46 /* Soft Res|  IRQM  |        IRQ Select        |   N/A  |  WAIT  |Proc err */
  47 /**************************************************************************/
  48 #define        ISA_COR             0    /* Offset for ISA config register */
  49 #define        ISA_COR_PERR     0x01    /* Processor Error Enabled        */
  50 #define        ISA_COR_WS       0x02    /* Insert Wait State if 1         */
  51 #define        ISA_COR_IRQOFF   0x38    /* No Interrupt                   */
  52 #define        ISA_COR_IRQ07    0x30    /* IRQ 7 Enable                   */
  53 #define        ISA_COR_IRQ05    0x28    /* IRQ 5 Enable                   */
  54 #define        ISA_COR_IRQ03    0x20    /* IRQ 3 Enable                   */
  55 #define        ISA_COR_IRQ10    0x18    /* IRQ 10 Enable                  */
  56 #define        ISA_COR_IRQ11    0x10    /* IRQ 11 Enable                  */
  57 #define        ISA_COR_IRQ12    0x08    /* IRQ 12 Enable                  */
  58 #define        ISA_COR_IRQ15    0x00    /* IRQ 15 Enable                  */
  59 #define        ISA_COR_IRQPULSE 0x40    /* 0 = Level 1 = Pulse Interrupt  */
  60 #define        ISA_COR_RESET    0x80    /* Soft Reset for Transputer      */
  61
  62 /**************************************************************************/
  63 /*      Interrupt Source Register ISR (RO)                                */
  64 /**************************************************************************/
  65 /*    7    |   6    |    5   |   4    |    3   |    2   |    1   |    0   */
  66 /*   N/A   |  N/A   |   N/A  |Err sig |Ser ID  |IN Intr |Out Intr| Error  */
  67 /**************************************************************************/
  68 #define        ISA_ISR             1    /* Offset for Interrupt Register  */
  69 #define        ISA_ISR_ERR      0x01    /* Error Interrupt                */
  70 #define        ISA_ISR_OUT      0x02    /* Output Interrupt               */
  71 #define        ISA_ISR_INP      0x04    /* Input Interrupt                */
  72 #define        ISA_ISR_SERIAL   0x08    /* Read out Serial ID after Reset */
  73 #define        ISA_ISR_ERRSIG   0x10    /* Error Signal Input             */
  74 #define        ISA_ISR_ERR_MASK 0xfe    /* Mask Error Interrupt           */
  75 #define        ISA_ISR_OUT_MASK 0xfd    /* Mask Output Interrupt          */
  76 #define        ISA_ISR_INP_MASK 0xfb    /* Mask Input Interrupt           */
  77
  78 /* Signature delivered after Reset at ISA_ISR_SERIAL (LSB first)          */
  79 #define        ISA_SER_ID     0x0201    /* ID for ISA Card                */
  80
  81 /**************************************************************************/
  82 /*      EEPROM Register EPR (RW)                                          */
  83 /**************************************************************************/
  84 /*    7    |   6    |    5   |   4    |    3   |    2   |    1   |    0   */
  85 /*   N/A   |  N/A   |   N/A  |ROM Hold| ROM CS |ROM CLK | ROM IN |ROM Out */
  86 /**************************************************************************/
  87 #define        ISA_EPR             2    /* Offset for this Register       */
  88 #define        ISA_EPR_OUT      0x01    /* Rome Register Out (RO)         */
  89 #define        ISA_EPR_IN       0x02    /* Rom Register In (WR)           */
  90 #define        ISA_EPR_CLK      0x04    /* Rom Clock (WR)                 */
  91 #define        ISA_EPR_CS       0x08    /* Rom Cip Select (WR)            */
  92 #define        ISA_EPR_HOLD     0x10    /* Rom Hold Signal (WR)           */
  93
  94 /**************************************************************************/
  95 /*      EEPROM enable Register EER (unused)                               */
  96 /**************************************************************************/
  97 #define        ISA_EER             3    /* Offset for this Register       */
  98
  99 /**************************************************************************/
 100 /*      SLC Data Input SDI (RO)                                           */
 101 /**************************************************************************/
 102 #define        ISA_SDI             4    /* Offset for this Register       */
 103
 104 /**************************************************************************/
 105 /*      SLC Data Output SDO (WO)                                          */
 106 /**************************************************************************/
 107 #define        ISA_SDO             5    /* Offset for this Register       */
 108
 109 /**************************************************************************/
 110 /*      IMS C011 Mode 2 Input Status Register for INMOS CPU SIS (RW)      */
 111 /**************************************************************************/
 112 /*    7    |   6    |    5   |   4    |    3   |    2   |    1   |    0   */
 113 /*   N/A   |  N/A   |   N/A  |  N/A   |   N/A  |   N/A  |Int Ena |Data Pre */
 114 /**************************************************************************/
 115 #define        ISA_SIS             6    /* Offset for this Register       */
 116 #define        ISA_SIS_READY    0x01    /* If 1 : data is available       */
 117 #define        ISA_SIS_INT      0x02    /* Enable Interrupt for READ      */
 118
 119 /**************************************************************************/
 120 /*      IMS C011 Mode 2 Output Status Register from INMOS CPU SOS (RW)    */
 121 /**************************************************************************/
 122 /*    7    |   6    |    5   |   4    |    3   |    2   |    1   |    0   */
 123 /*   N/A   |  N/A   |   N/A  |  N/A   |   N/A  |   N/A  |Int Ena |Out Rdy */
 124 /**************************************************************************/
 125 #define        ISA_SOS             7    /* Offset for this Register       */
 126 #define        ISA_SOS_READY    0x01    /* If 1 : we can write Data       */
 127 #define        ISA_SOS_INT      0x02    /* Enable Interrupt for WRITE     */
 128
 129 #define        ISA_REGION          8    /* Number of Registers            */
 130
 131
 132 /* Macros for accessing ports */
 133 #define ISA_PORT_COR (card->port+ISA_COR)
 134 #define ISA_PORT_ISR (card->port+ISA_ISR)
 135 #define ISA_PORT_EPR (card->port+ISA_EPR)
 136 #define ISA_PORT_EER (card->port+ISA_EER)
 137 #define ISA_PORT_SDI (card->port+ISA_SDI)
 138 #define ISA_PORT_SDO (card->port+ISA_SDO)
 139 #define ISA_PORT_SIS (card->port+ISA_SIS)
 140 #define ISA_PORT_SOS (card->port+ISA_SOS)
 141
 142 /* Prototypes */
 143
 144 extern int isa_detect(unsigned short portbase);
 145 extern int isa_config_irq(act2000_card * card, short irq);
 146 extern int isa_config_port(act2000_card * card, unsigned short portbase);
 147 extern int isa_download(act2000_card * card, act2000_ddef * cb);
 148 extern void isa_release(act2000_card * card);
 149 extern void isa_receive(act2000_card *card);
 150 extern void isa_send(act2000_card *card);
 151
 152 #endif                          /* act2000_isa_h */