drivers/sbus/audio/dbri.h

   1 /*
   2  * drivers/sbus/audio/cs4231.h
   3  *
   4  * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
   5  */
   6
   7 #ifndef _DBRI_H_
   8 #define _DBRI_H_
   9
  10 #include <linux/types.h>
  11
  12 struct dbri_regs {
  13   __volatile__ __u32 reg0;              /* Status & Control */
  14   __volatile__ __u32 reg1;              /* Mode & Interrupt */
  15   __volatile__ __u32 reg2;              /* Parallel IO */
  16   __volatile__ __u32 reg3;              /* Test */
  17   __volatile__ __u32 unused[4];
  18   __volatile__ __u32 reg8;              /* Command Queue Pointer */
  19   __volatile__ __u32 reg9;              /* Interrupt Queue Pointer */
  20 };
  21
  22 #define DBRI_NO_CMDS    64
  23 #define DBRI_NO_INTS    2
  24 #define DBRI_INT_BLK    64
  25 #define DBRI_NO_DESCS   64
  26
  27 #define DBRI_MM_ONB     1
  28 #define DBRI_MM_SB      2
  29
  30 struct dbri_mem {
  31         __u32   word1;
  32         __u32   ba;                     /* Transmit/Receive Buffer Address */
  33         __u32   nda;                    /* Next Descriptor Address */
  34         __u32   word4;
  35 };
  36
  37 #include "cs4215.h"
  38
  39 /* This structure is in a DMA region where it can accessed by both
  40  * the CPU and the DBRI
  41  */
  42
  43 struct dbri_dma {
  44   int cmd[DBRI_NO_CMDS];                        /* Place for commands */
  45   int intr[DBRI_NO_INTS * DBRI_INT_BLK];        /* Interrupt field */
  46   struct dbri_mem desc[DBRI_NO_DESCS];          /* Xmit/receive descriptors */
  47 };
  48
  49 struct dbri_pipe {
  50         u32 sdp;                                /* SDP command word */
  51         int nextpipe;                           /* Next pipe in linked list */
  52         int cycle;                              /* Offset of timeslot (bits) */
  53         int length;                             /* Length of timeslot (bits) */
  54         int desc;                               /* Index of active descriptor*/
  55         __u32 *recv_fixed_ptr;                  /* Ptr to receive fixed data */
  56 };
  57
  58 struct dbri_desc {
  59         int inuse;                              /* Boolean flag */
  60         int next;                               /* Index of next desc, or -1 */
  61         void *buffer;
  62         unsigned int len;
  63         void (*output_callback)(void *, int);
  64         void *output_callback_arg;
  65         void (*input_callback)(void *, int, unsigned int);
  66         void *input_callback_arg;
  67 };
  68
  69 /* This structure holds the information for both chips (DBRI & CS4215) */
  70
  71 struct dbri {
  72   int regs_size, irq;                           /* Needed for unload */
  73   struct linux_sbus_device *sdev;
  74
  75   volatile struct dbri_dma *dma;                /* Pointer to our DMA block */
  76   struct dbri_dma *dma_dvma;                    /* DBRI visible DMA address */
  77
  78   struct dbri_regs *regs;                       /* dbri HW regs */
  79   int dbri_version;                             /* 'e' and up is OK */
  80   int dbri_irqp;                                /* intr queue pointer */
  81
  82   struct dbri_pipe pipes[32];                   /* DBRI's 32 data pipes */
  83   struct dbri_desc descs[DBRI_NO_DESCS];
  84
  85   struct cs4215 mm;                             /* mmcodec special info */
  86
  87 #if 0
  88   wait_queue_head_t wait, int_wait;             /* Where to sleep if busy */
  89 #endif
  90   struct audio_info perchip_info;
  91
  92   /* Track ISDN LIU and notify changes */
  93   int liu_state;
  94   void (*liu_callback)(void *);
  95   void *liu_callback_arg;
  96 };
  97
  98
  99 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
 100 #define D_P             (1<<15) /* Program command & queue pointer valid */
 101 #define D_G             (1<<14) /* Allow 4-Word SBus Burst */
 102 #define D_S             (1<<13) /* Allow 16-Word SBus Burst */
 103 #define D_E             (1<<12) /* Allow 8-Word SBus Burst */
 104 #define D_X             (1<<7)  /* Sanity Timer Disable */
 105 #define D_T             (1<<6)  /* Permit activation of the TE interface */
 106 #define D_N             (1<<5)  /* Permit activation of the NT interface */
 107 #define D_C             (1<<4)  /* Permit activation of the CHI interface */
 108 #define D_F             (1<<3)  /* Force Sanity Timer Time-Out */
 109 #define D_D             (1<<2)  /* Disable Master Mode */
 110 #define D_H             (1<<1)  /* Halt for Analysis */
 111 #define D_R             (1<<0)  /* Soft Reset */
 112
 113
 114 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
 115 #define D_LITTLE_END    (1<<8)  /* Byte Order */
 116 #define D_BIG_END       (0<<8)  /* Byte Order */
 117 #define D_MRR           (1<<4)  /* Multiple Error Ack on SBus (readonly) */
 118 #define D_MLE           (1<<3)  /* Multiple Late Error on SBus (readonly) */
 119 #define D_LBG           (1<<2)  /* Lost Bus Grant on SBus (readonly) */
 120 #define D_MBE           (1<<1)  /* Burst Error on SBus (readonly) */
 121 #define D_IR            (1<<0)  /* Interrupt Indicator (readonly) */
 122
 123
 124 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
 125 #define D_ENPIO3        (1<<7)  /* Enable Pin 3 */
 126 #define D_ENPIO2        (1<<6)  /* Enable Pin 2 */
 127 #define D_ENPIO1        (1<<5)  /* Enable Pin 1 */
 128 #define D_ENPIO0        (1<<4)  /* Enable Pin 0 */
 129 #define D_ENPIO         (0xf0)  /* Enable all the pins */
 130 #define D_PIO3          (1<<3)  /* Pin 3: 1: Data mode, 0: Ctrl mode */
 131 #define D_PIO2          (1<<2)  /* Pin 2: 1: Onboard PDN */
 132 #define D_PIO1          (1<<1)  /* Pin 1: 0: Reset */
 133 #define D_PIO0          (1<<0)  /* Pin 0: 1: Speakerbox PDN */
 134
 135
 136 /* DBRI Commands (Page 20) */
 137 #define D_WAIT          0x0     /* Stop execution */
 138 #define D_PAUSE         0x1     /* Flush long pipes */
 139 #define D_JUMP          0x2     /* New command queue */
 140 #define D_IIQ           0x3     /* Initialize Interrupt Queue */
 141 #define D_REX           0x4     /* Report command execution via interrupt */
 142 #define D_SDP           0x5     /* Setup Data Pipe */
 143 #define D_CDP           0x6     /* Continue Data Pipe (reread NULL Pointer) */
 144 #define D_DTS           0x7     /* Define Time Slot */
 145 #define D_SSP           0x8     /* Set short Data Pipe */
 146 #define D_CHI           0x9     /* Set CHI Global Mode */
 147 #define D_NT            0xa     /* NT Command */
 148 #define D_TE            0xb     /* TE Command */
 149 #define D_CDEC          0xc     /* Codec setup */
 150 #define D_TEST          0xd     /* No comment */
 151 #define D_CDM           0xe     /* CHI Data mode command */
 152
 153
 154
 155 /* Special bits for some commands */
 156 #define D_PIPE(v)      ((v)<<0)        /* Pipe Nr: 0-15 long, 16-21 short */
 157
 158 /* Setup Data Pipe */
 159 /* IRM */
 160 #define D_SDP_2SAME     (1<<18) /* Report 2nd time in a row value rcvd*/
 161 #define D_SDP_CHANGE    (2<<18) /* Report any changes */
 162 #define D_SDP_EVERY     (3<<18) /* Report any changes */
 163 #define D_SDP_EOL       (1<<17) /* EOL interrupt enable */
 164 #define D_SDP_IDLE      (1<<16) /* HDLC idle interrupt enable */
 165
 166 /* Pipe data MODE */
 167 #define D_SDP_MEM       (0<<13) /* To/from memory */
 168 #define D_SDP_HDLC      (2<<13)
 169 #define D_SDP_HDLC_D    (3<<13) /* D Channel (prio control)*/
 170 #define D_SDP_SER       (4<<13) /* Serial to serial */
 171 #define D_SDP_FIXED     (6<<13) /* Short only */
 172 #define D_SDP_MODE(v)   ((v)&(7<<13))
 173
 174 #define D_SDP_TO_SER    (1<<12) /* Direction */
 175 #define D_SDP_FROM_SER  (0<<12) /* Direction */
 176 #define D_SDP_MSB       (1<<11) /* Bit order within Byte */
 177 #define D_SDP_LSB       (0<<11) /* Bit order within Byte */
 178 #define D_SDP_P         (1<<10) /* Pointer Valid */
 179 #define D_SDP_A         (1<<8)  /* Abort */
 180 #define D_SDP_C         (1<<7)  /* Clear */
 181
 182 /* Define Time Slot */
 183 #define D_DTS_VI        (1<<17) /* Valid Input Time-Slot Descriptor */
 184 #define D_DTS_VO        (1<<16) /* Valid Output Time-Slot Descriptor */
 185 #define D_DTS_INS       (1<<15) /* Insert Time Slot */
 186 #define D_DTS_DEL       (0<<15) /* Delete Time Slot */
 187 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
 188 #define D_DTS_PRVOUT(v)        ((v)<<5)  /* Previous Out Pipe */
 189
 190 /* Time Slot defines */
 191 #define D_TS_LEN(v)     ((v)<<24)       /* Number of bits in this time slot */
 192 #define D_TS_CYCLE(v)   ((v)<<14)       /* Bit Count at start of TS */
 193 #define D_TS_DI(v)      (1<<13) /* Data Invert */
 194 #define D_TS_1CHANNEL   (0<<10) /* Single Channel / Normal mode */
 195 #define D_TS_MONITOR    (2<<10) /* Monitor pipe */
 196 #define D_TS_NONCONTIG  (3<<10) /* Non contiguous mode */
 197 #define D_TS_ANCHOR     (7<<10) /* Starting short pipes */
 198 #define D_TS_MON(v)    ((v)<<5)        /* Monitor Pipe */
 199 #define D_TS_NEXT(v)   ((v)<<0)        /* Pipe Nr: 0-15 long, 16-21 short */
 200
 201 /* Concentration Highway Interface Modes */
 202 #define D_CHI_CHICM(v)  ((v)<<16)       /* Clock mode */
 203 #define D_CHI_IR        (1<<15) /* Immediate Interrupt Report */
 204 #define D_CHI_EN        (1<<14) /* CHIL Interrupt enabled */
 205 #define D_CHI_OD        (1<<13) /* Open Drain Enable */
 206 #define D_CHI_FE        (1<<12) /* Sample CHIFS on Rising Frame Edge */
 207 #define D_CHI_FD        (1<<11) /* Frame Drive */
 208 #define D_CHI_BPF(v)    ((v)<<0)        /* Bits per Frame */
 209
 210 /* NT: These are here for completeness */
 211 #define D_NT_FBIT       (1<<17) /* Frame Bit */
 212 #define D_NT_NBF        (1<<16) /* Number of bad frames to loose framing */
 213 #define D_NT_IRM_IMM    (1<<15) /* Interrupt Report & Mask: Immediate */
 214 #define D_NT_IRM_EN     (1<<14) /* Interrupt Report & Mask: Enable */
 215 #define D_NT_ISNT       (1<<13) /* Configfure interface as NT */
 216 #define D_NT_FT         (1<<12) /* Fixed Timing */
 217 #define D_NT_EZ         (1<<11) /* Echo Channel is Zeros */
 218 #define D_NT_IFA        (1<<10) /* Inhibit Final Activation */
 219 #define D_NT_ACT        (1<<9)  /* Activate Interface */
 220 #define D_NT_MFE        (1<<8)  /* Multiframe Enable */
 221 #define D_NT_RLB(v)     (1<<5)  /* Remote Loopback */
 222 #define D_NT_LLB(v)     (1<<2)  /* Local Loopback */
 223 #define D_NT_FACT       (1<<1)  /* Force Activation */
 224 #define D_NT_ABV        (1<<0)  /* Activate Bipolar Violation */
 225
 226 /* Codec Setup */
 227 #define D_CDEC_CK(v)    ((v)<<24)       /* Clock Select */
 228 #define D_CDEC_FED(v)   ((v)<<12)       /* FSCOD Falling Edge Delay */
 229 #define D_CDEC_RED(v)   ((v)<<0)        /* FSCOD Rising Edge Delay */
 230
 231 /* Test */
 232 #define D_TEST_RAM(v)   ((v)<<16)       /* RAM Pointer */
 233 #define D_TEST_SIZE(v)  ((v)<<11)       /* */
 234 #define D_TEST_ROMONOFF 0x5     /* Toggle ROM opcode monitor on/off */
 235 #define D_TEST_PROC     0x6     /* MicroProcessor test */
 236 #define D_TEST_SER      0x7     /* Serial-Controller test */
 237 #define D_TEST_RAMREAD  0x8     /* Copy from Ram to system memory */
 238 #define D_TEST_RAMWRITE 0x9     /* Copy into Ram from system memory */
 239 #define D_TEST_RAMBIST  0xa     /* RAM Built-In Self Test */
 240 #define D_TEST_MCBIST   0xb     /* Microcontroller Built-In Self Test */
 241 #define D_TEST_DUMP     0xe     /* ROM Dump */
 242
 243 /* CHI Data Mode */
 244 #define D_CDM_THI       (1<<8)  /* Transmit Data on CHIDR Pin */
 245 #define D_CDM_RHI       (1<<7)  /* Receive Data on CHIDX Pin */
 246 #define D_CDM_RCE       (1<<6)  /* Receive on Rising Edge of CHICK */
 247 #define D_CDM_XCE       (1<<2)  /* Transmit Data on Rising Edge of CHICK */
 248 #define D_CDM_XEN       (1<<1)  /* Transmit Highway Enable */
 249 #define D_CDM_REN       (1<<0)  /* Receive Highway Enable */
 250
 251 /* The Interrupts */
 252 #define D_INTR_BRDY     1       /* Buffer Ready for processing */
 253 #define D_INTR_MINT     2       /* Marked Interrupt in RD/TD */
 254 #define D_INTR_IBEG     3       /* Flag to idle transition detected (HDLC) */
 255 #define D_INTR_IEND     4       /* Idle to flag transition detected (HDLC) */
 256 #define D_INTR_EOL      5       /* End of List */
 257 #define D_INTR_CMDI     6       /* Command has bean read */
 258 #define D_INTR_XCMP     8       /* Transmission of frame complete */
 259 #define D_INTR_SBRI     9       /* BRI status change info */
 260 #define D_INTR_FXDT     10      /* Fixed data change */
 261 #define D_INTR_CHIL     11      /* CHI lost frame sync (channel 36 only) */
 262 #define D_INTR_COLL     11      /* Unrecoverable D-Channel collision */
 263 #define D_INTR_DBYT     12      /* Dropped by frame slip */
 264 #define D_INTR_RBYT     13      /* Repeated by frame slip */
 265 #define D_INTR_LINT     14      /* Lost Interrupt */
 266 #define D_INTR_UNDR     15      /* DMA underrun */
 267
 268 #define D_INTR_TE       32
 269 #define D_INTR_NT       34
 270 #define D_INTR_CHI      36
 271 #define D_INTR_CMD      38
 272
 273 #define D_INTR_GETCHAN(v)       (((v)>>24) & 0x3f)
 274 #define D_INTR_GETCODE(v)       (((v)>>20) & 0xf)
 275 #define D_INTR_GETCMD(v)        (((v)>>16) & 0xf)
 276 #define D_INTR_GETVAL(v)        ((v) & 0xffff)
 277 #define D_INTR_GETRVAL(v)       ((v) & 0xfffff)
 278
 279 #define D_P_0           0       /* TE receive anchor */
 280 #define D_P_1           1       /* TE transmit anchor */
 281 #define D_P_2           2       /* NT transmit anchor */
 282 #define D_P_3           3       /* NT receive anchor */
 283 #define D_P_4           4       /* CHI send data */
 284 #define D_P_5           5       /* CHI receive data */
 285 #define D_P_6           6       /* */
 286 #define D_P_7           7       /* */
 287 #define D_P_8           8       /* */
 288 #define D_P_9           9       /* */
 289 #define D_P_10          10      /* */
 290 #define D_P_11          11      /* */
 291 #define D_P_12          12      /* */
 292 #define D_P_13          13      /* */
 293 #define D_P_14          14      /* */
 294 #define D_P_15          15      /* */
 295 #define D_P_16          16      /* CHI anchor pipe */
 296 #define D_P_17          17      /* CHI send */
 297 #define D_P_18          18      /* CHI receive */
 298 #define D_P_19          19      /* CHI receive */
 299 #define D_P_20          20      /* CHI receive */
 300 #define D_P_21          21      /* */
 301 #define D_P_22          22      /* */
 302 #define D_P_23          23      /* */
 303 #define D_P_24          24      /* */
 304 #define D_P_25          25      /* */
 305 #define D_P_26          26      /* */
 306 #define D_P_27          27      /* */
 307 #define D_P_28          28      /* */
 308 #define D_P_29          29      /* */
 309 #define D_P_30          30      /* */
 310 #define D_P_31          31      /* */
 311
 312
 313 /* Transmit descriptor defines */
 314 #define DBRI_TD_F       (1<<31) /* End of Frame */
 315 #define DBRI_TD_D       (1<<30) /* Do not append CRC */
 316 #define DBRI_TD_CNT(v)  ((v)<<16)       /* Number of valid bytes in the buffer */
 317 #define DBRI_TD_B       (1<<15) /* Final interrupt */
 318 #define DBRI_TD_M       (1<<14) /* Marker interrupt */
 319 #define DBRI_TD_I       (1<<13) /* Transmit Idle Characters */
 320 #define DBRI_TD_FCNT(v) (v)     /* Flag Count */
 321 #define DBRI_TD_UNR     (1<<3)  /* Underrun: transmitter is out of data */
 322 #define DBRI_TD_ABT     (1<<2)  /* Abort: frame aborted */
 323 #define DBRI_TD_TBC     (1<<0)  /* Transmit buffer Complete */
 324 #define DBRI_TD_STATUS(v)       ((v)&0xff)      /* Transmit status */
 325
 326 /* Receive descriptor defines */
 327 #define DBRI_RD_F       (1<<31) /* End of Frame */
 328 #define DBRI_RD_C       (1<<30) /* Completed buffer */
 329 #define DBRI_RD_B       (1<<15) /* Final interrupt */
 330 #define DBRI_RD_M       (1<<14) /* Marker interrupt */
 331 #define DBRI_RD_BCNT(v) (v)     /* Buffer size */
 332 #define DBRI_RD_CRC     (1<<7)  /* 0: CRC is correct */
 333 #define DBRI_RD_BBC     (1<<6)  /* 1: Bad Byte received */
 334 #define DBRI_RD_ABT     (1<<5)  /* Abort: frame aborted */
 335 #define DBRI_RD_OVRN    (1<<3)  /* Overrun: data lost */
 336 #define DBRI_RD_STATUS(v)      ((v)&0xff)      /* Receive status */
 337 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff)        /* Number of valid bytes in the buffer */
 338
 339 #endif /* _DBRI_H_ */