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Import 2.3.41pre2
[davej-history.git] / drivers / sound / ad1848.c
blob498db82f068149e7c9157871c358a0c45593ef4f
1 /*
2 * sound/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 *
30 * Status:
31 * Tested. Believed fully functional.
32 */
33
34 #include <linux/config.h>
35 #include <linux/module.h>
36 #include <linux/stddef.h>
37
38 #include "soundmodule.h"
39
40 #define DEB(x)
41 #define DEB1(x)
42 #include "sound_config.h"
43
44 #ifdef CONFIG_AD1848
45
46 #include "ad1848_mixer.h"
47
48 typedef struct
49 {
50 int base;
51 int irq;
52 int dma1, dma2;
53 int dual_dma; /* 1, when two DMA channels allocated */
54 unsigned char MCE_bit;
55 unsigned char saved_regs[32];
56 int debug_flag;
57
58 int audio_flags;
59 int record_dev, playback_dev;
60
61 int xfer_count;
62 int audio_mode;
63 int open_mode;
64 int intr_active;
65 char *chip_name, *name;
66 int model;
67 #define MD_1848 1
68 #define MD_4231 2
69 #define MD_4231A 3
70 #define MD_1845 4
71 #define MD_4232 5
72 #define MD_C930 6
73 #define MD_IWAVE 7
74 #define MD_4235 8 /* Crystal Audio CS4235 */
75 #define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
76
77 /* Mixer parameters */
78 int recmask;
79 int supported_devices, orig_devices;
80 int supported_rec_devices, orig_rec_devices;
81 int *levels;
82 short mixer_reroute[32];
83 int dev_no;
84 volatile unsigned long timer_ticks;
85 int timer_running;
86 int irq_ok;
87 mixer_ents *mix_devices;
88 int mixer_output_port;
89 } ad1848_info;
90
91 typedef struct ad1848_port_info
92 {
93 int open_mode;
94 int speed;
95 unsigned char speed_bits;
96 int channels;
97 int audio_format;
98 unsigned char format_bits;
99 }
100 ad1848_port_info;
101
102 static int nr_ad1848_devs = 0;
103 int deskpro_xl = 0;
104 int deskpro_m = 0;
105 #ifdef CONFIG_SOUND_SPRO
106 int soundpro = 1;
107 #else
108 int soundpro = 0;
109 #endif
110
111 static volatile signed char irq2dev[17] = {
112 -1, -1, -1, -1, -1, -1, -1, -1,
113 -1, -1, -1, -1, -1, -1, -1, -1, -1
114 };
115
116 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS) || defined(MODULE)
117
118 static int timer_installed = -1;
119
120 #endif
121
122 static int ad_format_mask[10 /*devc->model */ ] =
123 {
124 0,
125 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
126 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
127 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
128 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
129 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
130 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
131 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
132 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
133 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/
134 };
135
136 static ad1848_info adev_info[MAX_AUDIO_DEV];
137
138 #define io_Index_Addr(d) ((d)->base)
139 #define io_Indexed_Data(d) ((d)->base+1)
140 #define io_Status(d) ((d)->base+2)
141 #define io_Polled_IO(d) ((d)->base+3)
142
143 static struct {
144 unsigned char flags;
145 #define CAP_F_TIMER 0x01
146 } capabilities [10 /*devc->model */ ] = {
147 {0}
148 ,{0} /* MD_1848 */
149 ,{CAP_F_TIMER} /* MD_4231 */
150 ,{CAP_F_TIMER} /* MD_4231A */
151 ,{CAP_F_TIMER} /* MD_1845 */
152 ,{CAP_F_TIMER} /* MD_4232 */
153 ,{0} /* MD_C930 */
154 ,{CAP_F_TIMER} /* MD_IWAVE */
155 ,{0} /* MD_4235 */
156 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
157 };
158
159 static int ad1848_open(int dev, int mode);
160 static void ad1848_close(int dev);
161 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
162 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
163 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
164 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
165 static void ad1848_halt(int dev);
166 static void ad1848_halt_input(int dev);
167 static void ad1848_halt_output(int dev);
168 static void ad1848_trigger(int dev, int bits);
169
170 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
171 static int ad1848_tmr_install(int dev);
172 static void ad1848_tmr_reprogram(int dev);
173
174 #endif
175
176 static int ad_read(ad1848_info * devc, int reg)
177 {
178 unsigned long flags;
179 int x;
180 int timeout = 900000;
181
182 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
183 timeout--;
184
185 save_flags(flags);
186 cli();
187 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
188 x = inb(io_Indexed_Data(devc));
189 /* printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
190 restore_flags(flags);
191
192 return x;
193 }
194
195 static void ad_write(ad1848_info * devc, int reg, int data)
196 {
197 unsigned long flags;
198 int timeout = 900000;
199
200 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
201 timeout--;
202
203 save_flags(flags);
204 cli();
205 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
206 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
207 /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
208 restore_flags(flags);
209 }
210
211 static void wait_for_calibration(ad1848_info * devc)
212 {
213 int timeout = 0;
214
215 /*
216 * Wait until the auto calibration process has finished.
217 *
218 * 1) Wait until the chip becomes ready (reads don't return 0x80).
219 * 2) Wait until the ACI bit of I11 gets on and then off.
220 */
221
222 timeout = 100000;
223 while (timeout > 0 && inb(devc->base) == 0x80)
224 timeout--;
225 if (inb(devc->base) & 0x80)
226 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
227
228 timeout = 100;
229 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
230 timeout--;
231 if (!(ad_read(devc, 11) & 0x20))
232 return;
233
234 timeout = 80000;
235 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
236 timeout--;
237 if (ad_read(devc, 11) & 0x20)
238 if ( (devc->model != MD_1845) || (devc->model != MD_1845_SSCAPE))
239 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
240 }
241
242 static void ad_mute(ad1848_info * devc)
243 {
244 int i;
245 unsigned char prev;
246
247 /*
248 * Save old register settings and mute output channels
249 */
250
251 for (i = 6; i < 8; i++)
252 {
253 prev = devc->saved_regs[i] = ad_read(devc, i);
254 }
255
256 }
257
258 static void ad_unmute(ad1848_info * devc)
259 {
260 }
261
262 static void ad_enter_MCE(ad1848_info * devc)
263 {
264 unsigned long flags;
265 int timeout = 1000;
266 unsigned short prev;
267
268 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
269 timeout--;
270
271 save_flags(flags);
272 cli();
273
274 devc->MCE_bit = 0x40;
275 prev = inb(io_Index_Addr(devc));
276 if (prev & 0x40)
277 {
278 restore_flags(flags);
279 return;
280 }
281 outb((devc->MCE_bit), io_Index_Addr(devc));
282 restore_flags(flags);
283 }
284
285 static void ad_leave_MCE(ad1848_info * devc)
286 {
287 unsigned long flags;
288 unsigned char prev, acal;
289 int timeout = 1000;
290
291 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
292 timeout--;
293
294 save_flags(flags);
295 cli();
296
297 acal = ad_read(devc, 9);
298
299 devc->MCE_bit = 0x00;
300 prev = inb(io_Index_Addr(devc));
301 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
302
303 if ((prev & 0x40) == 0) /* Not in MCE mode */
304 {
305 restore_flags(flags);
306 return;
307 }
308 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
309 if (acal & 0x08) /* Auto calibration is enabled */
310 wait_for_calibration(devc);
311 restore_flags(flags);
312 }
313
314 static int ad1848_set_recmask(ad1848_info * devc, int mask)
315 {
316 unsigned char recdev;
317 int i, n;
318
319 mask &= devc->supported_rec_devices;
320
321 /* Rename the mixer bits if necessary */
322 for (i = 0; i < 32; i++)
323 {
324 if (devc->mixer_reroute[i] != i)
325 {
326 if (mask & (1 << i))
327 {
328 mask &= ~(1 << i);
329 mask |= (1 << devc->mixer_reroute[i]);
330 }
331 }
332 }
333
334 n = 0;
335 for (i = 0; i < 32; i++) /* Count selected device bits */
336 if (mask & (1 << i))
337 n++;
338
339 if (!soundpro) {
340 if (n == 0)
341 mask = SOUND_MASK_MIC;
342 else if (n != 1) { /* Too many devices selected */
343 mask &= ~devc->recmask; /* Filter out active settings */
344
345 n = 0;
346 for (i = 0; i < 32; i++) /* Count selected device bits */
347 if (mask & (1 << i))
348 n++;
349
350 if (n != 1)
351 mask = SOUND_MASK_MIC;
352 }
353 switch (mask) {
354 case SOUND_MASK_MIC:
355 recdev = 2;
356 break;
357
358 case SOUND_MASK_LINE:
359 case SOUND_MASK_LINE3:
360 recdev = 0;
361 break;
362
363 case SOUND_MASK_CD:
364 case SOUND_MASK_LINE1:
365 recdev = 1;
366 break;
367
368 case SOUND_MASK_IMIX:
369 recdev = 3;
370 break;
371
372 default:
373 mask = SOUND_MASK_MIC;
374 recdev = 2;
375 }
376
377 recdev <<= 6;
378 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
379 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
380 } else { /* soundpro */
381 unsigned char val;
382 int set_rec_bit;
383 int j;
384
385 for (i = 0; i < 32; i++) { /* For each bit */
386 if ((devc->supported_rec_devices & (1 << i)) == 0)
387 continue; /* Device not supported */
388
389 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
390 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
391 continue;
392
393 /*
394 * This is tricky:
395 * set_rec_bit becomes 1 if the corresponding bit in mask is set
396 * then it gets flipped if the polarity is inverse
397 */
398 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
399
400 val = ad_read(devc, devc->mix_devices[i][j].recreg);
401 val &= ~(1 << devc->mix_devices[i][j].recpos);
402 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
403 ad_write(devc, devc->mix_devices[i][j].recreg, val);
404 }
405 }
406 }
407
408 /* Rename the mixer bits back if necessary */
409 for (i = 0; i < 32; i++)
410 {
411 if (devc->mixer_reroute[i] != i)
412 {
413 if (mask & (1 << devc->mixer_reroute[i]))
414 {
415 mask &= ~(1 << devc->mixer_reroute[i]);
416 mask |= (1 << i);
417 }
418 }
419 }
420 devc->recmask = mask;
421 return mask;
422 }
423
424 static void change_bits(ad1848_info * devc, unsigned char *regval,
425 unsigned char *muteval, int dev, int chn, int newval)
426 {
427 unsigned char mask;
428 int shift;
429 int mute;
430 int mutemask;
431 int set_mute_bit;
432
433 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
434
435 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
436 newval = 100 - newval;
437
438 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
439 shift = devc->mix_devices[dev][chn].bitpos;
440
441 if (devc->mix_devices[dev][chn].mutepos == 8)
442 { /* if there is no mute bit */
443 mute = 0; /* No mute bit; do nothing special */
444 mutemask = ~0; /* No mute bit; do nothing special */
445 }
446 else
447 {
448 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
449 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
450 }
451
452 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
453 *regval &= ~(mask << shift); /* Clear bits */
454 *regval |= (newval & mask) << shift; /* Set new value */
455
456 *muteval &= mutemask;
457 *muteval |= mute;
458 }
459
460 static int ad1848_mixer_get(ad1848_info * devc, int dev)
461 {
462 if (!((1 << dev) & devc->supported_devices))
463 return -EINVAL;
464
465 dev = devc->mixer_reroute[dev];
466
467 return devc->levels[dev];
468 }
469
470 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
471 {
472 int regoffs, muteregoffs;
473 unsigned char val, muteval;
474
475 regoffs = devc->mix_devices[dev][channel].regno;
476 muteregoffs = devc->mix_devices[dev][channel].mutereg;
477 val = ad_read(devc, regoffs);
478
479 if (muteregoffs != regoffs) {
480 muteval = ad_read(devc, muteregoffs);
481 change_bits(devc, &val, &muteval, dev, channel, value);
482 }
483 else
484 change_bits(devc, &val, &val, dev, channel, value);
485
486 ad_write(devc, regoffs, val);
487 devc->saved_regs[regoffs] = val;
488 if (muteregoffs != regoffs) {
489 ad_write(devc, muteregoffs, muteval);
490 devc->saved_regs[muteregoffs] = muteval;
491 }
492 }
493
494 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
495 {
496 int left = value & 0x000000ff;
497 int right = (value & 0x0000ff00) >> 8;
498 int retvol;
499
500 if (dev > 31)
501 return -EINVAL;
502
503 if (!(devc->supported_devices & (1 << dev)))
504 return -EINVAL;
505
506 dev = devc->mixer_reroute[dev];
507
508 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
509 return -EINVAL;
510
511 if (left > 100)
512 left = 100;
513 if (right > 100)
514 right = 100;
515
516 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
517 right = left;
518
519 retvol = left | (right << 8);
520
521 /* Scale volumes */
522 left = mix_cvt[left];
523 right = mix_cvt[right];
524
525 devc->levels[dev] = retvol;
526
527 /*
528 * Set the left channel
529 */
530 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
531
532 /*
533 * Set the right channel
534 */
535 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
536 goto out;
537 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
538
539 out:
540 return retvol;
541 }
542
543 static void ad1848_mixer_reset(ad1848_info * devc)
544 {
545 int i;
546 char name[32];
547
548 devc->mix_devices = &(ad1848_mix_devices[0]);
549
550 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
551
552 for (i = 0; i < 32; i++)
553 devc->mixer_reroute[i] = i;
554
555 devc->supported_rec_devices = MODE1_REC_DEVICES;
556
557 switch (devc->model)
558 {
559 case MD_4231:
560 case MD_4231A:
561 case MD_1845:
562 case MD_1845_SSCAPE:
563 devc->supported_devices = MODE2_MIXER_DEVICES;
564 break;
565
566 case MD_C930:
567 devc->supported_devices = C930_MIXER_DEVICES;
568 devc->mix_devices = &(c930_mix_devices[0]);
569 break;
570
571 case MD_IWAVE:
572 devc->supported_devices = MODE3_MIXER_DEVICES;
573 devc->mix_devices = &(iwave_mix_devices[0]);
574 break;
575
576 case MD_4232:
577 devc->supported_devices = MODE3_MIXER_DEVICES;
578 break;
579
580 case MD_1848:
581 if (soundpro) {
582 devc->supported_devices = SPRO_MIXER_DEVICES;
583 devc->supported_rec_devices = SPRO_REC_DEVICES;
584 devc->mix_devices = &(spro_mix_devices[0]);
585 break;
586 }
587
588 default:
589 devc->supported_devices = MODE1_MIXER_DEVICES;
590 }
591
592 devc->orig_devices = devc->supported_devices;
593 devc->orig_rec_devices = devc->supported_rec_devices;
594
595 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
596
597 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
598 {
599 if (devc->supported_devices & (1 << i))
600 ad1848_mixer_set(devc, i, devc->levels[i]);
601 }
602
603 ad1848_set_recmask(devc, SOUND_MASK_MIC);
604
605 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
606
607 if (!soundpro) {
608 if (devc->mixer_output_port & AUDIO_SPEAKER)
609 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
610 else
611 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
612 } else {
613 /*
614 * From the "wouldn't it be nice if the mixer API had (better)
615 * support for custom stuff" category
616 */
617 /* Enable surround mode and SB16 mixer */
618 ad_write(devc, 16, 0x60);
619 }
620 }
621
622 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
623 {
624 ad1848_info *devc = mixer_devs[dev]->devc;
625 int val;
626
627 if (cmd == SOUND_MIXER_PRIVATE1)
628 {
629 if (get_user(val, (int *)arg))
630 return -EFAULT;
631
632 if (val != 0xffff)
633 {
634 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
635 devc->mixer_output_port = val;
636 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
637 devc->mixer_output_port = val;
638 if (val & AUDIO_SPEAKER)
639 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
640 else
641 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
642 }
643 val = devc->mixer_output_port;
644 return put_user(val, (int *)arg);
645 }
646 if (cmd == SOUND_MIXER_PRIVATE2)
647 {
648 if (get_user(val, (int *)arg))
649 return -EFAULT;
650 return(ad1848_control(AD1848_MIXER_REROUTE, val));
651 }
652 if (((cmd >> 8) & 0xff) == 'M')
653 {
654 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
655 {
656 switch (cmd & 0xff)
657 {
658 case SOUND_MIXER_RECSRC:
659 if (get_user(val, (int *)arg))
660 return -EFAULT;
661 val = ad1848_set_recmask(devc, val);
662 break;
663
664 default:
665 if (get_user(val, (int *)arg))
666 return -EFAULT;
667 val = ad1848_mixer_set(devc, cmd & 0xff, val);
668 break;
669 }
670 return put_user(val, (int *)arg);
671 }
672 else
673 {
674 switch (cmd & 0xff)
675 {
676 /*
677 * Return parameters
678 */
679
680 case SOUND_MIXER_RECSRC:
681 val = devc->recmask;
682 break;
683
684 case SOUND_MIXER_DEVMASK:
685 val = devc->supported_devices;
686 break;
687
688 case SOUND_MIXER_STEREODEVS:
689 val = devc->supported_devices;
690 if (devc->model != MD_C930)
691 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
692 break;
693
694 case SOUND_MIXER_RECMASK:
695 val = devc->supported_rec_devices;
696 break;
697
698 case SOUND_MIXER_CAPS:
699 val=SOUND_CAP_EXCL_INPUT;
700 break;
701
702 default:
703 val = ad1848_mixer_get(devc, cmd & 0xff);
704 break;
705 }
706 return put_user(val, (int *)arg);
707 }
708 }
709 else
710 return -EINVAL;
711 }
712
713 static int ad1848_set_speed(int dev, int arg)
714 {
715 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
716 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
717
718 /*
719 * The sampling speed is encoded in the least significant nibble of I8. The
720 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
721 * three bits select the divisor (indirectly):
722 *
723 * The available speeds are in the following table. Keep the speeds in
724 * the increasing order.
725 */
726 typedef struct
727 {
728 int speed;
729 unsigned char bits;
730 }
731 speed_struct;
732
733 static speed_struct speed_table[] =
734 {
735 {5510, (0 << 1) | 1},
736 {5510, (0 << 1) | 1},
737 {6620, (7 << 1) | 1},
738 {8000, (0 << 1) | 0},
739 {9600, (7 << 1) | 0},
740 {11025, (1 << 1) | 1},
741 {16000, (1 << 1) | 0},
742 {18900, (2 << 1) | 1},
743 {22050, (3 << 1) | 1},
744 {27420, (2 << 1) | 0},
745 {32000, (3 << 1) | 0},
746 {33075, (6 << 1) | 1},
747 {37800, (4 << 1) | 1},
748 {44100, (5 << 1) | 1},
749 {48000, (6 << 1) | 0}
750 };
751
752 int i, n, selected = -1;
753
754 n = sizeof(speed_table) / sizeof(speed_struct);
755
756 if (arg <= 0)
757 return portc->speed;
758
759 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
760 {
761 if (arg < 4000)
762 arg = 4000;
763 if (arg > 50000)
764 arg = 50000;
765
766 portc->speed = arg;
767 portc->speed_bits = speed_table[3].bits;
768 return portc->speed;
769 }
770 if (arg < speed_table[0].speed)
771 selected = 0;
772 if (arg > speed_table[n - 1].speed)
773 selected = n - 1;
774
775 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
776 {
777 if (speed_table[i].speed == arg)
778 selected = i;
779 else if (speed_table[i].speed > arg)
780 {
781 int diff1, diff2;
782
783 diff1 = arg - speed_table[i - 1].speed;
784 diff2 = speed_table[i].speed - arg;
785
786 if (diff1 < diff2)
787 selected = i - 1;
788 else
789 selected = i;
790 }
791 }
792 if (selected == -1)
793 {
794 printk(KERN_WARNING "ad1848: Can't find speed???\n");
795 selected = 3;
796 }
797 portc->speed = speed_table[selected].speed;
798 portc->speed_bits = speed_table[selected].bits;
799 return portc->speed;
800 }
801
802 static short ad1848_set_channels(int dev, short arg)
803 {
804 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
805
806 if (arg != 1 && arg != 2)
807 return portc->channels;
808
809 portc->channels = arg;
810 return arg;
811 }
812
813 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
814 {
815 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
816 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
817
818 static struct format_tbl
819 {
820 int format;
821 unsigned char bits;
822 }
823 format2bits[] =
824 {
825 {
826 0, 0
827 }
828 ,
829 {
830 AFMT_MU_LAW, 1
831 }
832 ,
833 {
834 AFMT_A_LAW, 3
835 }
836 ,
837 {
838 AFMT_IMA_ADPCM, 5
839 }
840 ,
841 {
842 AFMT_U8, 0
843 }
844 ,
845 {
846 AFMT_S16_LE, 2
847 }
848 ,
849 {
850 AFMT_S16_BE, 6
851 }
852 ,
853 {
854 AFMT_S8, 0
855 }
856 ,
857 {
858 AFMT_U16_LE, 0
859 }
860 ,
861 {
862 AFMT_U16_BE, 0
863 }
864 };
865 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
866
867 if (arg == 0)
868 return portc->audio_format;
869
870 if (!(arg & ad_format_mask[devc->model]))
871 arg = AFMT_U8;
872
873 portc->audio_format = arg;
874
875 for (i = 0; i < n; i++)
876 if (format2bits[i].format == arg)
877 {
878 if ((portc->format_bits = format2bits[i].bits) == 0)
879 return portc->audio_format = AFMT_U8; /* Was not supported */
880
881 return arg;
882 }
883 /* Still hanging here. Something must be terribly wrong */
884 portc->format_bits = 0;
885 return portc->audio_format = AFMT_U8;
886 }
887
888 static struct audio_driver ad1848_audio_driver =
889 {
890 ad1848_open,
891 ad1848_close,
892 ad1848_output_block,
893 ad1848_start_input,
894 NULL,
895 ad1848_prepare_for_input,
896 ad1848_prepare_for_output,
897 ad1848_halt,
898 NULL,
899 NULL,
900 ad1848_halt_input,
901 ad1848_halt_output,
902 ad1848_trigger,
903 ad1848_set_speed,
904 ad1848_set_bits,
905 ad1848_set_channels
906 };
907
908 static struct mixer_operations ad1848_mixer_operations =
909 {
910 "SOUNDPORT",
911 "AD1848/CS4248/CS4231",
912 ad1848_mixer_ioctl
913 };
914
915 static int ad1848_open(int dev, int mode)
916 {
917 ad1848_info *devc = NULL;
918 ad1848_port_info *portc;
919 unsigned long flags;
920
921 if (dev < 0 || dev >= num_audiodevs)
922 return -ENXIO;
923
924 devc = (ad1848_info *) audio_devs[dev]->devc;
925 portc = (ad1848_port_info *) audio_devs[dev]->portc;
926
927 save_flags(flags);
928 cli();
929 if (portc->open_mode || (devc->open_mode & mode))
930 {
931 restore_flags(flags);
932 return -EBUSY;
933 }
934 devc->dual_dma = 0;
935
936 if (audio_devs[dev]->flags & DMA_DUPLEX)
937 {
938 devc->dual_dma = 1;
939 }
940 devc->intr_active = 0;
941 devc->audio_mode = 0;
942 devc->open_mode |= mode;
943 portc->open_mode = mode;
944 ad1848_trigger(dev, 0);
945
946 if (mode & OPEN_READ)
947 devc->record_dev = dev;
948 if (mode & OPEN_WRITE)
949 devc->playback_dev = dev;
950 restore_flags(flags);
951 /*
952 * Mute output until the playback really starts. This decreases clicking (hope so).
953 */
954 ad_mute(devc);
955
956 return 0;
957 }
958
959 static void ad1848_close(int dev)
960 {
961 unsigned long flags;
962 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
963 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
964
965 DEB(printk("ad1848_close(void)\n"));
966
967 save_flags(flags);
968 cli();
969
970 devc->intr_active = 0;
971 ad1848_halt(dev);
972
973 devc->audio_mode = 0;
974 devc->open_mode &= ~portc->open_mode;
975 portc->open_mode = 0;
976
977 ad_unmute(devc);
978 restore_flags(flags);
979 }
980
981 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
982 {
983 unsigned long flags, cnt;
984 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
985 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
986
987 cnt = count;
988
989 if (portc->audio_format == AFMT_IMA_ADPCM)
990 {
991 cnt /= 4;
992 }
993 else
994 {
995 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
996 cnt >>= 1;
997 }
998 if (portc->channels > 1)
999 cnt >>= 1;
1000 cnt--;
1001
1002 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1003 intrflag &&
1004 cnt == devc->xfer_count)
1005 {
1006 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1007 devc->intr_active = 1;
1008 return; /*
1009 * Auto DMA mode on. No need to react
1010 */
1011 }
1012 save_flags(flags);
1013 cli();
1014
1015 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1016 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1017
1018 devc->xfer_count = cnt;
1019 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1020 devc->intr_active = 1;
1021 restore_flags(flags);
1022 }
1023
1024 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1025 {
1026 unsigned long flags, cnt;
1027 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1028 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1029
1030 cnt = count;
1031 if (portc->audio_format == AFMT_IMA_ADPCM)
1032 {
1033 cnt /= 4;
1034 }
1035 else
1036 {
1037 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1038 cnt >>= 1;
1039 }
1040 if (portc->channels > 1)
1041 cnt >>= 1;
1042 cnt--;
1043
1044 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1045 intrflag &&
1046 cnt == devc->xfer_count)
1047 {
1048 devc->audio_mode |= PCM_ENABLE_INPUT;
1049 devc->intr_active = 1;
1050 return; /*
1051 * Auto DMA mode on. No need to react
1052 */
1053 }
1054 save_flags(flags);
1055 cli();
1056
1057 if (devc->model == MD_1848)
1058 {
1059 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1060 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1061 }
1062 else
1063 {
1064 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1065 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1066 }
1067
1068 ad_unmute(devc);
1069
1070 devc->xfer_count = cnt;
1071 devc->audio_mode |= PCM_ENABLE_INPUT;
1072 devc->intr_active = 1;
1073 restore_flags(flags);
1074 }
1075
1076 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1077 {
1078 int timeout;
1079 unsigned char fs, old_fs, tmp = 0;
1080 unsigned long flags;
1081 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1082 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1083
1084 ad_mute(devc);
1085
1086 save_flags(flags);
1087 cli();
1088 fs = portc->speed_bits | (portc->format_bits << 5);
1089
1090 if (portc->channels > 1)
1091 fs |= 0x10;
1092
1093 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1094
1095 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1096 {
1097 fs &= 0xf0; /* Mask off the rate select bits */
1098
1099 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1100 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1101 }
1102 old_fs = ad_read(devc, 8);
1103
1104 if (devc->model == MD_4232)
1105 {
1106 tmp = ad_read(devc, 16);
1107 ad_write(devc, 16, tmp | 0x30);
1108 }
1109 if (devc->model == MD_IWAVE)
1110 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1111
1112 ad_write(devc, 8, fs);
1113
1114 /*
1115 * Write to I8 starts resynchronization. Wait until it completes.
1116 */
1117
1118 timeout = 0;
1119 while (timeout < 100 && inb(devc->base) != 0x80)
1120 timeout++;
1121 timeout = 0;
1122 while (timeout < 10000 && inb(devc->base) == 0x80)
1123 timeout++;
1124
1125 if (devc->model == MD_4232)
1126 ad_write(devc, 16, tmp & ~0x30);
1127
1128 ad_leave_MCE(devc); /*
1129 * Starts the calibration process.
1130 */
1131 restore_flags(flags);
1132 devc->xfer_count = 0;
1133
1134 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1135 if (dev == timer_installed && devc->timer_running)
1136 if ((fs & 0x01) != (old_fs & 0x01))
1137 {
1138 ad1848_tmr_reprogram(dev);
1139 }
1140 #endif
1141 ad1848_halt_output(dev);
1142 return 0;
1143 }
1144
1145 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1146 {
1147 int timeout;
1148 unsigned char fs, old_fs, tmp = 0;
1149 unsigned long flags;
1150 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1151 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1152
1153 if (devc->audio_mode)
1154 return 0;
1155
1156 save_flags(flags);
1157 cli();
1158 fs = portc->speed_bits | (portc->format_bits << 5);
1159
1160 if (portc->channels > 1)
1161 fs |= 0x10;
1162
1163 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1164
1165 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1166 {
1167 fs &= 0xf0; /* Mask off the rate select bits */
1168
1169 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1170 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1171 }
1172 if (devc->model == MD_4232)
1173 {
1174 tmp = ad_read(devc, 16);
1175 ad_write(devc, 16, tmp | 0x30);
1176 }
1177 if (devc->model == MD_IWAVE)
1178 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1179
1180 /*
1181 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1182 */
1183
1184 if (devc->model != MD_1848)
1185 {
1186 old_fs = ad_read(devc, 28);
1187 ad_write(devc, 28, fs);
1188
1189 /*
1190 * Write to I28 starts resynchronization. Wait until it completes.
1191 */
1192
1193 timeout = 0;
1194 while (timeout < 100 && inb(devc->base) != 0x80)
1195 timeout++;
1196
1197 timeout = 0;
1198 while (timeout < 10000 && inb(devc->base) == 0x80)
1199 timeout++;
1200
1201 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1202 {
1203 /*
1204 * CS4231 compatible devices don't have separate sampling rate selection
1205 * register for recording an playback. The I8 register is shared so we have to
1206 * set the speed encoding bits of it too.
1207 */
1208 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1209
1210 ad_write(devc, 8, tmp);
1211 /*
1212 * Write to I8 starts resynchronization. Wait until it completes.
1213 */
1214 timeout = 0;
1215 while (timeout < 100 && inb(devc->base) != 0x80)
1216 timeout++;
1217
1218 timeout = 0;
1219 while (timeout < 10000 && inb(devc->base) == 0x80)
1220 timeout++;
1221 }
1222 }
1223 else
1224 { /* For AD1848 set I8. */
1225
1226 old_fs = ad_read(devc, 8);
1227 ad_write(devc, 8, fs);
1228 /*
1229 * Write to I8 starts resynchronization. Wait until it completes.
1230 */
1231 timeout = 0;
1232 while (timeout < 100 && inb(devc->base) != 0x80)
1233 timeout++;
1234 timeout = 0;
1235 while (timeout < 10000 && inb(devc->base) == 0x80)
1236 timeout++;
1237 }
1238
1239 if (devc->model == MD_4232)
1240 ad_write(devc, 16, tmp & ~0x30);
1241
1242 ad_leave_MCE(devc); /*
1243 * Starts the calibration process.
1244 */
1245 restore_flags(flags);
1246 devc->xfer_count = 0;
1247
1248 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1249 if (dev == timer_installed && devc->timer_running)
1250 {
1251 if ((fs & 0x01) != (old_fs & 0x01))
1252 {
1253 ad1848_tmr_reprogram(dev);
1254 }
1255 }
1256 #endif
1257 ad1848_halt_input(dev);
1258 return 0;
1259 }
1260
1261 static void ad1848_halt(int dev)
1262 {
1263 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1264 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1265
1266 unsigned char bits = ad_read(devc, 9);
1267
1268 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1269 ad1848_halt_output(dev);
1270
1271 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1272 ad1848_halt_input(dev);
1273 devc->audio_mode = 0;
1274 }
1275
1276 static void ad1848_halt_input(int dev)
1277 {
1278 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1279 unsigned long flags;
1280
1281 if (!(ad_read(devc, 9) & 0x02))
1282 return; /* Capture not enabled */
1283
1284 save_flags(flags);
1285 cli();
1286
1287 ad_mute(devc);
1288
1289 {
1290 int tmout;
1291
1292 if(!isa_dma_bridge_buggy)
1293 disable_dma(audio_devs[dev]->dmap_in->dma);
1294
1295 for (tmout = 0; tmout < 100000; tmout++)
1296 if (ad_read(devc, 11) & 0x10)
1297 break;
1298 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1299
1300 if(!isa_dma_bridge_buggy)
1301 enable_dma(audio_devs[dev]->dmap_in->dma);
1302 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1303 }
1304
1305 outb(0, io_Status(devc)); /* Clear interrupt status */
1306 outb(0, io_Status(devc)); /* Clear interrupt status */
1307
1308 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1309
1310 restore_flags(flags);
1311 }
1312
1313 static void ad1848_halt_output(int dev)
1314 {
1315 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1316 unsigned long flags;
1317
1318 if (!(ad_read(devc, 9) & 0x01))
1319 return; /* Playback not enabled */
1320
1321 save_flags(flags);
1322 cli();
1323
1324 ad_mute(devc);
1325 {
1326 int tmout;
1327
1328 if(!isa_dma_bridge_buggy)
1329 disable_dma(audio_devs[dev]->dmap_out->dma);
1330
1331 for (tmout = 0; tmout < 100000; tmout++)
1332 if (ad_read(devc, 11) & 0x10)
1333 break;
1334 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1335
1336 if(!isa_dma_bridge_buggy)
1337 enable_dma(audio_devs[dev]->dmap_out->dma);
1338
1339 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1340 }
1341
1342 outb((0), io_Status(devc)); /* Clear interrupt status */
1343 outb((0), io_Status(devc)); /* Clear interrupt status */
1344
1345 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1346
1347 restore_flags(flags);
1348 }
1349
1350 static void ad1848_trigger(int dev, int state)
1351 {
1352 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1353 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1354 unsigned long flags;
1355 unsigned char tmp, old;
1356
1357 save_flags(flags);
1358 cli();
1359 state &= devc->audio_mode;
1360
1361 tmp = old = ad_read(devc, 9);
1362
1363 if (portc->open_mode & OPEN_READ)
1364 {
1365 if (state & PCM_ENABLE_INPUT)
1366 tmp |= 0x02;
1367 else
1368 tmp &= ~0x02;
1369 }
1370 if (portc->open_mode & OPEN_WRITE)
1371 {
1372 if (state & PCM_ENABLE_OUTPUT)
1373 tmp |= 0x01;
1374 else
1375 tmp &= ~0x01;
1376 }
1377 /* ad_mute(devc); */
1378 if (tmp != old)
1379 {
1380 ad_write(devc, 9, tmp);
1381 ad_unmute(devc);
1382 }
1383 restore_flags(flags);
1384 }
1385
1386 static void ad1848_init_hw(ad1848_info * devc)
1387 {
1388 int i;
1389
1390 /*
1391 * Initial values for the indirect registers of CS4248/AD1848.
1392 */
1393 static int init_values[] =
1394 {
1395 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1396 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1397
1398 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1399 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1400 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1401 };
1402
1403
1404 for (i = 0; i < 16; i++)
1405 ad_write(devc, i, init_values[i]);
1406
1407
1408 ad_mute(devc); /* Initialize some variables */
1409 ad_unmute(devc); /* Leave it unmuted now */
1410
1411 if (devc->model > MD_1848)
1412 {
1413 if (devc->model == MD_1845_SSCAPE)
1414 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1415 else
1416 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1417
1418 if (devc->model == MD_IWAVE)
1419 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1420
1421 if (devc-> model != MD_1845_SSCAPE)
1422 for (i = 16; i < 32; i++)
1423 ad_write(devc, i, init_values[i]);
1424
1425 if (devc->model == MD_IWAVE)
1426 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1427 }
1428 if (devc->model > MD_1848)
1429 {
1430 if (devc->audio_flags & DMA_DUPLEX)
1431 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1432 else
1433 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1434
1435 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1436 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1437
1438 if (devc->model == MD_IWAVE)
1439 { /* Some magic Interwave specific initialization */
1440 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1441 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1442 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1443 }
1444 }
1445 else
1446 {
1447 devc->audio_flags &= ~DMA_DUPLEX;
1448 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1449 if (soundpro)
1450 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1451 }
1452
1453 outb((0), io_Status(devc)); /* Clear pending interrupts */
1454
1455 /*
1456 * Toggle the MCE bit. It completes the initialization phase.
1457 */
1458
1459 ad_enter_MCE(devc); /* In case the bit was off */
1460 ad_leave_MCE(devc);
1461
1462 ad1848_mixer_reset(devc);
1463 }
1464
1465 int ad1848_detect(int io_base, int *ad_flags, int *osp)
1466 {
1467 unsigned char tmp;
1468 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1469 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1470 int optiC930 = 0; /* OPTi 82C930 flag */
1471 int interwave = 0;
1472 int ad1847_flag = 0;
1473 int cs4248_flag = 0;
1474 int sscape_flag = 0;
1475
1476 int i;
1477
1478 DDB(printk("ad1848_detect(%x)\n", io_base));
1479
1480 if (ad_flags)
1481 {
1482 if (*ad_flags == 0x12345678)
1483 {
1484 interwave = 1;
1485 *ad_flags = 0;
1486 }
1487
1488 if (*ad_flags == 0x87654321)
1489 {
1490 sscape_flag = 1;
1491 *ad_flags = 0;
1492 }
1493
1494 if (*ad_flags == 0x12345677)
1495 {
1496 cs4248_flag = 1;
1497 *ad_flags = 0;
1498 }
1499 }
1500 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1501 {
1502 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1503 return 0;
1504 }
1505 if (check_region(io_base, 4))
1506 {
1507 printk(KERN_ERR "ad1848.c: Port %x not free.\n", io_base);
1508 return 0;
1509 }
1510 devc->base = io_base;
1511 devc->irq_ok = 0;
1512 devc->timer_running = 0;
1513 devc->MCE_bit = 0x40;
1514 devc->irq = 0;
1515 devc->open_mode = 0;
1516 devc->chip_name = devc->name = "AD1848";
1517 devc->model = MD_1848; /* AD1848 or CS4248 */
1518 devc->levels = NULL;
1519 devc->debug_flag = 0;
1520
1521 /*
1522 * Check that the I/O address is in use.
1523 *
1524 * The bit 0x80 of the base I/O port is known to be 0 after the
1525 * chip has performed its power on initialization. Just assume
1526 * this has happened before the OS is starting.
1527 *
1528 * If the I/O address is unused, it typically returns 0xff.
1529 */
1530
1531 if (inb(devc->base) == 0xff)
1532 {
1533 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1534 }
1535
1536 /*
1537 * Wait for the device to stop initialization
1538 */
1539
1540 DDB(printk("ad1848_detect() - step 0\n"));
1541
1542 for (i = 0; i < 10000000; i++)
1543 {
1544 unsigned char x = inb(devc->base);
1545
1546 if (x == 0xff || !(x & 0x80))
1547 break;
1548 }
1549
1550 DDB(printk("ad1848_detect() - step A\n"));
1551
1552 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1553 ad_leave_MCE(devc);
1554
1555 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1556 {
1557 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1558 return 0;
1559 }
1560
1561 /*
1562 * Test if it's possible to change contents of the indirect registers.
1563 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1564 * so try to avoid using it.
1565 */
1566
1567 DDB(printk("ad1848_detect() - step B\n"));
1568 ad_write(devc, 0, 0xaa);
1569 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1570
1571 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1572 {
1573 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1574 ad1847_flag = 1;
1575 else
1576 {
1577 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1578 return 0;
1579 }
1580 }
1581 DDB(printk("ad1848_detect() - step C\n"));
1582 ad_write(devc, 0, 0x45);
1583 ad_write(devc, 1, 0xaa);
1584
1585 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1586 {
1587 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1588 ad1847_flag = 1;
1589 else
1590 {
1591 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1592 return 0;
1593 }
1594 }
1595
1596 /*
1597 * The indirect register I12 has some read only bits. Let's
1598 * try to change them.
1599 */
1600
1601 DDB(printk("ad1848_detect() - step D\n"));
1602 tmp = ad_read(devc, 12);
1603 ad_write(devc, 12, (~tmp) & 0x0f);
1604
1605 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1606 {
1607 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1608 return 0;
1609 }
1610
1611 /*
1612 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1613 * 0x01=RevB and 0x0A=RevC.
1614 */
1615
1616 /*
1617 * The original AD1848/CS4248 has just 15 indirect registers. This means
1618 * that I0 and I16 should return the same value (etc.).
1619 * However this doesn't work with CS4248. Actually it seems to be impossible
1620 * to detect if the chip is a CS4231 or CS4248.
1621 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1622 * with CS4231.
1623 */
1624
1625 /*
1626 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1627 * with it. Accept this situation as a possible indication of this chip.
1628 */
1629
1630 DDB(printk("ad1848_detect() - step F\n"));
1631 ad_write(devc, 12, 0); /* Mode2=disabled */
1632
1633 for (i = 0; i < 16; i++)
1634 {
1635 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1636 {
1637 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1638 if (!ad1847_flag)
1639 optiC930 = 1;
1640 break;
1641 }
1642 }
1643
1644 /*
1645 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1646 * The bit 0x80 is always 1 in CS4248 and CS4231.
1647 */
1648
1649 DDB(printk("ad1848_detect() - step G\n"));
1650
1651 if (ad_flags && *ad_flags == 400)
1652 *ad_flags = 0;
1653 else
1654 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1655
1656
1657 if (ad_flags)
1658 *ad_flags = 0;
1659
1660 tmp1 = ad_read(devc, 12);
1661 if (tmp1 & 0x80)
1662 {
1663 if (ad_flags)
1664 *ad_flags |= AD_F_CS4248;
1665
1666 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1667 }
1668 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1669 {
1670 /*
1671 * CS4231 detected - is it?
1672 *
1673 * Verify that setting I0 doesn't change I16.
1674 */
1675
1676 DDB(printk("ad1848_detect() - step H\n"));
1677 ad_write(devc, 16, 0); /* Set I16 to known value */
1678
1679 ad_write(devc, 0, 0x45);
1680 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1681 {
1682 ad_write(devc, 0, 0xaa);
1683 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1684 {
1685 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1686 return 0;
1687 }
1688
1689 /*
1690 * Verify that some bits of I25 are read only.
1691 */
1692
1693 DDB(printk("ad1848_detect() - step I\n"));
1694 tmp1 = ad_read(devc, 25); /* Original bits */
1695 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1696 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1697 {
1698 int id;
1699
1700 /*
1701 * It's at least CS4231
1702 */
1703
1704 devc->chip_name = "CS4231";
1705 devc->model = MD_4231;
1706
1707 /*
1708 * It could be an AD1845 or CS4231A as well.
1709 * CS4231 and AD1845 report the same revision info in I25
1710 * while the CS4231A reports different.
1711 */
1712
1713 id = ad_read(devc, 25);
1714 if ((id & 0xe7) == 0x80) /* Device busy??? */
1715 id = ad_read(devc, 25);
1716 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1717 id = ad_read(devc, 25);
1718 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1719
1720 if ((id & 0xe7) == 0x80) {
1721 /*
1722 * It must be a CS4231 or AD1845. The register I23 of
1723 * CS4231 is undefined and it appears to be read only.
1724 * AD1845 uses I23 for setting sample rate. Assume
1725 * the chip is AD1845 if I23 is changeable.
1726 */
1727
1728 unsigned char tmp = ad_read(devc, 23);
1729 ad_write(devc, 23, ~tmp);
1730
1731 if (interwave)
1732 {
1733 devc->model = MD_IWAVE;
1734 devc->chip_name = "IWave";
1735 }
1736 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1737 {
1738 devc->chip_name = "AD1845";
1739 devc->model = MD_1845;
1740 }
1741 else if (cs4248_flag)
1742 {
1743 if (ad_flags)
1744 *ad_flags |= AD_F_CS4248;
1745 devc->chip_name = "CS4248";
1746 devc->model = MD_1848;
1747 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1748 }
1749 ad_write(devc, 23, tmp); /* Restore */
1750 }
1751 else
1752 {
1753 switch (id & 0x1f) {
1754 case 3: /* CS4236/CS4235 */
1755 {
1756 int xid;
1757 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1758 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1759 xid = inb(io_Indexed_Data(devc));
1760 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1761 if ((xid & 0x1f) == 0x1d) {
1762 devc->chip_name = "CS4235";
1763 devc->model = MD_4235;
1764 } else {
1765 devc->chip_name = "CS4236";
1766 devc->model = MD_4232;
1767 }
1768 }
1769 break;
1770
1771 case 2: /* CS4232/CS4232A */
1772 devc->chip_name = "CS4232";
1773 devc->model = MD_4232;
1774 break;
1775
1776 case 0:
1777 if ((id & 0xe0) == 0xa0)
1778 {
1779 devc->chip_name = "CS4231A";
1780 devc->model = MD_4231A;
1781 }
1782 else
1783 {
1784 devc->chip_name = "CS4321";
1785 devc->model = MD_4231;
1786 }
1787 break;
1788
1789 default: /* maybe */
1790 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1791 if (optiC930)
1792 {
1793 devc->chip_name = "82C930";
1794 devc->model = MD_C930;
1795 }
1796 else
1797 {
1798 devc->chip_name = "CS4231";
1799 devc->model = MD_4231;
1800 }
1801 }
1802 }
1803 }
1804 ad_write(devc, 25, tmp1); /* Restore bits */
1805
1806 DDB(printk("ad1848_detect() - step K\n"));
1807 }
1808 } else if (tmp1 == 0x0a) {
1809 /*
1810 * Is it perhaps a SoundPro CMI8330?
1811 * If so, then we should be able to change indirect registers
1812 * greater than I15 after activating MODE2, even though reading
1813 * back I12 does not show it.
1814 */
1815
1816 /*
1817 * Let's try comparing register values
1818 */
1819 for (i = 0; i < 16; i++) {
1820 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1821 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1822 soundpro = 1;
1823 devc->chip_name = "SoundPro CMI 8330";
1824 break;
1825 }
1826 }
1827 }
1828
1829 DDB(printk("ad1848_detect() - step L\n"));
1830 if (ad_flags)
1831 {
1832 if (devc->model != MD_1848)
1833 *ad_flags |= AD_F_CS4231;
1834 }
1835 DDB(printk("ad1848_detect() - Detected OK\n"));
1836
1837 if (devc->model == MD_1848 && ad1847_flag)
1838 devc->chip_name = "AD1847";
1839
1840
1841 if (sscape_flag == 1)
1842 devc->model = MD_1845_SSCAPE;
1843
1844 return 1;
1845 }
1846
1847 int ad1848_init(char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, int *osp)
1848 {
1849 /*
1850 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1851 * so that this driver doesn't need to allocate/deallocate it.
1852 * The actually used IRQ is ABS(irq).
1853 */
1854
1855
1856 int my_dev;
1857 char dev_name[100];
1858 int e;
1859
1860 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1861
1862 ad1848_port_info *portc = NULL;
1863
1864 devc->irq = (irq > 0) ? irq : 0;
1865 devc->open_mode = 0;
1866 devc->timer_ticks = 0;
1867 devc->dma1 = dma_playback;
1868 devc->dma2 = dma_capture;
1869 devc->audio_flags = DMA_AUTOMODE;
1870 devc->playback_dev = devc->record_dev = 0;
1871 if (name != NULL)
1872 devc->name = name;
1873
1874 if (name != NULL && name[0] != 0)
1875 sprintf(dev_name,
1876 "%s (%s)", name, devc->chip_name);
1877 else
1878 sprintf(dev_name,
1879 "Generic audio codec (%s)", devc->chip_name);
1880
1881 request_region(devc->base, 4, devc->name);
1882
1883 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1884
1885 if (devc->model == MD_1848 || devc->model == MD_C930)
1886 devc->audio_flags |= DMA_HARDSTOP;
1887
1888 if (devc->model > MD_1848)
1889 {
1890 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1891 devc->audio_flags &= ~DMA_DUPLEX;
1892 else
1893 devc->audio_flags |= DMA_DUPLEX;
1894 }
1895
1896 portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1897 if(portc==NULL)
1898 return -1;
1899
1900 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
1901 dev_name,
1902 &ad1848_audio_driver,
1903 sizeof(struct audio_driver),
1904 devc->audio_flags,
1905 ad_format_mask[devc->model],
1906 devc,
1907 dma_playback,
1908 dma_capture)) < 0)
1909 {
1910 kfree(portc);
1911 portc=NULL;
1912 return -1;
1913 }
1914
1915 audio_devs[my_dev]->portc = portc;
1916 audio_devs[my_dev]->mixer_dev = -1;
1917 memset((char *) portc, 0, sizeof(*portc));
1918
1919 nr_ad1848_devs++;
1920
1921 ad1848_init_hw(devc);
1922
1923 if (irq > 0)
1924 {
1925 devc->dev_no = my_dev;
1926 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
1927 {
1928 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
1929 /* Don't free it either then.. */
1930 devc->irq = 0;
1931 }
1932 if (capabilities[devc->model].flags & CAP_F_TIMER)
1933 {
1934 #ifndef __SMP__
1935 int x;
1936 unsigned char tmp = ad_read(devc, 16);
1937 #endif
1938
1939 devc->timer_ticks = 0;
1940
1941 ad_write(devc, 21, 0x00); /* Timer MSB */
1942 ad_write(devc, 20, 0x10); /* Timer LSB */
1943 #ifndef __SMP__
1944 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
1945 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1946 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
1947
1948 if (devc->timer_ticks == 0)
1949 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
1950 else
1951 {
1952 DDB(printk("Interrupt test OK\n"));
1953 devc->irq_ok = 1;
1954 }
1955 #else
1956 devc->irq_ok=1;
1957 #endif
1958 }
1959 else
1960 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
1961 } else if (irq < 0)
1962 irq2dev[-irq] = devc->dev_no = my_dev;
1963
1964 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1965 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
1966 devc->irq_ok)
1967 ad1848_tmr_install(my_dev);
1968 #endif
1969
1970 if (!share_dma)
1971 {
1972 if (sound_alloc_dma(dma_playback, devc->name))
1973 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
1974
1975 if (dma_capture != dma_playback)
1976 if (sound_alloc_dma(dma_capture, devc->name))
1977 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
1978 }
1979 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
1980 dev_name,
1981 &ad1848_mixer_operations,
1982 sizeof(struct mixer_operations),
1983 devc)) >= 0)
1984 {
1985 audio_devs[my_dev]->mixer_dev = e;
1986 }
1987 return my_dev;
1988 }
1989
1990 int ad1848_control(int cmd, int arg)
1991 {
1992 ad1848_info *devc;
1993
1994 if (nr_ad1848_devs < 1)
1995 return -ENODEV;
1996
1997 devc = &adev_info[nr_ad1848_devs - 1];
1998
1999 switch (cmd)
2000 {
2001 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
2002 if (devc->model != MD_1845 || devc->model != MD_1845_SSCAPE)
2003 return -EINVAL;
2004 ad_enter_MCE(devc);
2005 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2006 ad_leave_MCE(devc);
2007 break;
2008
2009 case AD1848_MIXER_REROUTE:
2010 {
2011 int o = (arg >> 8) & 0xff;
2012 int n = arg & 0xff;
2013
2014 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2015 return -EINVAL;
2016
2017 if (!(devc->supported_devices & (1 << o)) &&
2018 !(devc->supported_rec_devices & (1 << o)))
2019 return -EINVAL;
2020
2021 if (n == SOUND_MIXER_NONE)
2022 { /* Just hide this control */
2023 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2024 devc->supported_devices &= ~(1 << o);
2025 devc->supported_rec_devices &= ~(1 << o);
2026 break;
2027 }
2028
2029 /* Make the mixer control identified by o to appear as n */
2030 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2031 return -EINVAL;
2032
2033 devc->mixer_reroute[n] = o; /* Rename the control */
2034 if (devc->supported_devices & (1 << o))
2035 devc->supported_devices |= (1 << n);
2036 if (devc->supported_rec_devices & (1 << o))
2037 devc->supported_rec_devices |= (1 << n);
2038
2039 devc->supported_devices &= ~(1 << o);
2040 devc->supported_rec_devices &= ~(1 << o);
2041 }
2042 break;
2043 }
2044 return 0;
2045 }
2046
2047 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2048 {
2049 int i, mixer, dev = 0;
2050 ad1848_info *devc = NULL;
2051
2052 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2053 {
2054 if (adev_info[i].base == io_base)
2055 {
2056 devc = &adev_info[i];
2057 dev = devc->dev_no;
2058 }
2059 }
2060
2061 if (devc != NULL)
2062 {
2063 if(audio_devs[dev]->portc!=NULL)
2064 kfree(audio_devs[dev]->portc);
2065 release_region(devc->base, 4);
2066
2067 if (!share_dma)
2068 {
2069 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2070 free_irq(devc->irq, (void *)devc->dev_no);
2071
2072 sound_free_dma(dma_playback);
2073
2074 if (dma_playback != dma_capture)
2075 sound_free_dma(dma_capture);
2076
2077 }
2078 mixer = audio_devs[devc->dev_no]->mixer_dev;
2079 if(mixer>=0)
2080 sound_unload_mixerdev(mixer);
2081
2082 nr_ad1848_devs--;
2083 for ( ; i < nr_ad1848_devs ; i++)
2084 adev_info[i] = adev_info[i+1];
2085 }
2086 else
2087 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2088 }
2089
2090 void adintr(int irq, void *dev_id, struct pt_regs *dummy)
2091 {
2092 unsigned char status;
2093 ad1848_info *devc;
2094 int dev;
2095 int alt_stat = 0xff;
2096 unsigned char c930_stat = 0;
2097 int cnt = 0;
2098
2099 dev = (int)dev_id;
2100 devc = (ad1848_info *) audio_devs[dev]->devc;
2101
2102 interrupt_again: /* Jump back here if int status doesn't reset */
2103
2104 status = inb(io_Status(devc));
2105
2106 if (status == 0x80)
2107 printk(KERN_DEBUG "adintr: Why?\n");
2108 if (devc->model == MD_1848)
2109 outb((0), io_Status(devc)); /* Clear interrupt status */
2110
2111 if (status & 0x01)
2112 {
2113 if (devc->model == MD_C930)
2114 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2115 unsigned long flags;
2116
2117 save_flags(flags);
2118 cli();
2119
2120 /* 0xe0e is C930 address port
2121 * 0xe0f is C930 data port
2122 */
2123 outb(11, 0xe0e);
2124 c930_stat = inb(0xe0f);
2125 outb((~c930_stat), 0xe0f);
2126
2127 restore_flags(flags);
2128
2129 alt_stat = (c930_stat << 2) & 0x30;
2130 }
2131 else if (devc->model != MD_1848)
2132 {
2133 alt_stat = ad_read(devc, 24);
2134 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2135 }
2136
2137 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2138 {
2139 DMAbuf_inputintr(devc->record_dev);
2140 }
2141 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2142 (alt_stat & 0x10))
2143 {
2144 DMAbuf_outputintr(devc->playback_dev, 1);
2145 }
2146 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2147 {
2148 devc->timer_ticks++;
2149 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
2150 if (timer_installed == dev && devc->timer_running)
2151 sound_timer_interrupt();
2152 #endif
2153 }
2154 }
2155 /*
2156 * Sometimes playback or capture interrupts occur while a timer interrupt
2157 * is being handled. The interrupt will not be retriggered if we don't
2158 * handle it now. Check if an interrupt is still pending and restart
2159 * the handler in this case.
2160 */
2161 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2162 {
2163 goto interrupt_again;
2164 }
2165 }
2166
2167 /*
2168 * Experimental initialization sequence for the integrated sound system
2169 * of the Compaq Deskpro M.
2170 */
2171
2172 static int init_deskpro_m(struct address_info *hw_config)
2173 {
2174 unsigned char tmp;
2175
2176 if ((tmp = inb(0xc44)) == 0xff)
2177 {
2178 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2179 return 0;
2180 }
2181
2182 outb(0x10, 0xc44);
2183 outb(0x40, 0xc45);
2184 outb(0x00, 0xc46);
2185 outb(0xe8, 0xc47);
2186 outb(0x14, 0xc44);
2187 outb(0x40, 0xc45);
2188 outb(0x00, 0xc46);
2189 outb(0xe8, 0xc47);
2190 outb(0x10, 0xc44);
2191
2192 return 1;
2193 }
2194
2195 /*
2196 * Experimental initialization sequence for the integrated sound system
2197 * of Compaq Deskpro XL.
2198 */
2199
2200 static int init_deskpro(struct address_info *hw_config)
2201 {
2202 unsigned char tmp;
2203
2204 if ((tmp = inb(0xc44)) == 0xff)
2205 {
2206 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2207 return 0;
2208 }
2209 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2210 if (inb(0xc44) != 0x04)
2211 {
2212 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2213 return 0;
2214 }
2215 /*
2216 * OK. It looks like a Deskpro so let's proceed.
2217 */
2218
2219 /*
2220 * I/O port 0xc44 Audio configuration register.
2221 *
2222 * bits 0xc0: Audio revision bits
2223 * 0x00 = Compaq Business Audio
2224 * 0x40 = MS Sound System Compatible (reset default)
2225 * 0x80 = Reserved
2226 * 0xc0 = Reserved
2227 * bit 0x20: No Wait State Enable
2228 * 0x00 = Disabled (reset default, DMA mode)
2229 * 0x20 = Enabled (programmed I/O mode)
2230 * bit 0x10: MS Sound System Decode Enable
2231 * 0x00 = Decoding disabled (reset default)
2232 * 0x10 = Decoding enabled
2233 * bit 0x08: FM Synthesis Decode Enable
2234 * 0x00 = Decoding Disabled (reset default)
2235 * 0x08 = Decoding enabled
2236 * bit 0x04 Bank select
2237 * 0x00 = Bank 0
2238 * 0x04 = Bank 1
2239 * bits 0x03 MSS Base address
2240 * 0x00 = 0x530 (reset default)
2241 * 0x01 = 0x604
2242 * 0x02 = 0xf40
2243 * 0x03 = 0xe80
2244 */
2245
2246 #ifdef DEBUGXL
2247 /* Debug printing */
2248 printk("Port 0xc44 (before): ");
2249 outb((tmp & ~0x04), 0xc44);
2250 printk("%02x ", inb(0xc44));
2251 outb((tmp | 0x04), 0xc44);
2252 printk("%02x\n", inb(0xc44));
2253 #endif
2254
2255 /* Set bank 1 of the register */
2256 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2257
2258 switch (hw_config->io_base)
2259 {
2260 case 0x530:
2261 tmp |= 0x00;
2262 break;
2263 case 0x604:
2264 tmp |= 0x01;
2265 break;
2266 case 0xf40:
2267 tmp |= 0x02;
2268 break;
2269 case 0xe80:
2270 tmp |= 0x03;
2271 break;
2272 default:
2273 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2274 return 0;
2275 }
2276 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2277
2278 #ifdef DEBUGXL
2279 /* Debug printing */
2280 printk("Port 0xc44 (after): ");
2281 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2282 printk("%02x ", inb(0xc44));
2283 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2284 printk("%02x\n", inb(0xc44));
2285 #endif
2286
2287 /*
2288 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2289 *
2290 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2291 * bank=0, bit 0x01: SBIC Power Control Bit
2292 * 0x00 = Powered up
2293 * 0x01 = Powered down
2294 * bank=1, bits 0xfc: MSS ID (default=0x40)
2295 */
2296
2297 #ifdef DEBUGXL
2298 /* Debug printing */
2299 printk("Port 0xc45 (before): ");
2300 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2301 printk("%02x ", inb(0xc45));
2302 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2303 printk("%02x\n", inb(0xc45));
2304 #endif
2305
2306 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2307 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2308 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2309 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2310
2311 #ifdef DEBUGXL
2312 /* Debug printing */
2313 printk("Port 0xc45 (after): ");
2314 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2315 printk("%02x ", inb(0xc45));
2316 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2317 printk("%02x\n", inb(0xc45));
2318 #endif
2319
2320
2321 /*
2322 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2323 *
2324 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2325 * bank=1, bits 0xff: Audio addressing ASIC id
2326 */
2327
2328 #ifdef DEBUGXL
2329 /* Debug printing */
2330 printk("Port 0xc46 (before): ");
2331 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2332 printk("%02x ", inb(0xc46));
2333 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2334 printk("%02x\n", inb(0xc46));
2335 #endif
2336
2337 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2338 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2339 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2340 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2341
2342 #ifdef DEBUGXL
2343 /* Debug printing */
2344 printk("Port 0xc46 (after): ");
2345 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2346 printk("%02x ", inb(0xc46));
2347 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2348 printk("%02x\n", inb(0xc46));
2349 #endif
2350
2351 /*
2352 * I/O port 0xc47 FM Address Decode Register.
2353 *
2354 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2355 * bank=1, bits 0xff: Reserved
2356 */
2357
2358 #ifdef DEBUGXL
2359 /* Debug printing */
2360 printk("Port 0xc47 (before): ");
2361 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2362 printk("%02x ", inb(0xc47));
2363 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2364 printk("%02x\n", inb(0xc47));
2365 #endif
2366
2367 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2368 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2369 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2370 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2371
2372 #ifdef DEBUGXL
2373 /* Debug printing */
2374 printk("Port 0xc47 (after): ");
2375 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2376 printk("%02x ", inb(0xc47));
2377 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2378 printk("%02x\n", inb(0xc47));
2379 #endif
2380
2381 /*
2382 * I/O port 0xc6f = Audio Disable Function Register
2383 */
2384
2385 #ifdef DEBUGXL
2386 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2387 #endif
2388
2389 outb((0x80), 0xc6f);
2390
2391 #ifdef DEBUGXL
2392 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2393 #endif
2394
2395 return 1;
2396 }
2397
2398 int probe_ms_sound(struct address_info *hw_config)
2399 {
2400 unsigned char tmp;
2401
2402 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2403
2404 if (check_region(hw_config->io_base, 8))
2405 {
2406 printk(KERN_ERR "MSS: I/O port conflict\n");
2407 return 0;
2408 }
2409 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2410 {
2411 /* check_opl3(0x388, hw_config); */
2412 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2413 }
2414
2415 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2416 {
2417 if (!init_deskpro(hw_config))
2418 return 0;
2419 }
2420
2421 if (deskpro_m) /* Compaq Deskpro M */
2422 {
2423 if (!init_deskpro_m(hw_config))
2424 return 0;
2425 }
2426
2427 /*
2428 * Check if the IO port returns valid signature. The original MS Sound
2429 * system returns 0x04 while some cards (AudioTrix Pro for example)
2430 * return 0x00 or 0x0f.
2431 */
2432
2433 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2434 {
2435 int ret;
2436
2437 DDB(printk("I/O address is inactive (%x)\n", tmp));
2438 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2439 return 0;
2440 return 1;
2441 }
2442 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2443 if ((tmp & 0x3f) != 0x04 &&
2444 (tmp & 0x3f) != 0x0f &&
2445 (tmp & 0x3f) != 0x00)
2446 {
2447 int ret;
2448
2449 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2450 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2451 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2452 return 0;
2453
2454 hw_config->card_subtype = 1;
2455 return 1;
2456 }
2457 if ((hw_config->irq != 5) &&
2458 (hw_config->irq != 7) &&
2459 (hw_config->irq != 9) &&
2460 (hw_config->irq != 10) &&
2461 (hw_config->irq != 11) &&
2462 (hw_config->irq != 12))
2463 {
2464 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2465 return 0;
2466 }
2467 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2468 {
2469 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2470 return 0;
2471 }
2472 /*
2473 * Check that DMA0 is not in use with a 8 bit board.
2474 */
2475
2476 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2477 {
2478 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2479 return 0;
2480 }
2481 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2482 {
2483 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2484 return 0;
2485 }
2486 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2487 }
2488
2489 void attach_ms_sound(struct address_info *hw_config)
2490 {
2491 static signed char interrupt_bits[12] =
2492 {
2493 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2494 };
2495 signed char bits;
2496 char dma2_bit = 0;
2497
2498 static char dma_bits[4] =
2499 {
2500 1, 2, 0, 3
2501 };
2502
2503 int config_port = hw_config->io_base + 0;
2504 int version_port = hw_config->io_base + 3;
2505 int dma = hw_config->dma;
2506 int dma2 = hw_config->dma2;
2507
2508 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2509 {
2510 hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2511 hw_config->irq,
2512 hw_config->dma,
2513 hw_config->dma2, 0, hw_config->osp);
2514 request_region(hw_config->io_base, 4, "WSS config");
2515 return;
2516 }
2517 /*
2518 * Set the IRQ and DMA addresses.
2519 */
2520
2521 bits = interrupt_bits[hw_config->irq];
2522 if (bits == -1)
2523 {
2524 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2525 return;
2526 }
2527 outb((bits | 0x40), config_port);
2528 if ((inb(version_port) & 0x40) == 0)
2529 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2530
2531 /*
2532 * Handle the capture DMA channel
2533 */
2534
2535 if (dma2 != -1 && dma2 != dma)
2536 {
2537 if (!((dma == 0 && dma2 == 1) ||
2538 (dma == 1 && dma2 == 0) ||
2539 (dma == 3 && dma2 == 0)))
2540 { /* Unsupported combination. Try to swap channels */
2541 int tmp = dma;
2542
2543 dma = dma2;
2544 dma2 = tmp;
2545 }
2546 if ((dma == 0 && dma2 == 1) ||
2547 (dma == 1 && dma2 == 0) ||
2548 (dma == 3 && dma2 == 0))
2549 {
2550 dma2_bit = 0x04; /* Enable capture DMA */
2551 }
2552 else
2553 {
2554 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2555 dma2 = dma;
2556 }
2557 }
2558 else
2559 {
2560 dma2 = dma;
2561 }
2562
2563 hw_config->dma = dma;
2564 hw_config->dma2 = dma2;
2565
2566 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2567
2568 hw_config->slots[0] = ad1848_init("MSS audio codec", hw_config->io_base + 4,
2569 hw_config->irq,
2570 dma,
2571 dma2, 0,
2572 hw_config->osp);
2573 request_region(hw_config->io_base, 4, "WSS config");
2574 }
2575
2576 void unload_ms_sound(struct address_info *hw_config)
2577 {
2578 ad1848_unload(hw_config->io_base + 4,
2579 hw_config->irq,
2580 hw_config->dma,
2581 hw_config->dma2, 0);
2582 sound_unload_audiodev(hw_config->slots[0]);
2583 release_region(hw_config->io_base, 4);
2584 }
2585
2586 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
2587
2588 /*
2589 * Timer stuff (for /dev/music).
2590 */
2591
2592 static unsigned int current_interval = 0;
2593
2594 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2595 {
2596 unsigned long flags;
2597 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2598 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2599 unsigned long divider;
2600
2601 save_flags(flags);
2602 cli();
2603
2604 /*
2605 * Length of the timer interval (in nanoseconds) depends on the
2606 * selected crystal oscillator. Check this from bit 0x01 of I8.
2607 *
2608 * AD1845 has just one oscillator which has cycle time of 10.050 us
2609 * (when a 24.576 MHz xtal oscillator is used).
2610 *
2611 * Convert requested interval to nanoseconds before computing
2612 * the timer divider.
2613 */
2614
2615 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2616 xtal_nsecs = 10050;
2617 else if (ad_read(devc, 8) & 0x01)
2618 xtal_nsecs = 9920;
2619 else
2620 xtal_nsecs = 9969;
2621
2622 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2623
2624 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2625 divider = 100;
2626
2627 if (divider > 65535) /* Overflow check */
2628 divider = 65535;
2629
2630 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2631 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2632 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2633 devc->timer_running = 1;
2634 restore_flags(flags);
2635
2636 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2637 }
2638
2639 static void ad1848_tmr_reprogram(int dev)
2640 {
2641 /*
2642 * Audio driver has changed sampling rate so that a different xtal
2643 * oscillator was selected. We have to reprogram the timer rate.
2644 */
2645
2646 ad1848_tmr_start(dev, current_interval);
2647 sound_timer_syncinterval(current_interval);
2648 }
2649
2650 static void ad1848_tmr_disable(int dev)
2651 {
2652 unsigned long flags;
2653 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2654
2655 save_flags(flags);
2656 cli();
2657 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2658 devc->timer_running = 0;
2659 restore_flags(flags);
2660 }
2661
2662 static void ad1848_tmr_restart(int dev)
2663 {
2664 unsigned long flags;
2665 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2666
2667 if (current_interval == 0)
2668 return;
2669
2670 save_flags(flags);
2671 cli();
2672 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2673 devc->timer_running = 1;
2674 restore_flags(flags);
2675 }
2676
2677 static struct sound_lowlev_timer ad1848_tmr =
2678 {
2679 0,
2680 2,
2681 ad1848_tmr_start,
2682 ad1848_tmr_disable,
2683 ad1848_tmr_restart
2684 };
2685
2686 static int ad1848_tmr_install(int dev)
2687 {
2688 if (timer_installed != -1)
2689 return 0; /* Don't install another timer */
2690
2691 timer_installed = ad1848_tmr.dev = dev;
2692 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2693
2694 return 1;
2695 }
2696 #endif
2697
2698
2699 EXPORT_SYMBOL(ad1848_detect);
2700 EXPORT_SYMBOL(ad1848_init);
2701 EXPORT_SYMBOL(ad1848_unload);
2702 EXPORT_SYMBOL(ad1848_control);
2703 EXPORT_SYMBOL(adintr);
2704 EXPORT_SYMBOL(probe_ms_sound);
2705 EXPORT_SYMBOL(attach_ms_sound);
2706 EXPORT_SYMBOL(unload_ms_sound);
2707
2708 #ifdef MODULE
2709
2710 MODULE_PARM(io, "i"); /* I/O for a raw AD1848 card */
2711 MODULE_PARM(irq, "i"); /* IRQ to use */
2712 MODULE_PARM(dma, "i"); /* First DMA channel */
2713 MODULE_PARM(dma2, "i"); /* Second DMA channel */
2714 MODULE_PARM(type, "i"); /* Card type */
2715 MODULE_PARM(deskpro_xl, "i"); /* Special magic for Deskpro XL boxen */
2716 MODULE_PARM(deskpro_m, "i"); /* Special magic for Deskpro M box */
2717 MODULE_PARM(soundpro, "i"); /* More special magic for SoundPro chips */
2718
2719 int io = -1;
2720 int irq = -1;
2721 int dma = -1;
2722 int dma2 = -1;
2723 int type = 0;
2724
2725 static int loaded = 0;
2726
2727 struct address_info hw_config;
2728
2729 int init_module(void)
2730 {
2731 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2732 if(io != -1)
2733 {
2734 if(irq == -1 || dma == -1)
2735 {
2736 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
2737 return -EINVAL;
2738 }
2739 hw_config.irq = irq;
2740 hw_config.io_base = io;
2741 hw_config.dma = dma;
2742 hw_config.dma2 = dma2;
2743 hw_config.card_subtype = type;
2744 if(!probe_ms_sound(&hw_config))
2745 return -ENODEV;
2746 attach_ms_sound(&hw_config);
2747 loaded=1;
2748 }
2749 SOUND_LOCK;
2750 return 0;
2751 }
2752
2753 void cleanup_module(void)
2754 {
2755 SOUND_LOCK_END;
2756 if(loaded)
2757 unload_ms_sound(&hw_config);
2758 }
2759
2760 #endif
2761 #endif
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