drivers/scsi/blz1230.c

   1 /* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
   2  *
   3  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
   4  *
   5  * This driver is based on the CyberStorm driver, hence the occasional
   6  * reference to CyberStorm.
   7  */
   8
   9 /* TODO:
  10  *
  11  * 1) Figure out how to make a cleaner merge with the sparc driver with regard
  12  *    to the caches and the Sparc MMU mapping.
  13  * 2) Make as few routines required outside the generic driver. A lot of the
  14  *    routines in this file used to be inline!
  15  */
  16
  17 #include <linux/module.h>
  18
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/types.h>
  23 #include <linux/string.h>
  24 #include <linux/malloc.h>
  25 #include <linux/blk.h>
  26 #include <linux/proc_fs.h>
  27 #include <linux/stat.h>
  28
  29 #include "scsi.h"
  30 #include "hosts.h"
  31 #include "NCR53C9x.h"
  32 #include "blz1230.h"
  33
  34 #include <linux/zorro.h>
  35 #include <asm/irq.h>
  36 #include <asm/amigaints.h>
  37 #include <asm/amigahw.h>
  38
  39 #include <asm/pgtable.h>
  40
  41 #define MKIV 1
  42
  43 static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
  44 static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
  45 static void dma_dump_state(struct NCR_ESP *esp);
  46 static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
  47 static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
  48 static void dma_ints_off(struct NCR_ESP *esp);
  49 static void dma_ints_on(struct NCR_ESP *esp);
  50 static int  dma_irq_p(struct NCR_ESP *esp);
  51 static int  dma_ports_p(struct NCR_ESP *esp);
  52 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
  53
  54 volatile unsigned char cmd_buffer[16];
  55                                 /* This is where all commands are put
  56                                  * before they are transfered to the ESP chip
  57                                  * via PIO.
  58                                  */
  59
  60 /***************************************************************** Detection */
  61 int __init blz1230_esp_detect(Scsi_Host_Template *tpnt)
  62 {
  63         struct NCR_ESP *esp;
  64         struct zorro_dev *z = NULL;
  65         unsigned long address;
  66         struct ESP_regs *eregs;
  67
  68 #if MKIV
  69 #define REAL_BLZ1230_ID         ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
  70 #define REAL_BLZ1230_ESP_ADDR   BLZ1230_ESP_ADDR
  71 #define REAL_BLZ1230_DMA_ADDR   BLZ1230_DMA_ADDR
  72 #else
  73 #define REAL_BLZ1230_ID         ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060
  74 #define REAL_BLZ1230_ESP_ADDR   BLZ1230II_ESP_ADDR
  75 #define REAL_BLZ1230_DMA_ADDR   BLZ1230II_DMA_ADDR
  76 #endif
  77
  78         if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
  79             unsigned long board = z->resource.start;
  80             if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
  81                                    sizeof(struct ESP_regs), "NCR53C9x")) {
  82                 /* Do some magic to figure out if the blizzard is
  83                  * equipped with a SCSI controller
  84                  */
  85                 address = ZTWO_VADDR(board);
  86                 eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR);
  87                 esp = esp_allocate(tpnt, (void *)board+REAL_BLZ1230_ESP_ADDR);
  88
  89                 esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
  90                 udelay(5);
  91                 if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7)){
  92                         esp_deallocate(esp);
  93                         scsi_unregister(esp->ehost);
  94                         release_mem_region(board+REAL_BLZ1230_ESP_ADDR,
  95                                            sizeof(struct ESP_regs));
  96                         return 0; /* Bail out if address did not hold data */
  97                 }
  98
  99                 /* Do command transfer with programmed I/O */
 100                 esp->do_pio_cmds = 1;
 101
 102                 /* Required functions */
 103                 esp->dma_bytes_sent = &dma_bytes_sent;
 104                 esp->dma_can_transfer = &dma_can_transfer;
 105                 esp->dma_dump_state = &dma_dump_state;
 106                 esp->dma_init_read = &dma_init_read;
 107                 esp->dma_init_write = &dma_init_write;
 108                 esp->dma_ints_off = &dma_ints_off;
 109                 esp->dma_ints_on = &dma_ints_on;
 110                 esp->dma_irq_p = &dma_irq_p;
 111                 esp->dma_ports_p = &dma_ports_p;
 112                 esp->dma_setup = &dma_setup;
 113
 114                 /* Optional functions */
 115                 esp->dma_barrier = 0;
 116                 esp->dma_drain = 0;
 117                 esp->dma_invalidate = 0;
 118                 esp->dma_irq_entry = 0;
 119                 esp->dma_irq_exit = 0;
 120                 esp->dma_led_on = 0;
 121                 esp->dma_led_off = 0;
 122                 esp->dma_poll = 0;
 123                 esp->dma_reset = 0;
 124
 125                 /* SCSI chip speed */
 126                 esp->cfreq = 40000000;
 127
 128                 /* The DMA registers on the Blizzard are mapped
 129                  * relative to the device (i.e. in the same Zorro
 130                  * I/O block).
 131                  */
 132                 esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR);
 133
 134                 /* ESP register base */
 135                 esp->eregs = eregs;
 136
 137                 /* Set the command buffer */
 138                 esp->esp_command = (volatile unsigned char*) cmd_buffer;
 139                 esp->esp_command_dvma = virt_to_bus(cmd_buffer);
 140
 141                 esp->irq = IRQ_AMIGA_PORTS;
 142                 esp->slot = board+REAL_BLZ1230_ESP_ADDR;
 143                 request_irq(IRQ_AMIGA_PORTS, esp_intr, SA_SHIRQ,
 144                             "Blizzard 1230 SCSI IV", esp_intr);
 145
 146                 /* Figure out our scsi ID on the bus */
 147                 esp->scsi_id = 7;
 148
 149                 /* We don't have a differential SCSI-bus. */
 150                 esp->diff = 0;
 151
 152                 esp_initialize(esp);
 153
 154                 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
 155                 esps_running = esps_in_use;
 156                 return esps_in_use;
 157             }
 158         }
 159         return 0;
 160 }
 161
 162 /************************************************************* DMA Functions */
 163 static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
 164 {
 165         /* Since the Blizzard DMA is fully dedicated to the ESP chip,
 166          * the number of bytes sent (to the ESP chip) equals the number
 167          * of bytes in the FIFO - there is no buffering in the DMA controller.
 168          * XXXX Do I read this right? It is from host to ESP, right?
 169          */
 170         return fifo_count;
 171 }
 172
 173 static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
 174 {
 175         /* I don't think there's any limit on the Blizzard DMA. So we use what
 176          * the ESP chip can handle (24 bit).
 177          */
 178         unsigned long sz = sp->SCp.this_residual;
 179         if(sz > 0x1000000)
 180                 sz = 0x1000000;
 181         return sz;
 182 }
 183
 184 static void dma_dump_state(struct NCR_ESP *esp)
 185 {
 186         ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
 187                 custom.intreqr, custom.intenar));
 188 }
 189
 190 void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
 191 {
 192 #if MKIV
 193         struct blz1230_dma_registers *dregs =
 194                 (struct blz1230_dma_registers *) (esp->dregs);
 195 #else
 196         struct blz1230II_dma_registers *dregs =
 197                 (struct blz1230II_dma_registers *) (esp->dregs);
 198 #endif
 199
 200         cache_clear(addr, length);
 201
 202         addr >>= 1;
 203         addr &= ~(BLZ1230_DMA_WRITE);
 204
 205         /* First set latch */
 206         dregs->dma_latch = (addr >> 24) & 0xff;
 207
 208         /* Then pump the address to the DMA address register */
 209 #if MKIV
 210         dregs->dma_addr = (addr >> 24) & 0xff;
 211 #endif
 212         dregs->dma_addr = (addr >> 16) & 0xff;
 213         dregs->dma_addr = (addr >>  8) & 0xff;
 214         dregs->dma_addr = (addr      ) & 0xff;
 215 }
 216
 217 void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
 218 {
 219 #if MKIV
 220         struct blz1230_dma_registers *dregs =
 221                 (struct blz1230_dma_registers *) (esp->dregs);
 222 #else
 223         struct blz1230II_dma_registers *dregs =
 224                 (struct blz1230II_dma_registers *) (esp->dregs);
 225 #endif
 226
 227         cache_push(addr, length);
 228
 229         addr >>= 1;
 230         addr |= BLZ1230_DMA_WRITE;
 231
 232         /* First set latch */
 233         dregs->dma_latch = (addr >> 24) & 0xff;
 234
 235         /* Then pump the address to the DMA address register */
 236 #if MKIV
 237         dregs->dma_addr = (addr >> 24) & 0xff;
 238 #endif
 239         dregs->dma_addr = (addr >> 16) & 0xff;
 240         dregs->dma_addr = (addr >>  8) & 0xff;
 241         dregs->dma_addr = (addr      ) & 0xff;
 242 }
 243
 244 static void dma_ints_off(struct NCR_ESP *esp)
 245 {
 246         disable_irq(esp->irq);
 247 }
 248
 249 static void dma_ints_on(struct NCR_ESP *esp)
 250 {
 251         enable_irq(esp->irq);
 252 }
 253
 254 static int dma_irq_p(struct NCR_ESP *esp)
 255 {
 256         return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
 257 }
 258
 259 static int dma_ports_p(struct NCR_ESP *esp)
 260 {
 261         return ((custom.intenar) & IF_PORTS);
 262 }
 263
 264 static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
 265 {
 266         /* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
 267          * so when (write) is true, it actually means READ!
 268          */
 269         if(write){
 270                 dma_init_read(esp, addr, count);
 271         } else {
 272                 dma_init_write(esp, addr, count);
 273         }
 274 }
 275
 276 #define HOSTS_C
 277
 278 #include "blz1230.h"
 279
 280 static Scsi_Host_Template driver_template = SCSI_BLZ1230;
 281
 282 #include "scsi_module.c"
 283
 284 int blz1230_esp_release(struct Scsi_Host *instance)
 285 {
 286 #ifdef MODULE
 287         unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
 288         esp_deallocate((struct NCR_ESP *)instance->hostdata);
 289         esp_release();
 290         release_mem_region(address, sizeof(struct ESP_regs));
 291         free_irq(IRQ_AMIGA_PORTS, esp_intr);
 292 #endif
 293         return 1;
 294 }