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Import 2.3.36
[davej-history.git] / drivers / char / agp / agpgart_be.c
blob27413489ade9db28441bf49ab2ac7c21eb515472
1 /*
2 * AGPGART module version 0.99
3 * Copyright (C) 1999 Jeff Hartmann
4 * Copyright (C) 1999 Precision Insight, Inc.
5 * Copyright (C) 1999 Xi Graphics, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
23 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26 #include <linux/config.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/kernel.h>
31 #include <linux/sched.h>
32 #include <linux/mm.h>
33 #include <linux/string.h>
34 #include <linux/errno.h>
35 #include <linux/malloc.h>
36 #include <linux/vmalloc.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/pagemap.h>
40 #include <linux/miscdevice.h>
41 #include <asm/system.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44 #include <asm/page.h>
45
46 #include <linux/agp_backend.h>
47 #include "agp.h"
48
49 MODULE_AUTHOR("Jeff Hartmann <jhartmann@precisioninsight.com>");
50 MODULE_PARM(agp_try_unsupported, "1i");
51 EXPORT_SYMBOL(agp_free_memory);
52 EXPORT_SYMBOL(agp_allocate_memory);
53 EXPORT_SYMBOL(agp_copy_info);
54 EXPORT_SYMBOL(agp_bind_memory);
55 EXPORT_SYMBOL(agp_unbind_memory);
56 EXPORT_SYMBOL(agp_enable);
57 EXPORT_SYMBOL(agp_backend_acquire);
58 EXPORT_SYMBOL(agp_backend_release);
59
60 static void flush_cache(void);
61
62 static struct agp_bridge_data agp_bridge;
63 static int agp_try_unsupported __initdata = 0;
64
65
66 static inline void flush_cache(void)
67 {
68 #if defined(__i386__)
69 asm volatile ("wbinvd":::"memory");
70 #elif defined(__alpha__)
71 /* ??? I wonder if we'll really need to flush caches, or if the
72 core logic can manage to keep the system coherent. The ARM
73 speaks only of using `cflush' to get things in memory in
74 preparation for power failure.
75
76 If we do need to call `cflush', we'll need a target page,
77 as we can only flush one page at a time. */
78 mb();
79 #else
80 #error "Please define flush_cache."
81 #endif
82 }
83
84 #ifdef __SMP__
85 static atomic_t cpus_waiting;
86
87 static void ipi_handler(void *null)
88 {
89 flush_cache();
90 atomic_dec(&cpus_waiting);
91 while (atomic_read(&cpus_waiting) > 0)
92 barrier();
93 }
94
95 static void smp_flush_cache(void)
96 {
97 atomic_set(&cpus_waiting, smp_num_cpus - 1);
98 if (smp_call_function(ipi_handler, NULL, 1, 0) != 0)
99 panic("agpgart: timed out waiting for the other CPUs!\n");
100 flush_cache();
101 while (atomic_read(&cpus_waiting) > 0)
102 barrier();
103 }
104 #define global_cache_flush smp_flush_cache
105 #else /* __SMP__ */
106 #define global_cache_flush flush_cache
107 #endif /* __SMP__ */
108
109 int agp_backend_acquire(void)
110 {
111 atomic_inc(&agp_bridge.agp_in_use);
112
113 if (atomic_read(&agp_bridge.agp_in_use) != 1) {
114 atomic_dec(&agp_bridge.agp_in_use);
115 return -EBUSY;
116 }
117 MOD_INC_USE_COUNT;
118 return 0;
119 }
120
121 void agp_backend_release(void)
122 {
123 atomic_dec(&agp_bridge.agp_in_use);
124 MOD_DEC_USE_COUNT;
125 }
126
127 /*
128 * Basic Page Allocation Routines -
129 * These routines handle page allocation
130 * and by default they reserve the allocated
131 * memory. They also handle incrementing the
132 * current_memory_agp value, Which is checked
133 * against a maximum value.
134 */
135
136 static unsigned long agp_alloc_page(void)
137 {
138 void *pt;
139
140 pt = (void *) __get_free_page(GFP_KERNEL);
141 if (pt == NULL) {
142 return 0;
143 }
144 atomic_inc(&mem_map[MAP_NR(pt)].count);
145 set_bit(PG_locked, &mem_map[MAP_NR(pt)].flags);
146 atomic_inc(&agp_bridge.current_memory_agp);
147 return (unsigned long) pt;
148 }
149
150 static void agp_destroy_page(unsigned long page)
151 {
152 void *pt = (void *) page;
153
154 if (pt == NULL) {
155 return;
156 }
157 atomic_dec(&mem_map[MAP_NR(pt)].count);
158 clear_bit(PG_locked, &mem_map[MAP_NR(pt)].flags);
159 wake_up(&mem_map[MAP_NR(pt)].wait);
160 free_page((unsigned long) pt);
161 atomic_dec(&agp_bridge.current_memory_agp);
162 }
163
164 /* End Basic Page Allocation Routines */
165
166 /*
167 * Generic routines for handling agp_memory structures -
168 * They use the basic page allocation routines to do the
169 * brunt of the work.
170 */
171
172
173 static void agp_free_key(int key)
174 {
175
176 if (key < 0) {
177 return;
178 }
179 if (key < MAXKEY) {
180 clear_bit(key, agp_bridge.key_list);
181 }
182 }
183
184 static int agp_get_key(void)
185 {
186 int bit;
187
188 bit = find_first_zero_bit(agp_bridge.key_list, MAXKEY);
189 if (bit < MAXKEY) {
190 set_bit(bit, agp_bridge.key_list);
191 return bit;
192 }
193 return -1;
194 }
195
196 static agp_memory *agp_create_memory(int scratch_pages)
197 {
198 agp_memory *new;
199
200 new = kmalloc(sizeof(agp_memory), GFP_KERNEL);
201
202 if (new == NULL) {
203 return NULL;
204 }
205 memset(new, 0, sizeof(agp_memory));
206 new->key = agp_get_key();
207
208 if (new->key < 0) {
209 kfree(new);
210 return NULL;
211 }
212 new->memory = vmalloc(PAGE_SIZE * scratch_pages);
213
214 if (new->memory == NULL) {
215 agp_free_key(new->key);
216 kfree(new);
217 return NULL;
218 }
219 new->num_scratch_pages = scratch_pages;
220 return new;
221 }
222
223 void agp_free_memory(agp_memory * curr)
224 {
225 int i;
226
227 if (curr == NULL) {
228 return;
229 }
230 if (curr->is_bound == TRUE) {
231 agp_unbind_memory(curr);
232 }
233 if (curr->type != 0) {
234 agp_bridge.free_by_type(curr);
235 MOD_DEC_USE_COUNT;
236 return;
237 }
238 if (curr->page_count != 0) {
239 for (i = 0; i < curr->page_count; i++) {
240 curr->memory[i] &= ~(0x00000fff);
241 agp_destroy_page((unsigned long)
242 phys_to_virt(curr->memory[i]));
243 }
244 }
245 agp_free_key(curr->key);
246 vfree(curr->memory);
247 kfree(curr);
248 MOD_DEC_USE_COUNT;
249 }
250
251 #define ENTRIES_PER_PAGE (PAGE_SIZE / sizeof(unsigned long))
252
253 agp_memory *agp_allocate_memory(size_t page_count, u32 type)
254 {
255 int scratch_pages;
256 agp_memory *new;
257 int i;
258
259 if ((atomic_read(&agp_bridge.current_memory_agp) + page_count) >
260 agp_bridge.max_memory_agp) {
261 return NULL;
262 }
263 if (type != 0) {
264 new = agp_bridge.alloc_by_type(page_count, type);
265 return new;
266 }
267 scratch_pages = (page_count + ENTRIES_PER_PAGE - 1) / ENTRIES_PER_PAGE;
268
269 new = agp_create_memory(scratch_pages);
270
271 if (new == NULL) {
272 return NULL;
273 }
274 for (i = 0; i < page_count; i++) {
275 new->memory[i] = agp_alloc_page();
276
277 if (new->memory[i] == 0) {
278 /* Free this structure */
279 agp_free_memory(new);
280 return NULL;
281 }
282 new->memory[i] =
283 agp_bridge.mask_memory(
284 virt_to_phys((void *) new->memory[i]),
285 type);
286 new->page_count++;
287 }
288
289 MOD_INC_USE_COUNT;
290 return new;
291 }
292
293 /* End - Generic routines for handling agp_memory structures */
294
295 static int agp_return_size(void)
296 {
297 int current_size;
298 void *temp;
299
300 temp = agp_bridge.current_size;
301
302 switch (agp_bridge.size_type) {
303 case U8_APER_SIZE:
304 current_size = A_SIZE_8(temp)->size;
305 break;
306 case U16_APER_SIZE:
307 current_size = A_SIZE_16(temp)->size;
308 break;
309 case U32_APER_SIZE:
310 current_size = A_SIZE_32(temp)->size;
311 break;
312 case FIXED_APER_SIZE:
313 current_size = A_SIZE_FIX(temp)->size;
314 break;
315 default:
316 current_size = 0;
317 break;
318 }
319
320 return current_size;
321 }
322
323 /* Routine to copy over information structure */
324
325 void agp_copy_info(agp_kern_info * info)
326 {
327 memset(info, 0, sizeof(agp_kern_info));
328 info->version.major = agp_bridge.version->major;
329 info->version.minor = agp_bridge.version->minor;
330 info->device = agp_bridge.dev;
331 info->chipset = agp_bridge.type;
332 info->mode = agp_bridge.mode;
333 info->aper_base = agp_bridge.gart_bus_addr;
334 info->aper_size = agp_return_size();
335 info->max_memory = agp_bridge.max_memory_agp;
336 info->current_memory = atomic_read(&agp_bridge.current_memory_agp);
337 }
338
339 /* End - Routine to copy over information structure */
340
341 /*
342 * Routines for handling swapping of agp_memory into the GATT -
343 * These routines take agp_memory and insert them into the GATT.
344 * They call device specific routines to actually write to the GATT.
345 */
346
347 int agp_bind_memory(agp_memory * curr, off_t pg_start)
348 {
349 int ret_val;
350
351 if ((curr == NULL) || (curr->is_bound == TRUE)) {
352 return -EINVAL;
353 }
354 if (curr->is_flushed == FALSE) {
355 CACHE_FLUSH();
356 curr->is_flushed = TRUE;
357 }
358 ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type);
359
360 if (ret_val != 0) {
361 return ret_val;
362 }
363 curr->is_bound = TRUE;
364 curr->pg_start = pg_start;
365 return 0;
366 }
367
368 int agp_unbind_memory(agp_memory * curr)
369 {
370 int ret_val;
371
372 if (curr == NULL) {
373 return -EINVAL;
374 }
375 if (curr->is_bound != TRUE) {
376 return -EINVAL;
377 }
378 ret_val = agp_bridge.remove_memory(curr, curr->pg_start, curr->type);
379
380 if (ret_val != 0) {
381 return ret_val;
382 }
383 curr->is_bound = FALSE;
384 curr->pg_start = 0;
385 return 0;
386 }
387
388 /* End - Routines for handling swapping of agp_memory into the GATT */
389
390 /*
391 * Driver routines - start
392 * Currently this module supports the
393 * i810, 440lx, 440bx, 440gx, via vp3, via mvp3,
394 * amd irongate, ALi M1541 and generic support for the
395 * SiS chipsets.
396 */
397
398 /* Generic Agp routines - Start */
399
400 static void agp_generic_agp_enable(u32 mode)
401 {
402 struct pci_dev *device = NULL;
403 u32 command, scratch, cap_id;
404 u8 cap_ptr;
405
406 pci_read_config_dword(agp_bridge.dev,
407 agp_bridge.capndx + 4,
408 &command);
409
410 /*
411 * PASS1: go throu all devices that claim to be
412 * AGP devices and collect their data.
413 */
414
415 while ((device = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8,
416 device)) != NULL) {
417 pci_read_config_dword(device, 0x04, &scratch);
418
419 if (!(scratch & 0x00100000))
420 continue;
421
422 pci_read_config_byte(device, 0x34, &cap_ptr);
423
424 if (cap_ptr != 0x00) {
425 do {
426 pci_read_config_dword(device,
427 cap_ptr, &cap_id);
428
429 if ((cap_id & 0xff) != 0x02)
430 cap_ptr = (cap_id >> 8) & 0xff;
431 }
432 while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
433 }
434 if (cap_ptr != 0x00) {
435 /*
436 * Ok, here we have a AGP device. Disable impossible
437 * settings, and adjust the readqueue to the minimum.
438 */
439
440 pci_read_config_dword(device, cap_ptr + 4, &scratch);
441
442 /* adjust RQ depth */
443 command =
444 ((command & ~0xff000000) |
445 min((mode & 0xff000000),
446 min((command & 0xff000000),
447 (scratch & 0xff000000))));
448
449 /* disable SBA if it's not supported */
450 if (!((command & 0x00000200) &&
451 (scratch & 0x00000200) &&
452 (mode & 0x00000200)))
453 command &= ~0x00000200;
454
455 /* disable FW if it's not supported */
456 if (!((command & 0x00000010) &&
457 (scratch & 0x00000010) &&
458 (mode & 0x00000010)))
459 command &= ~0x00000010;
460
461 if (!((command & 4) &&
462 (scratch & 4) &&
463 (mode & 4)))
464 command &= ~0x00000004;
465
466 if (!((command & 2) &&
467 (scratch & 2) &&
468 (mode & 2)))
469 command &= ~0x00000002;
470
471 if (!((command & 1) &&
472 (scratch & 1) &&
473 (mode & 1)))
474 command &= ~0x00000001;
475 }
476 }
477 /*
478 * PASS2: Figure out the 4X/2X/1X setting and enable the
479 * target (our motherboard chipset).
480 */
481
482 if (command & 4) {
483 command &= ~3; /* 4X */
484 }
485 if (command & 2) {
486 command &= ~5; /* 2X */
487 }
488 if (command & 1) {
489 command &= ~6; /* 1X */
490 }
491 command |= 0x00000100;
492
493 pci_write_config_dword(agp_bridge.dev,
494 agp_bridge.capndx + 8,
495 command);
496
497 /*
498 * PASS3: Go throu all AGP devices and update the
499 * command registers.
500 */
501
502 while ((device = pci_find_class(PCI_CLASS_DISPLAY_VGA << 8,
503 device)) != NULL) {
504 pci_read_config_dword(device, 0x04, &scratch);
505
506 if (!(scratch & 0x00100000))
507 continue;
508
509 pci_read_config_byte(device, 0x34, &cap_ptr);
510
511 if (cap_ptr != 0x00) {
512 do {
513 pci_read_config_dword(device,
514 cap_ptr, &cap_id);
515
516 if ((cap_id & 0xff) != 0x02)
517 cap_ptr = (cap_id >> 8) & 0xff;
518 }
519 while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
520 }
521 if (cap_ptr != 0x00)
522 pci_write_config_dword(device, cap_ptr + 8, command);
523 }
524 }
525
526 static int agp_generic_create_gatt_table(void)
527 {
528 char *table;
529 char *table_end;
530 int size;
531 int page_order;
532 int num_entries;
533 int i;
534 void *temp;
535
536 table = NULL;
537 i = agp_bridge.aperture_size_idx;
538 temp = agp_bridge.current_size;
539 size = page_order = num_entries = 0;
540
541 if (agp_bridge.size_type != FIXED_APER_SIZE) {
542 do {
543 switch (agp_bridge.size_type) {
544 case U8_APER_SIZE:
545 size = A_SIZE_8(temp)->size;
546 page_order =
547 A_SIZE_8(temp)->page_order;
548 num_entries =
549 A_SIZE_8(temp)->num_entries;
550 break;
551 case U16_APER_SIZE:
552 size = A_SIZE_16(temp)->size;
553 page_order = A_SIZE_16(temp)->page_order;
554 num_entries = A_SIZE_16(temp)->num_entries;
555 break;
556 case U32_APER_SIZE:
557 size = A_SIZE_32(temp)->size;
558 page_order = A_SIZE_32(temp)->page_order;
559 num_entries = A_SIZE_32(temp)->num_entries;
560 break;
561 /* This case will never really happen. */
562 case FIXED_APER_SIZE:
563 default:
564 size = page_order = num_entries = 0;
565 break;
566 }
567
568 table = (char *) __get_free_pages(GFP_KERNEL,
569 page_order);
570
571 if (table == NULL) {
572 i++;
573 switch (agp_bridge.size_type) {
574 case U8_APER_SIZE:
575 agp_bridge.current_size = A_IDX8();
576 break;
577 case U16_APER_SIZE:
578 agp_bridge.current_size = A_IDX16();
579 break;
580 case U32_APER_SIZE:
581 agp_bridge.current_size = A_IDX32();
582 break;
583 /* This case will never really
584 * happen.
585 */
586 case FIXED_APER_SIZE:
587 default:
588 agp_bridge.current_size =
589 agp_bridge.current_size;
590 break;
591 }
592 } else {
593 agp_bridge.aperture_size_idx = i;
594 }
595 } while ((table == NULL) &&
596 (i < agp_bridge.num_aperture_sizes));
597 } else {
598 size = ((aper_size_info_fixed *) temp)->size;
599 page_order = ((aper_size_info_fixed *) temp)->page_order;
600 num_entries = ((aper_size_info_fixed *) temp)->num_entries;
601 table = (char *) __get_free_pages(GFP_KERNEL, page_order);
602 }
603
604 if (table == NULL) {
605 return -ENOMEM;
606 }
607 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
608
609 for (i = MAP_NR(table); i < MAP_NR(table_end); i++) {
610 set_bit(PG_reserved, &mem_map[i].flags);
611 }
612
613 agp_bridge.gatt_table_real = (unsigned long *) table;
614 CACHE_FLUSH();
615 agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
616 (PAGE_SIZE * (1 << page_order)));
617 CACHE_FLUSH();
618
619 if (agp_bridge.gatt_table == NULL) {
620 for (i = MAP_NR(table); i < MAP_NR(table_end); i++) {
621 clear_bit(PG_reserved, &mem_map[i].flags);
622 }
623
624 free_pages((unsigned long) table, page_order);
625
626 return -ENOMEM;
627 }
628 agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real);
629
630 for (i = 0; i < num_entries; i++) {
631 agp_bridge.gatt_table[i] =
632 (unsigned long) agp_bridge.scratch_page;
633 }
634
635 return 0;
636 }
637
638 static int agp_generic_free_gatt_table(void)
639 {
640 int i;
641 int page_order;
642 char *table, *table_end;
643 void *temp;
644
645 temp = agp_bridge.current_size;
646
647 switch (agp_bridge.size_type) {
648 case U8_APER_SIZE:
649 page_order = A_SIZE_8(temp)->page_order;
650 break;
651 case U16_APER_SIZE:
652 page_order = A_SIZE_16(temp)->page_order;
653 break;
654 case U32_APER_SIZE:
655 page_order = A_SIZE_32(temp)->page_order;
656 break;
657 case FIXED_APER_SIZE:
658 page_order = A_SIZE_FIX(temp)->page_order;
659 break;
660 default:
661 page_order = 0;
662 break;
663 }
664
665 /* Do not worry about freeing memory, because if this is
666 * called, then all agp memory is deallocated and removed
667 * from the table.
668 */
669
670 iounmap(agp_bridge.gatt_table);
671 table = (char *) agp_bridge.gatt_table_real;
672 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
673
674 for (i = MAP_NR(table); i < MAP_NR(table_end); i++) {
675 clear_bit(PG_reserved, &mem_map[i].flags);
676 }
677
678 free_pages((unsigned long) agp_bridge.gatt_table_real, page_order);
679 return 0;
680 }
681
682 static int agp_generic_insert_memory(agp_memory * mem,
683 off_t pg_start, int type)
684 {
685 int i, j, num_entries;
686 void *temp;
687
688 temp = agp_bridge.current_size;
689
690 switch (agp_bridge.size_type) {
691 case U8_APER_SIZE:
692 num_entries = A_SIZE_8(temp)->num_entries;
693 break;
694 case U16_APER_SIZE:
695 num_entries = A_SIZE_16(temp)->num_entries;
696 break;
697 case U32_APER_SIZE:
698 num_entries = A_SIZE_32(temp)->num_entries;
699 break;
700 case FIXED_APER_SIZE:
701 num_entries = A_SIZE_FIX(temp)->num_entries;
702 break;
703 default:
704 num_entries = 0;
705 break;
706 }
707
708 if (type != 0 || mem->type != 0) {
709 /* The generic routines know nothing of memory types */
710 return -EINVAL;
711 }
712 if ((pg_start + mem->page_count) > num_entries) {
713 return -EINVAL;
714 }
715 j = pg_start;
716
717 while (j < (pg_start + mem->page_count)) {
718 if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
719 return -EBUSY;
720 }
721 j++;
722 }
723
724 if (mem->is_flushed == FALSE) {
725 CACHE_FLUSH();
726 mem->is_flushed = TRUE;
727 }
728 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
729 agp_bridge.gatt_table[j] = mem->memory[i];
730 }
731
732 agp_bridge.tlb_flush(mem);
733 return 0;
734 }
735
736 static int agp_generic_remove_memory(agp_memory * mem, off_t pg_start,
737 int type)
738 {
739 int i;
740
741 if (type != 0 || mem->type != 0) {
742 /* The generic routines know nothing of memory types */
743 return -EINVAL;
744 }
745 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
746 agp_bridge.gatt_table[i] =
747 (unsigned long) agp_bridge.scratch_page;
748 }
749
750 agp_bridge.tlb_flush(mem);
751 return 0;
752 }
753
754 static agp_memory *agp_generic_alloc_by_type(size_t page_count, int type)
755 {
756 return NULL;
757 }
758
759 static void agp_generic_free_by_type(agp_memory * curr)
760 {
761 if (curr->memory != NULL) {
762 vfree(curr->memory);
763 }
764 agp_free_key(curr->key);
765 kfree(curr);
766 }
767
768 void agp_enable(u32 mode)
769 {
770 agp_bridge.agp_enable(mode);
771 }
772
773 /* End - Generic Agp routines */
774
775 #ifdef CONFIG_AGP_I810
776 static aper_size_info_fixed intel_i810_sizes[] =
777 {
778 {64, 16384, 4},
779 /* The 32M mode still requires a 64k gatt */
780 {32, 8192, 4}
781 };
782
783 #define AGP_DCACHE_MEMORY 1
784
785 static gatt_mask intel_i810_masks[] =
786 {
787 {I810_PTE_VALID, 0},
788 {(I810_PTE_VALID | I810_PTE_LOCAL), AGP_DCACHE_MEMORY}
789 };
790
791 static struct _intel_i810_private {
792 struct pci_dev *i810_dev; /* device one */
793 volatile u8 *registers;
794 int num_dcache_entries;
795 } intel_i810_private;
796
797 static int intel_i810_fetch_size(void)
798 {
799 u32 smram_miscc;
800 aper_size_info_fixed *values;
801
802 pci_read_config_dword(agp_bridge.dev, I810_SMRAM_MISCC, &smram_miscc);
803 values = A_SIZE_FIX(agp_bridge.aperture_sizes);
804
805 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
806 printk("agpgart: i810 is disabled\n");
807 return 0;
808 }
809 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
810 agp_bridge.previous_size =
811 agp_bridge.current_size = (void *) (values + 1);
812 agp_bridge.aperture_size_idx = 1;
813 return values[1].size;
814 } else {
815 agp_bridge.previous_size =
816 agp_bridge.current_size = (void *) (values);
817 agp_bridge.aperture_size_idx = 0;
818 return values[0].size;
819 }
820
821 return 0;
822 }
823
824 static int intel_i810_configure(void)
825 {
826 aper_size_info_fixed *current_size;
827 u32 temp;
828 int i;
829
830 current_size = A_SIZE_FIX(agp_bridge.current_size);
831
832 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
833 temp &= 0xfff80000;
834
835 intel_i810_private.registers =
836 (volatile u8 *) ioremap(temp, 128 * 4096);
837
838 if ((INREG32(intel_i810_private.registers, I810_DRAM_CTL)
839 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
840 /* This will need to be dynamically assigned */
841 printk(KERN_INFO
842 "agpgart: detected 4MB dedicated video ram.\n");
843 intel_i810_private.num_dcache_entries = 1024;
844 }
845 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
846 agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
847 OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL,
848 agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
849 CACHE_FLUSH();
850
851 if (agp_bridge.needs_scratch_page == TRUE) {
852 for (i = 0; i < current_size->num_entries; i++) {
853 OUTREG32(intel_i810_private.registers,
854 I810_PTE_BASE + (i * 4),
855 agp_bridge.scratch_page);
856 }
857 }
858 return 0;
859 }
860
861 static void intel_i810_cleanup(void)
862 {
863 OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL, 0);
864 iounmap((void *) intel_i810_private.registers);
865 }
866
867 static void intel_i810_tlbflush(agp_memory * mem)
868 {
869 return;
870 }
871
872 static void intel_i810_agp_enable(u32 mode)
873 {
874 return;
875 }
876
877 static int intel_i810_insert_entries(agp_memory * mem, off_t pg_start,
878 int type)
879 {
880 int i, j, num_entries;
881 void *temp;
882
883 temp = agp_bridge.current_size;
884 num_entries = A_SIZE_FIX(temp)->num_entries;
885
886 if ((pg_start + mem->page_count) > num_entries) {
887 return -EINVAL;
888 }
889 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
890 if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
891 return -EBUSY;
892 }
893 }
894
895 if (type != 0 || mem->type != 0) {
896 if ((type == AGP_DCACHE_MEMORY) &&
897 (mem->type == AGP_DCACHE_MEMORY)) {
898 /* special insert */
899
900 for (i = pg_start;
901 i < (pg_start + mem->page_count); i++) {
902 OUTREG32(intel_i810_private.registers,
903 I810_PTE_BASE + (i * 4),
904 (i * 4096) | I810_PTE_LOCAL |
905 I810_PTE_VALID);
906 }
907
908 agp_bridge.tlb_flush(mem);
909 return 0;
910 }
911 return -EINVAL;
912 }
913 if (mem->is_flushed == FALSE) {
914 CACHE_FLUSH();
915 mem->is_flushed = TRUE;
916 }
917 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
918 OUTREG32(intel_i810_private.registers,
919 I810_PTE_BASE + (j * 4), mem->memory[i]);
920 }
921
922 agp_bridge.tlb_flush(mem);
923 return 0;
924 }
925
926 static int intel_i810_remove_entries(agp_memory * mem, off_t pg_start,
927 int type)
928 {
929 int i;
930
931 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
932 OUTREG32(intel_i810_private.registers,
933 I810_PTE_BASE + (i * 4),
934 agp_bridge.scratch_page);
935 }
936
937 agp_bridge.tlb_flush(mem);
938 return 0;
939 }
940
941 static agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
942 {
943 agp_memory *new;
944
945 if (type == AGP_DCACHE_MEMORY) {
946 if (pg_count != intel_i810_private.num_dcache_entries) {
947 return NULL;
948 }
949 new = agp_create_memory(1);
950
951 if (new == NULL) {
952 return NULL;
953 }
954 new->type = AGP_DCACHE_MEMORY;
955 new->page_count = pg_count;
956 new->num_scratch_pages = 0;
957 vfree(new->memory);
958 return new;
959 }
960 return NULL;
961 }
962
963 static void intel_i810_free_by_type(agp_memory * curr)
964 {
965 agp_free_key(curr->key);
966 kfree(curr);
967 }
968
969 static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
970 {
971 /* Type checking must be done elsewhere */
972 return addr | agp_bridge.masks[type].mask;
973 }
974
975 static void intel_i810_setup(struct pci_dev *i810_dev)
976 {
977 intel_i810_private.i810_dev = i810_dev;
978
979 agp_bridge.masks = intel_i810_masks;
980 agp_bridge.num_of_masks = 2;
981 agp_bridge.aperture_sizes = (void *) intel_i810_sizes;
982 agp_bridge.size_type = FIXED_APER_SIZE;
983 agp_bridge.num_aperture_sizes = 2;
984 agp_bridge.dev_private_data = (void *) &intel_i810_private;
985 agp_bridge.needs_scratch_page = TRUE;
986 agp_bridge.configure = intel_i810_configure;
987 agp_bridge.fetch_size = intel_i810_fetch_size;
988 agp_bridge.cleanup = intel_i810_cleanup;
989 agp_bridge.tlb_flush = intel_i810_tlbflush;
990 agp_bridge.mask_memory = intel_i810_mask_memory;
991 agp_bridge.agp_enable = intel_i810_agp_enable;
992 agp_bridge.cache_flush = global_cache_flush;
993 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
994 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
995 agp_bridge.insert_memory = intel_i810_insert_entries;
996 agp_bridge.remove_memory = intel_i810_remove_entries;
997 agp_bridge.alloc_by_type = intel_i810_alloc_by_type;
998 agp_bridge.free_by_type = intel_i810_free_by_type;
999 }
1000
1001 #endif
1002
1003 #ifdef CONFIG_AGP_INTEL
1004
1005 static int intel_fetch_size(void)
1006 {
1007 int i;
1008 u16 temp;
1009 aper_size_info_16 *values;
1010
1011 pci_read_config_word(agp_bridge.dev, INTEL_APSIZE, &temp);
1012 values = A_SIZE_16(agp_bridge.aperture_sizes);
1013
1014 for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
1015 if (temp == values[i].size_value) {
1016 agp_bridge.previous_size =
1017 agp_bridge.current_size = (void *) (values + i);
1018 agp_bridge.aperture_size_idx = i;
1019 return values[i].size;
1020 }
1021 }
1022
1023 return 0;
1024 }
1025
1026 static void intel_tlbflush(agp_memory * mem)
1027 {
1028 pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2200);
1029 pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
1030 }
1031
1032 static void intel_cleanup(void)
1033 {
1034 u16 temp;
1035 aper_size_info_16 *previous_size;
1036
1037 previous_size = A_SIZE_16(agp_bridge.previous_size);
1038 pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
1039 pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
1040 pci_write_config_word(agp_bridge.dev, INTEL_APSIZE,
1041 previous_size->size_value);
1042 }
1043
1044 static int intel_configure(void)
1045 {
1046 u32 temp;
1047 u16 temp2;
1048 aper_size_info_16 *current_size;
1049
1050 current_size = A_SIZE_16(agp_bridge.current_size);
1051
1052 /* aperture size */
1053 pci_write_config_word(agp_bridge.dev, INTEL_APSIZE,
1054 current_size->size_value);
1055
1056 /* address to map to */
1057 pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
1058 agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1059
1060 /* attbase - aperture base */
1061 pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE,
1062 agp_bridge.gatt_bus_addr);
1063
1064 /* agpctrl */
1065 pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
1066
1067 /* paccfg/nbxcfg */
1068 pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
1069 pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG,
1070 (temp2 & ~(1 << 10)) | (1 << 9));
1071 /* clear any possible error conditions */
1072 pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7);
1073 return 0;
1074 }
1075
1076 static unsigned long intel_mask_memory(unsigned long addr, int type)
1077 {
1078 /* Memory type is ignored */
1079
1080 return addr | agp_bridge.masks[0].mask;
1081 }
1082
1083
1084 /* Setup function */
1085 static gatt_mask intel_generic_masks[] =
1086 {
1087 {0x00000017, 0}
1088 };
1089
1090 static aper_size_info_16 intel_generic_sizes[7] =
1091 {
1092 {256, 65536, 6, 0},
1093 {128, 32768, 5, 32},
1094 {64, 16384, 4, 48},
1095 {32, 8192, 3, 56},
1096 {16, 4096, 2, 60},
1097 {8, 2048, 1, 62},
1098 {4, 1024, 0, 63}
1099 };
1100
1101 static void intel_generic_setup(void)
1102 {
1103 agp_bridge.masks = intel_generic_masks;
1104 agp_bridge.num_of_masks = 1;
1105 agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
1106 agp_bridge.size_type = U16_APER_SIZE;
1107 agp_bridge.num_aperture_sizes = 7;
1108 agp_bridge.dev_private_data = NULL;
1109 agp_bridge.needs_scratch_page = FALSE;
1110 agp_bridge.configure = intel_configure;
1111 agp_bridge.fetch_size = intel_fetch_size;
1112 agp_bridge.cleanup = intel_cleanup;
1113 agp_bridge.tlb_flush = intel_tlbflush;
1114 agp_bridge.mask_memory = intel_mask_memory;
1115 agp_bridge.agp_enable = agp_generic_agp_enable;
1116 agp_bridge.cache_flush = global_cache_flush;
1117 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
1118 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
1119 agp_bridge.insert_memory = agp_generic_insert_memory;
1120 agp_bridge.remove_memory = agp_generic_remove_memory;
1121 agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
1122 agp_bridge.free_by_type = agp_generic_free_by_type;
1123 }
1124
1125 #endif
1126
1127 #ifdef CONFIG_AGP_VIA
1128
1129 static int via_fetch_size(void)
1130 {
1131 int i;
1132 u8 temp;
1133 aper_size_info_8 *values;
1134
1135 values = A_SIZE_8(agp_bridge.aperture_sizes);
1136 pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp);
1137 for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
1138 if (temp == values[i].size_value) {
1139 agp_bridge.previous_size =
1140 agp_bridge.current_size = (void *) (values + i);
1141 agp_bridge.aperture_size_idx = i;
1142 return values[i].size;
1143 }
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int via_configure(void)
1150 {
1151 u32 temp;
1152 aper_size_info_8 *current_size;
1153
1154 current_size = A_SIZE_8(agp_bridge.current_size);
1155 /* aperture size */
1156 pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
1157 current_size->size_value);
1158 /* address to map too */
1159 pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
1160 agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1161
1162 /* GART control register */
1163 pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
1164
1165 /* attbase - aperture GATT base */
1166 pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE,
1167 (agp_bridge.gatt_bus_addr & 0xfffff000) | 3);
1168 return 0;
1169 }
1170
1171 static void via_cleanup(void)
1172 {
1173 aper_size_info_8 *previous_size;
1174
1175 previous_size = A_SIZE_8(agp_bridge.previous_size);
1176 pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE, 0);
1177 pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
1178 previous_size->size_value);
1179 }
1180
1181 static void via_tlbflush(agp_memory * mem)
1182 {
1183 pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f);
1184 pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
1185 }
1186
1187 static unsigned long via_mask_memory(unsigned long addr, int type)
1188 {
1189 /* Memory type is ignored */
1190
1191 return addr | agp_bridge.masks[0].mask;
1192 }
1193
1194 static aper_size_info_8 via_generic_sizes[7] =
1195 {
1196 {256, 65536, 6, 0},
1197 {128, 32768, 5, 128},
1198 {64, 16384, 4, 192},
1199 {32, 8192, 3, 224},
1200 {16, 4096, 2, 240},
1201 {8, 2048, 1, 248},
1202 {4, 1024, 0, 252}
1203 };
1204
1205 static gatt_mask via_generic_masks[] =
1206 {
1207 {0x00000000, 0}
1208 };
1209
1210 static void via_generic_setup(void)
1211 {
1212 agp_bridge.masks = via_generic_masks;
1213 agp_bridge.num_of_masks = 1;
1214 agp_bridge.aperture_sizes = (void *) via_generic_sizes;
1215 agp_bridge.size_type = U8_APER_SIZE;
1216 agp_bridge.num_aperture_sizes = 7;
1217 agp_bridge.dev_private_data = NULL;
1218 agp_bridge.needs_scratch_page = FALSE;
1219 agp_bridge.configure = via_configure;
1220 agp_bridge.fetch_size = via_fetch_size;
1221 agp_bridge.cleanup = via_cleanup;
1222 agp_bridge.tlb_flush = via_tlbflush;
1223 agp_bridge.mask_memory = via_mask_memory;
1224 agp_bridge.agp_enable = agp_generic_agp_enable;
1225 agp_bridge.cache_flush = global_cache_flush;
1226 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
1227 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
1228 agp_bridge.insert_memory = agp_generic_insert_memory;
1229 agp_bridge.remove_memory = agp_generic_remove_memory;
1230 agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
1231 agp_bridge.free_by_type = agp_generic_free_by_type;
1232 }
1233
1234 #endif
1235
1236 #ifdef CONFIG_AGP_SIS
1237
1238 static int sis_fetch_size(void)
1239 {
1240 u8 temp_size;
1241 int i;
1242 aper_size_info_8 *values;
1243
1244 pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
1245 values = A_SIZE_8(agp_bridge.aperture_sizes);
1246 for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
1247 if ((temp_size == values[i].size_value) ||
1248 ((temp_size & ~(0x03)) ==
1249 (values[i].size_value & ~(0x03)))) {
1250 agp_bridge.previous_size =
1251 agp_bridge.current_size = (void *) (values + i);
1252
1253 agp_bridge.aperture_size_idx = i;
1254 return values[i].size;
1255 }
1256 }
1257
1258 return 0;
1259 }
1260
1261
1262 static void sis_tlbflush(agp_memory * mem)
1263 {
1264 pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
1265 }
1266
1267 static int sis_configure(void)
1268 {
1269 u32 temp;
1270 aper_size_info_8 *current_size;
1271
1272 current_size = A_SIZE_8(agp_bridge.current_size);
1273 pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
1274 pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
1275 agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1276 pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
1277 agp_bridge.gatt_bus_addr);
1278 pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
1279 current_size->size_value);
1280 return 0;
1281 }
1282
1283 static void sis_cleanup(void)
1284 {
1285 aper_size_info_8 *previous_size;
1286
1287 previous_size = A_SIZE_8(agp_bridge.previous_size);
1288 pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
1289 (previous_size->size_value & ~(0x03)));
1290 }
1291
1292 static unsigned long sis_mask_memory(unsigned long addr, int type)
1293 {
1294 /* Memory type is ignored */
1295
1296 return addr | agp_bridge.masks[0].mask;
1297 }
1298
1299 static aper_size_info_8 sis_generic_sizes[7] =
1300 {
1301 {256, 65536, 6, 99},
1302 {128, 32768, 5, 83},
1303 {64, 16384, 4, 67},
1304 {32, 8192, 3, 51},
1305 {16, 4096, 2, 35},
1306 {8, 2048, 1, 19},
1307 {4, 1024, 0, 3}
1308 };
1309
1310 static gatt_mask sis_generic_masks[] =
1311 {
1312 {0x00000000, 0}
1313 };
1314
1315 static void sis_generic_setup(void)
1316 {
1317 agp_bridge.masks = sis_generic_masks;
1318 agp_bridge.num_of_masks = 1;
1319 agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
1320 agp_bridge.size_type = U8_APER_SIZE;
1321 agp_bridge.num_aperture_sizes = 7;
1322 agp_bridge.dev_private_data = NULL;
1323 agp_bridge.needs_scratch_page = FALSE;
1324 agp_bridge.configure = sis_configure;
1325 agp_bridge.fetch_size = sis_fetch_size;
1326 agp_bridge.cleanup = sis_cleanup;
1327 agp_bridge.tlb_flush = sis_tlbflush;
1328 agp_bridge.mask_memory = sis_mask_memory;
1329 agp_bridge.agp_enable = agp_generic_agp_enable;
1330 agp_bridge.cache_flush = global_cache_flush;
1331 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
1332 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
1333 agp_bridge.insert_memory = agp_generic_insert_memory;
1334 agp_bridge.remove_memory = agp_generic_remove_memory;
1335 agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
1336 agp_bridge.free_by_type = agp_generic_free_by_type;
1337 }
1338
1339 #endif
1340
1341 #ifdef CONFIG_AGP_AMD
1342
1343 static struct _amd_irongate_private {
1344 volatile u8 *registers;
1345 } amd_irongate_private;
1346
1347 static int amd_irongate_fetch_size(void)
1348 {
1349 int i;
1350 u32 temp;
1351 aper_size_info_32 *values;
1352
1353 pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
1354 temp = (temp & 0x0000000e);
1355 values = A_SIZE_32(agp_bridge.aperture_sizes);
1356 for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
1357 if (temp == values[i].size_value) {
1358 agp_bridge.previous_size =
1359 agp_bridge.current_size = (void *) (values + i);
1360
1361 agp_bridge.aperture_size_idx = i;
1362 return values[i].size;
1363 }
1364 }
1365
1366 return 0;
1367 }
1368
1369 static int amd_irongate_configure(void)
1370 {
1371 aper_size_info_32 *current_size;
1372 unsigned long addr;
1373 u32 temp;
1374 u16 enable_reg;
1375
1376 current_size = A_SIZE_32(agp_bridge.current_size);
1377
1378 /* Get the memory mapped registers */
1379 pci_read_config_dword(agp_bridge.dev, AMD_MMBASE, &temp);
1380 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1381 amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
1382
1383 /* Write out the address of the gatt table */
1384 OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
1385 agp_bridge.gatt_bus_addr);
1386
1387 /* Write the Sync register */
1388 pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL, 0x80);
1389
1390 /* Write the enable register */
1391 enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
1392 enable_reg = (enable_reg | 0x0004);
1393 OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
1394
1395 /* Write out the size register */
1396 pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
1397 temp = (((temp & ~(0x0000000e)) | current_size->size_value)
1398 | 0x00000001);
1399 pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
1400
1401 /* Flush the tlb */
1402 OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
1403
1404 /* Get the address for the gart region */
1405 pci_read_config_dword(agp_bridge.dev, AMD_APBASE, &temp);
1406 addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1407 #ifdef __alpha__
1408 /* ??? Presumably what is wanted is the bus address as seen
1409 from the CPU side, since it appears that this value is
1410 exported to userland via an ioctl. The terminology below
1411 is confused, mixing `physical address' with `bus address',
1412 as x86 folk are wont to do. */
1413 addr = virt_to_phys(ioremap(addr, 0));
1414 #endif
1415 agp_bridge.gart_bus_addr = addr;
1416 return 0;
1417 }
1418
1419 static void amd_irongate_cleanup(void)
1420 {
1421 aper_size_info_32 *previous_size;
1422 u32 temp;
1423 u16 enable_reg;
1424
1425 previous_size = A_SIZE_32(agp_bridge.previous_size);
1426
1427 enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
1428 enable_reg = (enable_reg & ~(0x0004));
1429 OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
1430
1431 /* Write back the previous size and disable gart translation */
1432 pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
1433 temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
1434 pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
1435 iounmap((void *) amd_irongate_private.registers);
1436 }
1437
1438 /*
1439 * This routine could be implemented by taking the addresses
1440 * written to the GATT, and flushing them individually. However
1441 * currently it just flushes the whole table. Which is probably
1442 * more efficent, since agp_memory blocks can be a large number of
1443 * entries.
1444 */
1445
1446 static void amd_irongate_tlbflush(agp_memory * temp)
1447 {
1448 OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
1449 }
1450
1451 static unsigned long amd_irongate_mask_memory(unsigned long addr, int type)
1452 {
1453 /* Only type 0 is supported by the irongate */
1454
1455 return addr | agp_bridge.masks[0].mask;
1456 }
1457
1458 static aper_size_info_32 amd_irongate_sizes[7] =
1459 {
1460 {2048, 524288, 9, 0x0000000c},
1461 {1024, 262144, 8, 0x0000000a},
1462 {512, 131072, 7, 0x00000008},
1463 {256, 65536, 6, 0x00000006},
1464 {128, 32768, 5, 0x00000004},
1465 {64, 16384, 4, 0x00000002},
1466 {32, 8192, 3, 0x00000000}
1467 };
1468
1469 static gatt_mask amd_irongate_masks[] =
1470 {
1471 {0x00000001, 0}
1472 };
1473
1474 static void amd_irongate_setup(void)
1475 {
1476 agp_bridge.masks = amd_irongate_masks;
1477 agp_bridge.num_of_masks = 1;
1478 agp_bridge.aperture_sizes = (void *) amd_irongate_sizes;
1479 agp_bridge.size_type = U32_APER_SIZE;
1480 agp_bridge.num_aperture_sizes = 7;
1481 agp_bridge.dev_private_data = (void *) &amd_irongate_private;
1482 agp_bridge.needs_scratch_page = FALSE;
1483 agp_bridge.configure = amd_irongate_configure;
1484 agp_bridge.fetch_size = amd_irongate_fetch_size;
1485 agp_bridge.cleanup = amd_irongate_cleanup;
1486 agp_bridge.tlb_flush = amd_irongate_tlbflush;
1487 agp_bridge.mask_memory = amd_irongate_mask_memory;
1488 agp_bridge.agp_enable = agp_generic_agp_enable;
1489 agp_bridge.cache_flush = global_cache_flush;
1490 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
1491 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
1492 agp_bridge.insert_memory = agp_generic_insert_memory;
1493 agp_bridge.remove_memory = agp_generic_remove_memory;
1494 agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
1495 agp_bridge.free_by_type = agp_generic_free_by_type;
1496 }
1497
1498 #endif
1499
1500 #ifdef CONFIG_AGP_ALI
1501
1502 static int ali_fetch_size(void)
1503 {
1504 int i;
1505 u32 temp;
1506 aper_size_info_32 *values;
1507
1508 pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
1509 temp &= ~(0xfffffff0);
1510 values = A_SIZE_32(agp_bridge.aperture_sizes);
1511
1512 for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
1513 if (temp == values[i].size_value) {
1514 agp_bridge.previous_size =
1515 agp_bridge.current_size = (void *) (values + i);
1516 agp_bridge.aperture_size_idx = i;
1517 return values[i].size;
1518 }
1519 }
1520
1521 return 0;
1522 }
1523
1524 static void ali_tlbflush(agp_memory * mem)
1525 {
1526 u32 temp;
1527
1528 pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
1529 pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL,
1530 ((temp & 0xffffff00) | 0x00000090));
1531 pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL,
1532 ((temp & 0xffffff00) | 0x00000010));
1533 }
1534
1535 static void ali_cleanup(void)
1536 {
1537 aper_size_info_32 *previous_size;
1538 u32 temp;
1539
1540 previous_size = A_SIZE_32(agp_bridge.previous_size);
1541
1542 pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
1543 pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL,
1544 ((temp & 0xffffff00) | 0x00000090));
1545 pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
1546 previous_size->size_value);
1547 }
1548
1549 static int ali_configure(void)
1550 {
1551 u32 temp;
1552 aper_size_info_32 *current_size;
1553
1554 current_size = A_SIZE_32(agp_bridge.current_size);
1555
1556 /* aperture size and gatt addr */
1557 pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
1558 agp_bridge.gatt_bus_addr | current_size->size_value);
1559
1560 /* tlb control */
1561 pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
1562 pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL,
1563 ((temp & 0xffffff00) | 0x00000010));
1564
1565 /* address to map to */
1566 pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
1567 agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1568 return 0;
1569 }
1570
1571 static unsigned long ali_mask_memory(unsigned long addr, int type)
1572 {
1573 /* Memory type is ignored */
1574
1575 return addr | agp_bridge.masks[0].mask;
1576 }
1577
1578
1579 /* Setup function */
1580 static gatt_mask ali_generic_masks[] =
1581 {
1582 {0x00000000, 0}
1583 };
1584
1585 static aper_size_info_32 ali_generic_sizes[7] =
1586 {
1587 {256, 65536, 6, 10},
1588 {128, 32768, 5, 9},
1589 {64, 16384, 4, 8},
1590 {32, 8192, 3, 7},
1591 {16, 4096, 2, 6},
1592 {8, 2048, 1, 4},
1593 {4, 1024, 0, 3}
1594 };
1595
1596 static void ali_generic_setup(void)
1597 {
1598 agp_bridge.masks = ali_generic_masks;
1599 agp_bridge.num_of_masks = 1;
1600 agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
1601 agp_bridge.size_type = U32_APER_SIZE;
1602 agp_bridge.num_aperture_sizes = 7;
1603 agp_bridge.dev_private_data = NULL;
1604 agp_bridge.needs_scratch_page = FALSE;
1605 agp_bridge.configure = ali_configure;
1606 agp_bridge.fetch_size = ali_fetch_size;
1607 agp_bridge.cleanup = ali_cleanup;
1608 agp_bridge.tlb_flush = ali_tlbflush;
1609 agp_bridge.mask_memory = ali_mask_memory;
1610 agp_bridge.agp_enable = agp_generic_agp_enable;
1611 agp_bridge.cache_flush = global_cache_flush;
1612 agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
1613 agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
1614 agp_bridge.insert_memory = agp_generic_insert_memory;
1615 agp_bridge.remove_memory = agp_generic_remove_memory;
1616 agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
1617 agp_bridge.free_by_type = agp_generic_free_by_type;
1618 }
1619
1620 #endif
1621
1622
1623
1624 /* Supported Device Scanning routine */
1625
1626 static void agp_find_supported_device(void)
1627 {
1628 struct pci_dev *dev = NULL;
1629 u8 cap_ptr = 0x00;
1630 u32 cap_id, scratch;
1631
1632 if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) == NULL) {
1633 agp_bridge.type = NOT_SUPPORTED;
1634 return;
1635 }
1636 agp_bridge.dev = dev;
1637
1638 /* Need to test for I810 here */
1639 #ifdef CONFIG_AGP_I810
1640 if (dev->vendor == PCI_VENDOR_ID_INTEL) {
1641 struct pci_dev *i810_dev;
1642
1643 switch (dev->device) {
1644 case PCI_DEVICE_ID_INTEL_810_0:
1645 i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
1646 PCI_DEVICE_ID_INTEL_810_1,
1647 NULL);
1648 if (i810_dev == NULL) {
1649 printk("agpgart: Detected an Intel i810,"
1650 " but could not find the secondary"
1651 " device.\n");
1652 agp_bridge.type = NOT_SUPPORTED;
1653 return;
1654 }
1655 printk(KERN_INFO "agpgart: Detected an Intel "
1656 "i810 Chipset.\n");
1657 agp_bridge.type = INTEL_I810;
1658 agp_bridge.intel_i810_setup(i810_dev);
1659 return;
1660
1661 case PCI_DEVICE_ID_INTEL_810_DC100_0:
1662 i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
1663 PCI_DEVICE_ID_INTEL_810_DC100_1,
1664 NULL);
1665 if (i810_dev == NULL) {
1666 printk("agpgart: Detected an Intel i810 "
1667 "DC100, but could not find the "
1668 "secondary device.\n");
1669 agp_bridge.type = NOT_SUPPORTED;
1670 return;
1671 }
1672 printk(KERN_INFO "agpgart: Detected an Intel i810 "
1673 "DC100 Chipset.\n");
1674 agp_bridge.type = INTEL_I810;
1675 agp_bridge.intel_i810_setup(i810_dev);
1676 return;
1677
1678 case PCI_DEVICE_ID_INTEL_810_E_0:
1679 i810_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
1680 PCI_DEVICE_ID_INTEL_810_E_1,
1681 NULL);
1682 if (i810_dev == NULL) {
1683 printk("agpgart: Detected an Intel i810 E"
1684 ", but could not find the secondary "
1685 "device.\n");
1686 agp_bridge.type = NOT_SUPPORTED;
1687 return;
1688 }
1689 printk(KERN_INFO "agpgart: Detected an Intel i810 E "
1690 "Chipset.\n");
1691 agp_bridge.type = INTEL_I810;
1692 agp_bridge.intel_i810_setup(i810_dev);
1693 return;
1694 default:
1695 break;
1696 }
1697 }
1698 #endif
1699 /* find capndx */
1700 pci_read_config_dword(dev, 0x04, &scratch);
1701
1702 if (!(scratch & 0x00100000)) {
1703 agp_bridge.type = NOT_SUPPORTED;
1704 return;
1705 }
1706 pci_read_config_byte(dev, 0x34, &cap_ptr);
1707
1708 if (cap_ptr != 0x00) {
1709 do {
1710 pci_read_config_dword(dev, cap_ptr, &cap_id);
1711
1712 if ((cap_id & 0xff) != 0x02)
1713 cap_ptr = (cap_id >> 8) & 0xff;
1714 }
1715 while (((cap_id & 0xff) != 0x02) && (cap_ptr != 0x00));
1716 }
1717 if (cap_ptr == 0x00) {
1718 agp_bridge.type = NOT_SUPPORTED;
1719 return;
1720 }
1721 agp_bridge.capndx = cap_ptr;
1722
1723 /* Fill in the mode register */
1724 pci_read_config_dword(agp_bridge.dev,
1725 agp_bridge.capndx + 4,
1726 &agp_bridge.mode);
1727
1728 switch (dev->vendor) {
1729 #ifdef CONFIG_AGP_INTEL
1730 case PCI_VENDOR_ID_INTEL:
1731 switch (dev->device) {
1732 case PCI_DEVICE_ID_INTEL_82443LX_0:
1733 agp_bridge.type = INTEL_LX;
1734 printk(KERN_INFO "agpgart: Detected an Intel 440LX"
1735 " Chipset.\n");
1736 agp_bridge.intel_generic_setup();
1737 return;
1738
1739 case PCI_DEVICE_ID_INTEL_82443BX_0:
1740 agp_bridge.type = INTEL_BX;
1741 printk(KERN_INFO "agpgart: Detected an Intel 440BX "
1742 "Chipset.\n");
1743 agp_bridge.intel_generic_setup();
1744 return;
1745
1746 case PCI_DEVICE_ID_INTEL_82443GX_0:
1747 agp_bridge.type = INTEL_GX;
1748 printk(KERN_INFO "agpgart: Detected an Intel 440GX "
1749 "Chipset.\n");
1750 agp_bridge.intel_generic_setup();
1751 return;
1752
1753 default:
1754 if (agp_try_unsupported != 0) {
1755 printk("agpgart: Trying generic intel "
1756 "routines for device id: %x\n",
1757 dev->device);
1758 agp_bridge.type = INTEL_GENERIC;
1759 agp_bridge.intel_generic_setup();
1760 return;
1761 } else {
1762 printk("agpgart: Unsupported intel chipset,"
1763 " you might want to try "
1764 "agp_try_unsupported=1.\n");
1765 agp_bridge.type = NOT_SUPPORTED;
1766 return;
1767 }
1768 }
1769 break;
1770 #endif
1771
1772 #ifdef CONFIG_AGP_VIA
1773 case PCI_VENDOR_ID_VIA:
1774 switch (dev->device) {
1775 case PCI_DEVICE_ID_VIA_82C597_0:
1776 agp_bridge.type = VIA_VP3;
1777 printk(KERN_INFO "agpgart: Detected a VIA VP3 "
1778 "Chipset.\n");
1779 agp_bridge.via_generic_setup();
1780 return;
1781
1782 case PCI_DEVICE_ID_VIA_82C598_0:
1783 agp_bridge.type = VIA_MVP3;
1784 printk(KERN_INFO "agpgart: Detected a VIA MVP3 "
1785 "Chipset.\n");
1786 agp_bridge.via_generic_setup();
1787 return;
1788
1789 case PCI_DEVICE_ID_VIA_82C691_0:
1790 agp_bridge.type = VIA_APOLLO_PRO;
1791 printk(KERN_INFO "agpgart: Detected a VIA Apollo "
1792 "Pro Chipset.\n");
1793 agp_bridge.via_generic_setup();
1794 return;
1795
1796 default:
1797 if (agp_try_unsupported != 0) {
1798 printk("agpgart: Trying generic VIA routines"
1799 " for device id: %x\n", dev->device);
1800 agp_bridge.type = VIA_GENERIC;
1801 agp_bridge.via_generic_setup();
1802 return;
1803 } else {
1804 printk("agpgart: Unsupported VIA chipset,"
1805 " you might want to try "
1806 "agp_try_unsupported=1.\n");
1807 agp_bridge.type = NOT_SUPPORTED;
1808 return;
1809 }
1810 }
1811 break;
1812 #endif
1813
1814 #ifdef CONFIG_AGP_SIS
1815 case PCI_VENDOR_ID_SI:
1816 switch (dev->device) {
1817 /* ToDo need to find out the
1818 * specific devices supported.
1819 */
1820 default:
1821 if (agp_try_unsupported != 0) {
1822 printk("agpgart: Trying generic SiS routines"
1823 " for device id: %x\n", dev->device);
1824 agp_bridge.type = SIS_GENERIC;
1825 agp_bridge.sis_generic_setup();
1826 return;
1827 } else {
1828 printk("agpgart: Unsupported SiS chipset, "
1829 "you might want to try "
1830 "agp_try_unsupported=1.\n");
1831 agp_bridge.type = NOT_SUPPORTED;
1832 return;
1833 }
1834 }
1835 break;
1836 #endif
1837
1838 #ifdef CONFIG_AGP_AMD
1839 case PCI_VENDOR_ID_AMD:
1840 switch (dev->device) {
1841 case PCI_DEVICE_ID_AMD_IRONGATE_0:
1842 agp_bridge.type = AMD_IRONGATE;
1843 printk(KERN_INFO "agpgart: Detected an AMD Irongate"
1844 " Chipset.\n");
1845 agp_bridge.amd_irongate_setup();
1846 return;
1847
1848 default:
1849 if (agp_try_unsupported != 0) {
1850 printk("agpgart: Trying Amd irongate"
1851 " routines for device id: %x\n",
1852 dev->device);
1853 agp_bridge.type = AMD_GENERIC;
1854 agp_bridge.amd_irongate_setup();
1855 return;
1856 } else {
1857 printk("agpgart: Unsupported Amd chipset,"
1858 " you might want to try "
1859 "agp_try_unsupported=1.\n");
1860 agp_bridge.type = NOT_SUPPORTED;
1861 return;
1862 }
1863 }
1864 break;
1865 #endif
1866
1867 #ifdef CONFIG_AGP_ALI
1868 case PCI_VENDOR_ID_AL:
1869 switch (dev->device) {
1870 case PCI_DEVICE_ID_AL_M1541_0:
1871 agp_bridge.type = ALI_M1541;
1872 printk(KERN_INFO "agpgart: Detected an ALi M1541"
1873 " Chipset\n");
1874 agp_bridge.ali_generic_setup();
1875 return;
1876 default:
1877 if (agp_try_unsupported != 0) {
1878 printk("agpgart: Trying ALi generic routines"
1879 " for device id: %x\n", dev->device);
1880 agp_bridge.type = ALI_GENERIC;
1881 agp_bridge.ali_generic_setup();
1882 return;
1883 } else {
1884 printk("agpgart: Unsupported ALi chipset,"
1885 " you might want to type "
1886 "agp_try_unsupported=1.\n");
1887 agp_bridge.type = NOT_SUPPORTED;
1888 return;
1889 }
1890 }
1891 break;
1892 #endif
1893 default:
1894 agp_bridge.type = NOT_SUPPORTED;
1895 return;
1896 }
1897 }
1898
1899 struct agp_max_table {
1900 int mem;
1901 int agp;
1902 };
1903
1904 static struct agp_max_table maxes_table[9] =
1905 {
1906 {0, 0},
1907 {32, 4},
1908 {64, 28},
1909 {128, 96},
1910 {256, 204},
1911 {512, 440},
1912 {1024, 942},
1913 {2048, 1920},
1914 {4096, 3932}
1915 };
1916
1917 static int agp_find_max(void)
1918 {
1919 long memory, t, index, result;
1920
1921 memory = virt_to_phys(high_memory) >> 20;
1922 index = 1;
1923
1924 while ((memory > maxes_table[index].mem) &&
1925 (index < 8)) {
1926 index++;
1927 }
1928
1929 t = (memory - maxes_table[index - 1].mem) /
1930 (maxes_table[index].mem - maxes_table[index - 1].mem);
1931
1932 result = maxes_table[index - 1].agp +
1933 (t * (maxes_table[index].agp - maxes_table[index - 1].agp));
1934
1935 printk(KERN_INFO "agpgart: Maximum main memory to use "
1936 "for agp memory: %ldM\n", result);
1937 result = result << (20 - PAGE_SHIFT);
1938 return result;
1939 }
1940
1941 #define AGPGART_VERSION_MAJOR 0
1942 #define AGPGART_VERSION_MINOR 99
1943
1944 static agp_version agp_current_version =
1945 {
1946 AGPGART_VERSION_MAJOR,
1947 AGPGART_VERSION_MINOR
1948 };
1949
1950 static int agp_backend_initialize(void)
1951 {
1952 int size_value;
1953
1954 memset(&agp_bridge, 0, sizeof(struct agp_bridge_data));
1955 agp_bridge.type = NOT_SUPPORTED;
1956 #ifdef CONFIG_AGP_INTEL
1957 agp_bridge.intel_generic_setup = intel_generic_setup;
1958 #endif
1959 #ifdef CONFIG_AGP_I810
1960 agp_bridge.intel_i810_setup = intel_i810_setup;
1961 #endif
1962 #ifdef CONFIG_AGP_VIA
1963 agp_bridge.via_generic_setup = via_generic_setup;
1964 #endif
1965 #ifdef CONFIG_AGP_SIS
1966 agp_bridge.sis_generic_setup = sis_generic_setup;
1967 #endif
1968 #ifdef CONFIG_AGP_AMD
1969 agp_bridge.amd_irongate_setup = amd_irongate_setup;
1970 #endif
1971 #ifdef CONFIG_AGP_ALI
1972 agp_bridge.ali_generic_setup = ali_generic_setup;
1973 #endif
1974 agp_bridge.max_memory_agp = agp_find_max();
1975 agp_bridge.version = &agp_current_version;
1976 agp_find_supported_device();
1977
1978 if (agp_bridge.needs_scratch_page == TRUE) {
1979 agp_bridge.scratch_page = agp_alloc_page();
1980
1981 if (agp_bridge.scratch_page == 0) {
1982 printk("agpgart: unable to get memory for "
1983 "scratch page.\n");
1984 return -ENOMEM;
1985 }
1986 agp_bridge.scratch_page =
1987 virt_to_phys((void *) agp_bridge.scratch_page);
1988 agp_bridge.scratch_page =
1989 agp_bridge.mask_memory(agp_bridge.scratch_page, 0);
1990 }
1991 if (agp_bridge.type == NOT_SUPPORTED) {
1992 printk("agpgart: no supported devices found.\n");
1993 return -EINVAL;
1994 }
1995 size_value = agp_bridge.fetch_size();
1996
1997 if (size_value == 0) {
1998 printk("agpgart: unable to detrimine aperture size.\n");
1999 return -EINVAL;
2000 }
2001 if (agp_bridge.create_gatt_table()) {
2002 printk("agpgart: unable to get memory for graphics "
2003 "translation table.\n");
2004 return -ENOMEM;
2005 }
2006 agp_bridge.key_list = vmalloc(PAGE_SIZE * 4);
2007
2008 if (agp_bridge.key_list == NULL) {
2009 printk("agpgart: error allocating memory for key lists.\n");
2010 agp_bridge.free_gatt_table();
2011 return -ENOMEM;
2012 }
2013 memset(agp_bridge.key_list, 0, PAGE_SIZE * 4);
2014
2015 if (agp_bridge.configure()) {
2016 printk("agpgart: error configuring host chipset.\n");
2017 agp_bridge.free_gatt_table();
2018 vfree(agp_bridge.key_list);
2019 return -EINVAL;
2020 }
2021 printk(KERN_INFO "agpgart: Physical address of the agp aperture:"
2022 " 0x%lx\n", agp_bridge.gart_bus_addr);
2023 printk(KERN_INFO "agpgart: Agp aperture is %dM in size.\n",
2024 size_value);
2025 return 0;
2026 }
2027
2028 static void agp_backend_cleanup(void)
2029 {
2030 agp_bridge.cleanup();
2031 agp_bridge.free_gatt_table();
2032 vfree(agp_bridge.key_list);
2033
2034 if (agp_bridge.needs_scratch_page == TRUE) {
2035 agp_bridge.scratch_page &= ~(0x00000fff);
2036 agp_destroy_page((unsigned long)
2037 phys_to_virt(agp_bridge.scratch_page));
2038 }
2039 }
2040
2041 extern int agp_frontend_initialize(void);
2042 extern void agp_frontend_cleanup(void);
2043
2044 static int __init agp_init(void)
2045 {
2046 int ret_val;
2047
2048 printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Jeff Hartmann\n",
2049 AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR);
2050 ret_val = agp_backend_initialize();
2051
2052 if (ret_val != 0) {
2053 return ret_val;
2054 }
2055 ret_val = agp_frontend_initialize();
2056
2057 if (ret_val != 0) {
2058 agp_backend_cleanup();
2059 return ret_val;
2060 }
2061 return 0;
2062 }
2063
2064 static void __exit agp_cleanup(void)
2065 {
2066 agp_frontend_cleanup();
2067 agp_backend_cleanup();
2068 }
2069
2070 module_init(agp_init);
2071 module_exit(agp_cleanup);
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