2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <asm/sn/arch.h>
13 #include <asm/pci/bridge.h>
14 #include <asm/paccess.h>
15 #include <asm/sn/sn0/ip27.h>
16 #include <asm/sn/sn0/hub.h>
19 * Max #PCI busses we can handle; ie, max #PCI bridges.
21 #define MAX_PCI_BUSSES 20
24 * Max #PCI devices (like scsi controllers) we handle on a bus.
26 #define MAX_DEVICES_PER_PCIBUS 8
29 * No locking needed until PCI initialization is done parallely.
31 int irqstore
[MAX_PCI_BUSSES
][MAX_DEVICES_PER_PCIBUS
];
32 int lastirq
= BASE_PCI_IRQ
;
35 * Translate from irq to software PCI bus number and PCI slot.
37 int irq_to_bus
[MAX_PCI_BUSSES
* MAX_DEVICES_PER_PCIBUS
];
38 int irq_to_slot
[MAX_PCI_BUSSES
* MAX_DEVICES_PER_PCIBUS
];
41 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
42 * not really documented, so right now I can't write code which uses it.
43 * Therefore we use type 0 accesses for now even though they won't work
44 * correcly for PCI-to-PCI bridges.
46 #define CF0_READ_PCI_CFG(dev,where,value,bm,mask) \
49 int slot = PCI_SLOT(dev->devfn); \
50 int fn = PCI_FUNC(dev->devfn); \
53 unsigned int bus_id = (unsigned) dev->bus->number; \
55 bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \
56 bus_to_wid[bus_id]); \
58 /*if (dev->bus->number) */ \
59 /* return PCIBIOS_DEVICE_NOT_FOUND; */ \
61 __bit = (((where) & (bm)) << 3); \
62 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \
63 if (get_dbe(cf, addr)) \
64 return PCIBIOS_DEVICE_NOT_FOUND; \
65 *value = (cf >> __bit) & (mask); \
66 return PCIBIOS_SUCCESSFUL; \
70 pci_conf0_read_config_byte(struct pci_dev
*dev
, int where
, u8
*value
)
72 CF0_READ_PCI_CFG(dev
,where
,value
,3,0xff);
76 pci_conf0_read_config_word(struct pci_dev
*dev
, int where
, u16
*value
)
78 CF0_READ_PCI_CFG(dev
,where
,value
,2,0xffff);
82 pci_conf0_read_config_dword(struct pci_dev
*dev
, int where
, u32
*value
)
84 CF0_READ_PCI_CFG(dev
,where
,value
,0,0xffffffff);
87 #define CF0_WRITE_PCI_CFG(dev,where,value,bm,mask) \
90 int slot = PCI_SLOT(dev->devfn); \
91 int fn = PCI_FUNC(dev->devfn); \
94 unsigned int bus_id = (unsigned) dev->bus->number; \
96 bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \
97 bus_to_wid[bus_id]); \
99 /* if (dev->bus->number) */ \
100 /* return PCIBIOS_DEVICE_NOT_FOUND; */ \
102 if (dev->vendor == PCI_VENDOR_ID_SGI \
103 && dev->device == PCI_DEVICE_ID_SGI_IOC3) \
104 return PCIBIOS_SUCCESSFUL; \
106 __bit = (((where) & (bm)) << 3); \
107 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \
108 if (get_dbe(cf, addr)) \
109 return PCIBIOS_DEVICE_NOT_FOUND; \
113 return PCIBIOS_SUCCESSFUL; \
117 pci_conf0_write_config_byte(struct pci_dev
*dev
, int where
, u8 value
)
119 CF0_WRITE_PCI_CFG(dev
,where
,value
,3,0xff);
123 pci_conf0_write_config_word(struct pci_dev
*dev
, int where
, u16 value
)
125 CF0_WRITE_PCI_CFG(dev
,where
,value
,2,0xffff);
129 pci_conf0_write_config_dword(struct pci_dev
*dev
, int where
, u32 value
)
131 CF0_WRITE_PCI_CFG(dev
,where
,value
,0,0xffffffff);
135 static struct pci_ops bridge_pci_ops
= {
136 pci_conf0_read_config_byte
,
137 pci_conf0_read_config_word
,
138 pci_conf0_read_config_dword
,
139 pci_conf0_write_config_byte
,
140 pci_conf0_write_config_word
,
141 pci_conf0_write_config_dword
144 void __init
pcibios_init(void)
146 struct pci_ops
*ops
= &bridge_pci_ops
;
149 ioport_resource
.end
= ~0UL;
151 for (i
=0; i
<num_bridges
; i
++) {
152 printk("PCI: Probing PCI hardware on host bus %2d.\n", i
);
153 pci_scan_bus(i
, ops
, NULL
);
158 bridge_swizzle(u8 pin
, u8 slot
)
160 return (((pin
-1) + slot
) % 4) + 1;
164 pci_swizzle(struct pci_dev
*dev
, u8
*pinp
)
168 while (dev
->bus
->self
) { /* Move up the chain of bridges. */
169 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
170 dev
= dev
->bus
->self
;
174 return PCI_SLOT(dev
->devfn
);
178 * All observed requests have pin == 1. We could have a global here, that
179 * gets incremented and returned every time - unfortunately, pci_map_irq
180 * may be called on the same device over and over, and need to return the
181 * same value. On o2000, pin can be 0 or 1, and PCI slots can be [0..7].
183 * A given PCI device, in general, should be able to intr any of the cpus
184 * on any one of the hubs connected to its xbow.
187 pci_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
189 if ((dev
->bus
->number
>= MAX_PCI_BUSSES
) || (pin
!= 1) || \
190 (slot
>= MAX_DEVICES_PER_PCIBUS
)) {
191 printk("Increase supported PCI busses %d,%d,%d\n", \
192 dev
->bus
->number
, slot
, pin
);
197 * Already assigned? Then return previously assigned value ...
199 if (irqstore
[dev
->bus
->number
][slot
])
200 return(irqstore
[dev
->bus
->number
][slot
]);
202 irq_to_bus
[lastirq
] = dev
->bus
->number
;
203 irq_to_slot
[lastirq
] = slot
;
204 irqstore
[dev
->bus
->number
][slot
] = lastirq
;
206 return (lastirq
- 1);
211 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
213 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
217 pcibios_update_resource(struct pci_dev
*dev
, struct resource
*root
,
218 struct resource
*res
, int resource
)
220 unsigned long where
, size
;
223 where
= PCI_BASE_ADDRESS_0
+ (resource
* 4);
224 size
= res
->end
- res
->start
;
225 pci_read_config_dword(dev
, where
, ®
);
226 reg
= (reg
& size
) | (((u32
)(res
->start
- root
->start
)) & ~size
);
227 pci_write_config_dword(dev
, where
, reg
);
231 pcibios_fixup_bus(struct pci_bus
*b
)
233 pci_fixup_irqs(pci_swizzle
, pci_map_irq
);
237 pcibios_fixup_pbus_ranges(struct pci_bus
* bus
,
238 struct pbus_set_ranges_data
* ranges
)
240 ranges
->io_start
-= bus
->resource
[0]->start
;
241 ranges
->io_end
-= bus
->resource
[0]->start
;
242 ranges
->mem_start
-= bus
->resource
[1]->start
;
243 ranges
->mem_end
-= bus
->resource
[1]->start
;
247 pcibios_enable_device(struct pci_dev
*dev
)
249 /* Not needed, since we enable all devices at startup. */
254 pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
)
259 pcibios_setup(char *str
)
261 /* Nothing to do for now. */
267 pci_disable_swapping(struct pci_dev
*dev
)
269 unsigned int bus_id
= (unsigned) dev
->bus
->number
;
270 bridge_t
*bridge
= (bridge_t
*) NODE_SWIN_BASE(bus_to_nid
[bus_id
],
272 int slot
= PCI_SLOT(dev
->devfn
);
275 devreg
= bridge
->b_device
[slot
].reg
;
276 devreg
&= ~BRIDGE_DEV_SWAP_DIR
; /* turn off byte swapping */
277 bridge
->b_device
[slot
].reg
= devreg
;
279 bridge
->b_widget
.w_tflush
; /* Flush */
283 pci_enable_swapping(struct pci_dev
*dev
)
285 unsigned int bus_id
= (unsigned) dev
->bus
->number
;
286 bridge_t
*bridge
= (bridge_t
*) NODE_SWIN_BASE(bus_to_nid
[bus_id
],
288 int slot
= PCI_SLOT(dev
->devfn
);
291 devreg
= bridge
->b_device
[slot
].reg
;
292 devreg
|= BRIDGE_DEV_SWAP_DIR
; /* turn on byte swapping */
293 bridge
->b_device
[slot
].reg
= devreg
;
295 bridge
->b_widget
.w_tflush
; /* Flush */
299 pci_fixup_ioc3(struct pci_dev
*d
)
301 unsigned int bus_id
= (unsigned) d
->bus
->number
;
304 /* IOC3 only decodes 0x20 bytes of the config space, so we end up
305 with tons of bogus information in the pci_dev. On Origins the
306 INTA, INTB and INTC pins are all wired together as if it'd only
308 printk("PCI: Fixing base addresses for IOC3 device %s\n", d
->slot_name
);
310 d
->resource
[0].start
|= NODE_OFFSET(bus_to_nid
[bus_id
]);
311 d
->resource
[0].end
|= NODE_OFFSET(bus_to_nid
[bus_id
]);
313 for (i
= 1; i
<= PCI_ROM_RESOURCE
; i
++) {
314 d
->resource
[i
].start
= 0UL;
315 d
->resource
[i
].end
= 0UL;
316 d
->resource
[i
].flags
= 0UL;
319 pci_disable_swapping(d
);
322 * The serial driver will try to probe for serial ports
323 * later on. MENET boards dbe out unrecoverably on sio space
324 * access to the 4th ioc3. (The first 3 iocs work okay, they
325 * have kbd/ms ports; all have ethernet ports). Catch this
326 * case now and disable the serial driver from looking at
327 * these ioc3s. Identify MENET cards by seeing if an ioc3 is
330 d
->subsystem_vendor
= 0xFF00;
331 if (PCI_SLOT(d
->devfn
) == 3) {
333 list_for_each(p
, &d
->bus
->devices
) {
334 list_entry(p
, struct pci_dev
, bus_list
)->subsystem_vendor
= 0;
340 pci_fixup_isp1020(struct pci_dev
*d
)
342 unsigned short command
;
344 d
->resource
[0].start
|= ((unsigned long)(bus_to_nid
[d
->bus
->number
])<<32);
345 printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d
->slot_name
);
347 /* Configure device to allow bus mastering, i/o and memory mapping.
348 * Older qlogicisp driver expects to have the IO space enable
349 * bit set. Things stop working if we program the controllers as not
350 * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags.
354 pci_read_config_word(d
, PCI_COMMAND
, &command
);
355 command
|= PCI_COMMAND_MEMORY
;
356 command
|= PCI_COMMAND_IO
;
357 pci_write_config_word(d
, PCI_COMMAND
, command
);
358 d
->resource
[1].flags
|= 1;
360 pci_enable_swapping(d
);
364 pci_fixup_isp2x00(struct pci_dev
*d
)
366 unsigned int bus_id
= (unsigned) d
->bus
->number
;
367 bridge_t
*bridge
= (bridge_t
*) NODE_SWIN_BASE(bus_to_nid
[bus_id
],
371 int slot
= PCI_SLOT(d
->devfn
);
373 unsigned short command
;
375 printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d
->slot_name
);
377 /* set the resource struct for this device */
378 start
= (u32
) (u64
)bridge
; /* yes, we want to lose the upper 32 bits here */
379 start
|= BRIDGE_DEVIO(slot
);
381 d
->resource
[0].start
= start
;
382 d
->resource
[0].end
= d
->resource
[0].start
+ 0xff;
383 d
->resource
[0].flags
= IORESOURCE_IO
;
385 d
->resource
[1].start
= start
;
386 d
->resource
[1].end
= d
->resource
[0].start
+ 0xfff;
387 d
->resource
[1].flags
= IORESOURCE_MEM
;
390 * set the bridge device(x) reg for this device
392 devreg
= bridge
->b_device
[slot
].reg
;
393 /* point device(x) to it appropriate small window */
394 devreg
&= ~BRIDGE_DEV_OFF_MASK
;
395 devreg
|= (start
>> 20) & BRIDGE_DEV_OFF_MASK
;
396 bridge
->b_device
[slot
].reg
= devreg
;
398 pci_enable_swapping(d
);
400 /* set card's base addr reg */
401 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001);
402 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000);
403 //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000);
405 /* I got these from booting irix on system...*/
406 pci_conf0_write_config_dword(d
, PCI_BASE_ADDRESS_0
, 0x200001);
407 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000);
408 pci_conf0_write_config_dword(d
, PCI_ROM_ADDRESS
, 0x10200000);
410 pci_conf0_write_config_dword(d
, PCI_BASE_ADDRESS_1
, start
);
411 //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000));
413 /* set cache line size */
414 pci_conf0_write_config_dword(d
, PCI_CACHE_LINE_SIZE
, 0xf080);
416 /* set pci bus timeout */
417 bridge
->b_bus_timeout
|= BRIDGE_BUS_PCI_RETRY_HLD(0x3);
418 bridge
->b_wid_tflush
;
419 printk("PCI: bridge bus timeout= 0x%x \n", bridge
->b_bus_timeout
);
421 /* set host error field */
422 bridge
->b_int_host_err
= 0x44;
423 bridge
->b_wid_tflush
;
425 bridge
->b_wid_tflush
; /* wait until Bridge PIO complete */
427 printk("PCI: device(%d)= 0x%x\n",i
,bridge
->b_device
[i
].reg
);
429 /* configure device to allow bus mastering, i/o and memory mapping */
431 pci_read_config_word(d
, PCI_COMMAND
, &command
);
432 command
|= PCI_COMMAND_MEMORY
;
433 command
|= PCI_COMMAND_IO
;
434 pci_write_config_word(d
, PCI_COMMAND
, command
);
435 /*d->resource[1].flags |= 1;*/
438 struct pci_fixup pcibios_fixups
[] = {
439 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
441 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP1020
,
443 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP2100
,
445 { PCI_FIXUP_HEADER
, PCI_VENDOR_ID_QLOGIC
, PCI_DEVICE_ID_QLOGIC_ISP2200
,