2 * linux/drivers/block/pdc202xx.c Version 0.26 May 12, 1999
4 * Copyright (C) 1998-99 Andre Hedrick
5 * (hedrick@astro.dyer.vanderbilt.edu)
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
12 * The latest chipset code will support the following ::
13 * Three Ultra33 controllers and 12 drives.
14 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
15 * The 8/4 ratio is a BIOS code limit by promise.
17 * UNLESS you enable "PDC202XX_FORCE_BURST_BIT"
19 * There is only one BIOS in the three contollers.
21 * May 8 20:56:17 Orion kernel:
22 * Uniform Multi-Platform E-IDE driver Revision: 6.19
23 * PDC20246: IDE controller on PCI bus 00 dev a0
24 * PDC20246: not 100% native mode: will probe irqs later
25 * PDC20246: ROM enabled at 0xfebd0000
26 * PDC20246: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
27 * ide0: BM-DMA at 0xef80-0xef87, BIOS settings: hda:DMA, hdb:DMA
28 * ide1: BM-DMA at 0xef88-0xef8f, BIOS settings: hdc:pio, hdd:pio
29 * PDC20246: IDE controller on PCI bus 00 dev 98
30 * PDC20246: not 100% native mode: will probe irqs later
31 * PDC20246: ROM enabled at 0xfebc0000
32 * PDC20246: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
33 * ide2: BM-DMA at 0xef40-0xef47, BIOS settings: hde:DMA, hdf:DMA
34 * ide3: BM-DMA at 0xef48-0xef4f, BIOS settings: hdg:DMA, hdh:DMA
35 * PDC20246: IDE controller on PCI bus 00 dev 90
36 * PDC20246: not 100% native mode: will probe irqs later
37 * PDC20246: ROM enabled at 0xfebb0000
38 * PDC20246: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
39 * PDC20246: FORCING BURST BIT 0x00 -> 0x01 ACTIVE
40 * ide4: BM-DMA at 0xef00-0xef07, BIOS settings: hdi:DMA, hdj:pio
41 * ide5: BM-DMA at 0xef08-0xef0f, BIOS settings: hdk:pio, hdl:pio
42 * PIIX3: IDE controller on PCI bus 00 dev 39
43 * PIIX3: device not capable of full native PCI mode
45 * ide0 at 0xeff0-0xeff7,0xefe6 on irq 19
46 * ide1 at 0xefa8-0xefaf,0xebe6 on irq 19
47 * ide2 at 0xefa0-0xefa7,0xef7e on irq 18
48 * ide3 at 0xef68-0xef6f,0xef66 on irq 18
49 * ide4 at 0xef38-0xef3f,0xef62 on irq 17
50 * hda: QUANTUM FIREBALL ST6.4A, 6149MB w/81kB Cache, CHS=13328/15/63, UDMA(33)
51 * hdb: QUANTUM FIREBALL ST3.2A, 3079MB w/81kB Cache, CHS=6256/16/63, UDMA(33)
52 * hde: Maxtor 72004 AP, 1916MB w/128kB Cache, CHS=3893/16/63, DMA
53 * hdf: Maxtor 71626 A, 1554MB w/64kB Cache, CHS=3158/16/63, DMA
54 * hdi: Maxtor 90680D4, 6485MB w/256kB Cache, CHS=13176/16/63, UDMA(33)
55 * hdj: Maxtor 90680D4, 6485MB w/256kB Cache, CHS=13176/16/63, UDMA(33)
57 * Promise Ultra66 cards with BIOS v1.11 this
58 * compiled into the kernel if you have more than one card installed.
60 * PDC20262: IDE controller on PCI bus 00 dev a0
61 * PDC20262: not 100% native mode: will probe irqs later
62 * PDC20262: ROM enabled at 0xfebb0000
63 * PDC20262: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
64 * ide0: BM-DMA at 0xef00-0xef07, BIOS settings: hda:pio, hdb:pio
65 * ide1: BM-DMA at 0xef08-0xef0f, BIOS settings: hdc:pio, hdd:pio
67 * UDMA 4/2 and UDMA 3/1 only differ by the testing bit 13 in word93.
68 * Chipset timing speeds must be identical
71 * = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
72 * = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
75 #include <linux/types.h>
76 #include <linux/kernel.h>
77 #include <linux/delay.h>
78 #include <linux/timer.h>
80 #include <linux/ioport.h>
81 #include <linux/blkdev.h>
82 #include <linux/hdreg.h>
83 #include <linux/interrupt.h>
84 #include <linux/pci.h>
85 #include <linux/init.h>
86 #include <linux/ide.h>
91 #define PDC202XX_DEBUG_DRIVE_INFO 0
92 #define PDC202XX_DECODE_REGISTER_INFO 0
94 extern char *ide_xfer_verbose (byte xfer_rate
);
97 #define SYNC_ERRDY_EN 0xC0
99 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
100 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
101 #define IORDY_EN 0x20 /* PIO: IOREADY */
102 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
104 #define PA3 0x08 /* PIO"A" timing */
105 #define PA2 0x04 /* PIO"A" timing */
106 #define PA1 0x02 /* PIO"A" timing */
107 #define PA0 0x01 /* PIO"A" timing */
111 #define MB2 0x80 /* DMA"B" timing */
112 #define MB1 0x40 /* DMA"B" timing */
113 #define MB0 0x20 /* DMA"B" timing */
115 #define PB4 0x10 /* PIO_FORCE 1:0 */
117 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
118 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
119 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
120 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
123 #define IORDYp_NO_SPEED 0x4F
124 #define SPEED_DIS 0x0F
131 #define MC3 0x08 /* DMA"C" timing */
132 #define MC2 0x04 /* DMA"C" timing */
133 #define MC1 0x02 /* DMA"C" timing */
134 #define MC0 0x01 /* DMA"C" timing */
136 #if PDC202XX_DECODE_REGISTER_INFO
143 static void decode_registers (byte registers
, byte value
)
145 byte bit
= 0, bit1
= 0, bit2
= 0;
150 printk("A Register ");
151 if (value
& 0x80) printk("SYNC_IN ");
152 if (value
& 0x40) printk("ERRDY_EN ");
153 if (value
& 0x20) printk("IORDY_EN ");
154 if (value
& 0x10) printk("PREFETCH_EN ");
155 if (value
& 0x08) { printk("PA3 ");bit2
|= 0x08; }
156 if (value
& 0x04) { printk("PA2 ");bit2
|= 0x04; }
157 if (value
& 0x02) { printk("PA1 ");bit2
|= 0x02; }
158 if (value
& 0x01) { printk("PA0 ");bit2
|= 0x01; }
159 printk("PIO(A) = %d ", bit2
);
163 printk("B Register ");
164 if (value
& 0x80) { printk("MB2 ");bit1
|= 0x80; }
165 if (value
& 0x40) { printk("MB1 ");bit1
|= 0x40; }
166 if (value
& 0x20) { printk("MB0 ");bit1
|= 0x20; }
167 printk("DMA(B) = %d ", bit1
>> 5);
168 if (value
& 0x10) printk("PIO_FORCED/PB4 ");
169 if (value
& 0x08) { printk("PB3 ");bit2
|= 0x08; }
170 if (value
& 0x04) { printk("PB2 ");bit2
|= 0x04; }
171 if (value
& 0x02) { printk("PB1 ");bit2
|= 0x02; }
172 if (value
& 0x01) { printk("PB0 ");bit2
|= 0x01; }
173 printk("PIO(B) = %d ", bit2
);
177 printk("C Register ");
178 if (value
& 0x80) printk("DMARQp ");
179 if (value
& 0x40) printk("IORDYp ");
180 if (value
& 0x20) printk("DMAR_EN ");
181 if (value
& 0x10) printk("DMAW_EN ");
183 if (value
& 0x08) { printk("MC3 ");bit2
|= 0x08; }
184 if (value
& 0x04) { printk("MC2 ");bit2
|= 0x04; }
185 if (value
& 0x02) { printk("MC1 ");bit2
|= 0x02; }
186 if (value
& 0x01) { printk("MC0 ");bit2
|= 0x01; }
187 printk("DMA(C) = %d ", bit2
);
190 printk("D Register ");
195 printk("\n %s ", (registers
& REG_D
) ? "DP" :
196 (registers
& REG_C
) ? "CP" :
197 (registers
& REG_B
) ? "BP" :
198 (registers
& REG_A
) ? "AP" : "ERROR");
199 for (bit
=128;bit
>0;bit
/=2)
200 printk("%s", (value
& bit
) ? "1" : "0");
204 #endif /* PDC202XX_DECODE_REGISTER_INFO */
206 static int config_chipset_for_dma (ide_drive_t
*drive
, byte ultra
)
208 struct hd_driveid
*id
= drive
->id
;
209 ide_hwif_t
*hwif
= HWIF(drive
);
210 struct pci_dev
*dev
= hwif
->pci_dev
;
213 unsigned int drive_conf
;
215 byte test1
, test2
, speed
;
216 byte AP
, BP
, CP
, DP
, EP
;
217 int drive_number
= ((hwif
->channel
? 2 : 0) + (drive
->select
.b
.unit
& 0x01));
218 byte udma_66
= ((id
->word93
& 0x2000) && (dev
->device
== PCI_DEVICE_ID_PROMISE_20262
)) ? 1 : 0;
219 byte udma_33
= ultra
? (inb((dev
->base_address
[4] & PCI_BASE_ADDRESS_IO_MASK
) + 0x001f) & 1) : 0;
221 pci_read_config_byte(dev
, 0x50, &EP
);
223 switch(drive_number
) {
224 case 0: drive_pci
= 0x60;
225 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
226 pci_read_config_byte(dev
, (drive_pci
), &test1
);
227 if (!(test1
& SYNC_ERRDY_EN
))
228 pci_write_config_byte(dev
, (drive_pci
), test1
|SYNC_ERRDY_EN
);
230 case 1: drive_pci
= 0x64;
231 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
232 pci_read_config_byte(dev
, 0x60, &test1
);
233 pci_read_config_byte(dev
, (drive_pci
), &test2
);
234 if ((test1
& SYNC_ERRDY_EN
) && !(test2
& SYNC_ERRDY_EN
))
235 pci_write_config_byte(dev
, (drive_pci
), test2
|SYNC_ERRDY_EN
);
237 case 2: drive_pci
= 0x68;
238 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
239 pci_read_config_byte(dev
, (drive_pci
), &test1
);
240 if (!(test1
& SYNC_ERRDY_EN
))
241 pci_write_config_byte(dev
, (drive_pci
), test1
|SYNC_ERRDY_EN
);
243 case 3: drive_pci
= 0x6c;
244 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
245 pci_read_config_byte(dev
, 0x68, &test1
);
246 pci_read_config_byte(dev
, (drive_pci
), &test2
);
247 if ((test1
& SYNC_ERRDY_EN
) && !(test2
& SYNC_ERRDY_EN
))
248 pci_write_config_byte(dev
, (drive_pci
), test2
|SYNC_ERRDY_EN
);
254 if (drive
->media
!= ide_disk
)
255 return ide_dma_off_quietly
;
257 pci_read_config_byte(dev
, (drive_pci
), &AP
);
258 pci_read_config_byte(dev
, (drive_pci
)|0x01, &BP
);
259 pci_read_config_byte(dev
, (drive_pci
)|0x02, &CP
);
260 pci_read_config_byte(dev
, (drive_pci
)|0x03, &DP
);
262 if (id
->capability
& 4) { /* IORDY_EN */
263 pci_write_config_byte(dev
, (drive_pci
), AP
|IORDY_EN
);
264 pci_read_config_byte(dev
, (drive_pci
), &AP
);
267 if (drive
->media
== ide_disk
) { /* PREFETCH_EN */
268 pci_write_config_byte(dev
, (drive_pci
), AP
|PREFETCH_EN
);
269 pci_read_config_byte(dev
, (drive_pci
), &AP
);
272 if ((BP
& 0xF0) && (CP
& 0x0F)) {
273 /* clear DMA modes of upper 842 bits of B Register */
274 /* clear PIO forced mode upper 1 bit of B Register */
275 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
& ~0xF0);
276 pci_read_config_byte(dev
, (drive_pci
)|0x01, &BP
);
278 /* clear DMA modes of lower 8421 bits of C Register */
279 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
& ~0x0F);
280 pci_read_config_byte(dev
, (drive_pci
)|0x02, &CP
);
283 pci_read_config_byte(dev
, (drive_pci
), &AP
);
284 pci_read_config_byte(dev
, (drive_pci
)|0x01, &BP
);
285 pci_read_config_byte(dev
, (drive_pci
)|0x02, &CP
);
287 if ((id
->dma_ultra
& 0x0010) && (udma_66
) && (udma_33
)) {
288 if (!((id
->dma_ultra
>> 8) & 16)) {
289 drive
->id
->dma_ultra
&= ~0xFF00;
290 drive
->id
->dma_ultra
|= 0x1010;
291 drive
->id
->dma_mword
&= ~0x0F00;
292 drive
->id
->dma_1word
&= ~0x0F00;
294 /* speed 8 == UDMA mode 4 == speed 6 plus cable */
295 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x20);
296 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x01);
298 } else if ((id
->dma_ultra
& 0x0008) && (udma_66
) && (udma_33
)) {
299 if (!((id
->dma_ultra
>> 8) & 8)) {
300 drive
->id
->dma_ultra
&= ~0xFF00;
301 drive
->id
->dma_ultra
|= 0x0808;
302 drive
->id
->dma_mword
&= ~0x0F00;
303 drive
->id
->dma_1word
&= ~0x0F00;
305 /* speed 7 == UDMA mode 3 == speed 5 plus cable */
306 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x40);
307 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x02);
309 } else if ((id
->dma_ultra
& 0x0004) && (udma_33
)) {
310 if (!((id
->dma_ultra
>> 8) & 4)) {
311 drive
->id
->dma_ultra
&= ~0x0F00;
312 drive
->id
->dma_ultra
|= 0x0404;
313 drive
->id
->dma_mword
&= ~0x0F00;
314 drive
->id
->dma_1word
&= ~0x0F00;
316 /* speed 6 == UDMA mode 2 */
317 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x20);
318 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x01);
320 } else if ((id
->dma_ultra
& 0x0002) && (udma_33
)) {
321 if (!((id
->dma_ultra
>> 8) & 2)) {
322 drive
->id
->dma_ultra
&= ~0x0F00;
323 drive
->id
->dma_ultra
|= 0x0202;
324 drive
->id
->dma_mword
&= ~0x0F00;
325 drive
->id
->dma_1word
&= ~0x0F00;
327 /* speed 5 == UDMA mode 1 */
328 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x40);
329 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x02);
331 } else if ((id
->dma_ultra
& 0x0001) && (udma_33
)) {
332 if (!((id
->dma_ultra
>> 8) & 1)) {
333 drive
->id
->dma_ultra
&= ~0x0F00;
334 drive
->id
->dma_ultra
|= 0x0101;
335 drive
->id
->dma_mword
&= ~0x0F00;
336 drive
->id
->dma_1word
&= ~0x0F00;
338 /* speed 4 == UDMA mode 0 */
339 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x60);
340 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x03);
342 } else if (id
->dma_mword
& 0x0004) {
343 if (!((id
->dma_mword
>> 8) & 4)) {
344 drive
->id
->dma_mword
&= ~0x0F00;
345 drive
->id
->dma_mword
|= 0x0404;
346 drive
->id
->dma_1word
&= ~0x0F00;
348 /* speed 4 == DMA mode 2 multi-word */
349 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x60);
350 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x03);
351 speed
= XFER_MW_DMA_2
;
352 } else if (id
->dma_mword
& 0x0002) {
353 if (!((id
->dma_mword
>> 8) & 2)) {
354 drive
->id
->dma_mword
&= ~0x0F00;
355 drive
->id
->dma_mword
|= 0x0202;
356 drive
->id
->dma_1word
&= ~0x0F00;
358 /* speed 3 == DMA mode 1 multi-word */
359 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x60);
360 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x04);
361 speed
= XFER_MW_DMA_1
;
362 } else if (id
->dma_mword
& 0x0001) {
363 if (!((id
->dma_mword
>> 8) & 1)) {
364 drive
->id
->dma_mword
&= ~0x0F00;
365 drive
->id
->dma_mword
|= 0x0101;
366 drive
->id
->dma_1word
&= ~0x0F00;
368 /* speed 2 == DMA mode 0 multi-word */
369 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x60);
370 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x05);
371 speed
= XFER_MW_DMA_0
;
372 } else if (id
->dma_1word
& 0x0004) {
373 if (!((id
->dma_1word
>> 8) & 4)) {
374 drive
->id
->dma_mword
&= ~0x0F00;
375 drive
->id
->dma_1word
&= ~0x0F00;
376 drive
->id
->dma_1word
|= 0x0404;
378 /* speed 2 == DMA mode 2 single-word */
379 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x60);
380 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x05);
381 speed
= XFER_SW_DMA_2
;
382 } else if (id
->dma_1word
& 0x0002) {
383 if (!((id
->dma_1word
>> 8) & 2)) {
384 drive
->id
->dma_mword
&= ~0x0F00;
385 drive
->id
->dma_1word
&= ~0x0F00;
386 drive
->id
->dma_1word
|= 0x0202;
388 /* speed 1 == DMA mode 1 single-word */
389 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0x80);
390 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x06);
391 speed
= XFER_SW_DMA_1
;
392 } else if (id
->dma_1word
& 0x0001) {
393 if (!((id
->dma_1word
>> 8) & 1)) {
394 drive
->id
->dma_mword
&= ~0x0F00;
395 drive
->id
->dma_1word
&= ~0x0F00;
396 drive
->id
->dma_1word
|= 0x0101;
398 /* speed 0 == DMA mode 0 single-word */
399 pci_write_config_byte(dev
, (drive_pci
)|0x01, BP
|0xC0);
400 pci_write_config_byte(dev
, (drive_pci
)|0x02, CP
|0x0B);
401 speed
= XFER_SW_DMA_0
;
403 /* restore original pci-config space */
404 pci_write_config_dword(dev
, drive_pci
, drive_conf
);
405 return ide_dma_off_quietly
;
408 err
= ide_config_drive_speed(drive
, speed
);
410 #if PDC202XX_DECODE_REGISTER_INFO
411 pci_read_config_byte(dev
, (drive_pci
), &AP
);
412 pci_read_config_byte(dev
, (drive_pci
)|0x01, &BP
);
413 pci_read_config_byte(dev
, (drive_pci
)|0x02, &CP
);
415 decode_registers(REG_A
, AP
);
416 decode_registers(REG_B
, BP
);
417 decode_registers(REG_C
, CP
);
418 decode_registers(REG_D
, DP
);
419 #endif /* PDC202XX_DECODE_REGISTER_INFO */
421 #if PDC202XX_DEBUG_DRIVE_INFO
422 printk("%s: %s drive%d 0x%08x ",
423 drive
->name
, ide_xfer_verbose(speed
),
424 drive_number
, drive_conf
);
425 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
426 printk("0x%08x\n", drive_conf
);
427 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
429 return ((int) ((id
->dma_ultra
>> 11) & 3) ? ide_dma_on
:
430 ((id
->dma_ultra
>> 8) & 7) ? ide_dma_on
:
431 ((id
->dma_mword
>> 8) & 7) ? ide_dma_on
:
432 ((id
->dma_1word
>> 8) & 7) ? ide_dma_on
:
433 ide_dma_off_quietly
);
437 * 960, 480, 390, 300, 240, 180, 120, 90, 60
438 * 180, 150, 120, 90, 60
440 * 180, 120, 90, 90, 90, 60, 30
441 * 11, 5, 4, 3, 2, 1, 0
444 static int config_drive_xfer_rate (ide_drive_t
*drive
)
446 struct hd_driveid
*id
= drive
->id
;
447 ide_hwif_t
*hwif
= HWIF(drive
);
448 ide_dma_action_t dma_func
= ide_dma_off_quietly
;
450 if (id
&& (id
->capability
& 1) && hwif
->autodma
) {
451 /* Consult the list of known "bad" drives */
452 if (ide_dmaproc(ide_dma_bad_drive
, drive
)) {
453 return HWIF(drive
)->dmaproc(ide_dma_off
, drive
);
456 if (id
->field_valid
& 4) {
457 if (id
->dma_ultra
& 0x001F) {
458 /* Force if Capable UltraDMA */
459 dma_func
= config_chipset_for_dma(drive
, 1);
460 if ((id
->field_valid
& 2) &&
461 (dma_func
!= ide_dma_on
))
464 } else if (id
->field_valid
& 2) {
466 if ((id
->dma_mword
& 0x0004) ||
467 (id
->dma_1word
& 0x0004)) {
468 /* Force if Capable regular DMA modes */
469 dma_func
= config_chipset_for_dma(drive
, 0);
471 } else if ((ide_dmaproc(ide_dma_good_drive
, drive
)) &&
472 (id
->eide_dma_time
> 150)) {
473 /* Consult the list of known "good" drives */
474 dma_func
= config_chipset_for_dma(drive
, 0);
477 return HWIF(drive
)->dmaproc(dma_func
, drive
);
481 * pdc202xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
483 int pdc202xx_dmaproc (ide_dma_action_t func
, ide_drive_t
*drive
)
487 return config_drive_xfer_rate(drive
);
491 return ide_dmaproc(func
, drive
); /* use standard DMA stuff */
494 __initfunc(unsigned int pci_init_pdc202xx (struct pci_dev
*dev
, const char *name
))
496 unsigned long high_16
= dev
->base_address
[4] & PCI_BASE_ADDRESS_IO_MASK
;
497 byte udma_speed_flag
= inb(high_16
+ 0x001f);
498 byte primary_mode
= inb(high_16
+ 0x001a);
499 byte secondary_mode
= inb(high_16
+ 0x001b);
501 if (dev
->rom_address
) {
502 pci_write_config_dword(dev
, PCI_ROM_ADDRESS
, dev
->rom_address
| PCI_ROM_ADDRESS_ENABLE
);
503 printk("%s: ROM enabled at 0x%08lx\n", name
, dev
->rom_address
);
506 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
) {
507 byte irq
= 0, irq2
= 0;
508 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
509 pci_read_config_byte(dev
, (PCI_INTERRUPT_LINE
)|0x80, &irq2
); /* 0xbc */
511 pci_write_config_byte(dev
, (PCI_INTERRUPT_LINE
)|0x80, irq
); /* 0xbc */
512 printk("%s: pci-config space interrupt mirror fixed.\n", name
);
516 printk("%s: (U)DMA Burst Bit %sABLED " \
518 "Secondary %s Mode.\n",
520 (udma_speed_flag
& 1) ? "EN" : "DIS",
521 (primary_mode
& 1) ? "MASTER" : "PCI",
522 (secondary_mode
& 1) ? "MASTER" : "PCI" );
524 #ifdef PDC202XX_FORCE_BURST_BIT
525 if (!(udma_speed_flag
& 1)) {
526 printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", name
, udma_speed_flag
, (udma_speed_flag
|1));
527 outb(udma_speed_flag
|1, high_16
+ 0x001f);
528 printk("%sCTIVE\n", (inb(high_16
+ 0x001f) & 1) ? "A" : "INA");
530 #endif /* PDC202XX_FORCE_BURST_BIT */
532 #ifdef PDC202XX_FORCE_MASTER_MODE
533 if (!(primary_mode
& 1)) {
534 printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
535 name
, primary_mode
, (primary_mode
|1));
536 outb(primary_mode
|1, high_16
+ 0x001a);
537 printk("%s\n", (inb(high_16
+ 0x001a) & 1) ? "MASTER" : "PCI");
540 if (!(secondary_mode
& 1)) {
541 printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
542 name
, secondary_mode
, (secondary_mode
|1));
543 outb(secondary_mode
|1, high_16
+ 0x001b);
544 printk("%s\n", (inb(high_16
+ 0x001b) & 1) ? "MASTER" : "PCI");
546 #endif /* PDC202XX_FORCE_MASTER_MODE */
550 __initfunc(void ide_init_pdc202xx (ide_hwif_t
*hwif
))
552 if (hwif
->dma_base
) {
553 hwif
->dmaproc
= &pdc202xx_dmaproc
;