include/linux/serial_reg.h

   1 /*
   2  * include/linux/serial_reg.h
   3  *
   4  * Copyright (C) 1992, 1994 by Theodore Ts'o.
   5  *
   6  * Redistribution of this file is permitted under the terms of the GNU
   7  * Public License (GPL)
   8  *
   9  * These are the UART port assignments, expressed as offsets from the base
  10  * register.  These assignments should hold for any serial port based on
  11  * a 8250, 16450, or 16550(A).
  12  */
  13
  14 #ifndef _LINUX_SERIAL_REG_H
  15 #define _LINUX_SERIAL_REG_H
  16
  17 #define UART_RX         0       /* In:  Receive buffer (DLAB=0) */
  18 #define UART_TX         0       /* Out: Transmit buffer (DLAB=0) */
  19 #define UART_DLL        0       /* Out: Divisor Latch Low (DLAB=1) */
  20 #define UART_TRG        0       /* (LCR=BF) FCTR bit 7 selects Rx or Tx
  21                                  * In: Fifo count
  22                                  * Out: Fifo custom trigger levels
  23                                  * XR16C85x only */
  24
  25 #define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
  26 #define UART_IER        1       /* Out: Interrupt Enable Register */
  27 #define UART_FCTR       1       /* (LCR=BF) Feature Control Register
  28                                  * XR16C85x only */
  29
  30 #define UART_IIR        2       /* In:  Interrupt ID Register */
  31 #define UART_FCR        2       /* Out: FIFO Control Register */
  32 #define UART_EFR        2       /* I/O: Extended Features Register */
  33                                 /* (DLAB=1, 16C660 only) */
  34
  35 #define UART_LCR        3       /* Out: Line Control Register */
  36 #define UART_MCR        4       /* Out: Modem Control Register */
  37 #define UART_LSR        5       /* In:  Line Status Register */
  38 #define UART_MSR        6       /* In:  Modem Status Register */
  39 #define UART_SCR        7       /* I/O: Scratch Register */
  40 #define UART_EMSR       7       /* (LCR=BF) Extended Mode Select Register
  41                                  * FCTR bit 6 selects SCR or EMSR
  42                                  * XR16c85x only */
  43
  44 /*
  45  * These are the definitions for the FIFO Control Register
  46  * (16650 only)
  47  */
  48 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
  49 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
  50 #define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
  51 #define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
  52 #define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
  53 #define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
  54 #define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
  55 #define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
  56 #define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
  57 /* 16650 redefinitions */
  58 #define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
  59 #define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
  60 #define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
  61 #define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
  62 #define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
  63 #define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
  64 #define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
  65 #define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
  66 /* TI 16750 definitions */
  67 #define UART_FCR7_64BYTE        0x20 /* Go into 64 byte mode */
  68
  69 /*
  70  * These are the definitions for the Line Control Register
  71  *
  72  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  73  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  74  */
  75 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  76 #define UART_LCR_SBC    0x40    /* Set break control */
  77 #define UART_LCR_SPAR   0x20    /* Stick parity (?) */
  78 #define UART_LCR_EPAR   0x10    /* Even parity select */
  79 #define UART_LCR_PARITY 0x08    /* Parity Enable */
  80 #define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
  81 #define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
  82 #define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
  83 #define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
  84 #define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
  85
  86 /*
  87  * These are the definitions for the Line Status Register
  88  */
  89 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  90 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  91 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  92 #define UART_LSR_FE     0x08    /* Frame error indicator */
  93 #define UART_LSR_PE     0x04    /* Parity error indicator */
  94 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  95 #define UART_LSR_DR     0x01    /* Receiver data ready */
  96
  97 /*
  98  * These are the definitions for the Interrupt Identification Register
  99  */
 100 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
 101 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
 102
 103 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
 104 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
 105 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
 106 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
 107
 108 /*
 109  * These are the definitions for the Interrupt Enable Register
 110  */
 111 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
 112 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
 113 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
 114 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
 115 /*
 116  * Sleep mode for ST16650 and TI16750.
 117  * Note that for 16650, EFR-bit 4 must be selected as well.
 118  */
 119 #define UART_IERX_SLEEP  0x10   /* Enable sleep mode */
 120
 121 /*
 122  * These are the definitions for the Modem Control Register
 123  */
 124 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
 125 #define UART_MCR_OUT2   0x08    /* Out2 complement */
 126 #define UART_MCR_OUT1   0x04    /* Out1 complement */
 127 #define UART_MCR_RTS    0x02    /* RTS complement */
 128 #define UART_MCR_DTR    0x01    /* DTR complement */
 129
 130 /*
 131  * These are the definitions for the Modem Status Register
 132  */
 133 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
 134 #define UART_MSR_RI     0x40    /* Ring Indicator */
 135 #define UART_MSR_DSR    0x20    /* Data Set Ready */
 136 #define UART_MSR_CTS    0x10    /* Clear to Send */
 137 #define UART_MSR_DDCD   0x08    /* Delta DCD */
 138 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
 139 #define UART_MSR_DDSR   0x02    /* Delta DSR */
 140 #define UART_MSR_DCTS   0x01    /* Delta CTS */
 141 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
 142
 143 /*
 144  * These are the definitions for the Extended Features Register
 145  * (StarTech 16C660 only, when DLAB=1)
 146  */
 147 #define UART_EFR_CTS    0x80    /* CTS flow control */
 148 #define UART_EFR_RTS    0x40    /* RTS flow control */
 149 #define UART_EFR_SCD    0x20    /* Special character detect */
 150 #define UART_EFR_ECB    0x10    /* Enhanced control bit */
 151 /*
 152  * the low four bits control software flow control
 153  */
 154
 155 /*
 156  * These register definitions are for the 16C950
 157  */
 158 #define UART_ASR        0x01    /* Additional Status Register */
 159 #define UART_RFL        0x03    /* Transmitter FIFO level */
 160 #define UART_TFL        0x04    /* Receiver FIFO level */
 161 #define UART_ICR        0x05    /* Index Control Register */
 162
 163 /* The 16950 ICR registers */
 164 #define UART_ACR        0x00    /* Additional Control Register */
 165 #define UART_CPR        0x01    /* Clock Prescalar Register */
 166 #define UART_TCR        0x02    /* Times Clock Register */
 167 #define UART_CKS        0x03    /* Clock Select Register */
 168 #define UART_TTL        0x04    /* Transmitter Interrupt Trigger Level */
 169 #define UART_RTL        0x05    /* Receiver Interrupt Trigger Level */
 170 #define UART_FCL        0x06    /* Flow Control Level Lower */
 171 #define UART_FCH        0x07    /* Flow Control Level Higher */
 172 #define UART_ID1        0x08    /* ID #1 */
 173 #define UART_ID2        0x09    /* ID #2 */
 174 #define UART_ID3        0x0A    /* ID #3 */
 175 #define UART_REV        0x0B    /* Revision */
 176 #define UART_CSR        0x0C    /* Channel Software Reset */
 177 #define UART_NMR        0x0D    /* Nine-bit Mode Register */
 178 #define UART_CTR        0xFF
 179
 180 /*
 181  * The 16C950 Additional Control Reigster
 182  */
 183 #define UART_ACR_RXDIS  0x01    /* Receiver disable */
 184 #define UART_ACR_TXDIS  0x02    /* Receiver disable */
 185 #define UART_ACR_DSRFC  0x04    /* DSR Flow Control */
 186 #define UART_ACR_TLENB  0x20    /* 950 trigger levels enable */
 187 #define UART_ACR_ICRRD  0x40    /* ICR Read enable */
 188 #define UART_ACR_ASREN  0x80    /* Additional status enable */
 189
 190 /*
 191  * These are the definitions for the Feature Control Register
 192  * (XR16C85x only, when LCR=bf; doubles with the Interrupt Enable
 193  * Register, UART register #1)
 194  */
 195 #define UART_FCTR_RTS_NODELAY   0x00  /* RTS flow control delay */
 196 #define UART_FCTR_RTS_4DELAY    0x01
 197 #define UART_FCTR_RTS_6DELAY    0x02
 198 #define UART_FCTR_RTS_8DELAY    0x03
 199 #define UART_FCTR_IRDA  0x04  /* IrDa data encode select */
 200 #define UART_FCTR_TX_INT        0x08  /* Tx interrupt type select */
 201 #define UART_FCTR_TRGA  0x00  /* Tx/Rx 550 trigger table select */
 202 #define UART_FCTR_TRGB  0x10  /* Tx/Rx 650 trigger table select */
 203 #define UART_FCTR_TRGC  0x20  /* Tx/Rx 654 trigger table select */
 204 #define UART_FCTR_TRGD  0x30  /* Tx/Rx 850 programmable trigger select */
 205 #define UART_FCTR_SCR_SWAP      0x40  /* Scratch pad register swap */
 206 #define UART_FCTR_RX    0x00  /* Programmable trigger mode select */
 207 #define UART_FCTR_TX    0x80  /* Programmable trigger mode select */
 208
 209 /*
 210  * These are the definitions for the Enhanced Mode Select Register
 211  * (XR16C85x only, when LCR=bf and FCTR bit 6=1; doubles with the
 212  * Scratch register, UART register #7)
 213  */
 214 #define UART_EMSR_FIFO_COUNT    0x01  /* Rx/Tx select */
 215 #define UART_EMSR_ALT_COUNT     0x02  /* Alternating count select */
 216
 217 /*
 218  * These are the definitions for the Programmable Trigger
 219  * Register (XR16C85x only, when LCR=bf; doubles with the UART RX/TX
 220  * register, UART register #0)
 221  */
 222 #define UART_TRG_1      0x01
 223 #define UART_TRG_4      0x04
 224 #define UART_TRG_8      0x08
 225 #define UART_TRG_16     0x10
 226 #define UART_TRG_32     0x20
 227 #define UART_TRG_64     0x40
 228 #define UART_TRG_96     0x60
 229 #define UART_TRG_120    0x78
 230 #define UART_TRG_128    0x80
 231
 232 /*
 233  * These definitions are for the RSA-DV II/S card, from
 234  *
 235  * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
 236  */
 237
 238 #define UART_RSA_BASE (-8)
 239
 240 #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
 241
 242 #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
 243 #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
 244 #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
 245 #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
 246
 247 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
 248
 249 #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
 250 #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
 251 #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
 252 #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
 253 #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
 254
 255 #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
 256
 257 #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
 258 #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
 259 #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
 260 #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
 261 #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
 262 #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
 263 #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occured (1) */
 264 #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occured */
 265
 266 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
 267
 268 #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
 269
 270 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
 271
 272 #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
 273
 274 /*
 275  * The RSA DSV/II board has two fixed clock frequencies.  One is the
 276  * standard rate, and the other is 8 times faster.
 277  */
 278 #define SERIAL_RSA_BAUD_BASE (921600)
 279 #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
 280
 281 #endif /* _LINUX_SERIAL_REG_H */
 282