drivers/scsi/tmscsim.h

   1 /***********************************************************************
   2 ;*      File Name : TMSCSIM.H                                          *
   3 ;*                  TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter  *
   4 ;*                  Device Driver                                      *
   5 ;***********************************************************************/
   6 /* $Id: tmscsim.h,v 2.4 1998/12/25 17:33:27 garloff Exp $ */
   7
   8 #ifndef _TMSCSIM_H
   9 #define _TMSCSIM_H
  10
  11 #include <linux/config.h>
  12
  13 #define IRQ_NONE 255
  14
  15 #define MAX_ADAPTER_NUM         4
  16 #define MAX_SG_LIST_BUF         16
  17 #define MAX_CMD_PER_LUN         8
  18 #define MAX_CMD_QUEUE           2*MAX_CMD_PER_LUN+1
  19 #define MAX_SCSI_ID             8
  20 #define MAX_SRB_CNT             MAX_CMD_QUEUE+1 /* Max number of started commands */
  21 #define END_SCAN                2
  22
  23 #define SEL_TIMEOUT             153     /* 250 ms selection timeout (@ 40 MHz) */
  24
  25 typedef unsigned char   UCHAR;
  26 typedef unsigned short  USHORT;
  27 typedef unsigned long   ULONG;
  28 typedef unsigned int    UINT;
  29
  30 typedef UCHAR           *PUCHAR;
  31 typedef USHORT          *PUSHORT;
  32 typedef ULONG           *PULONG;
  33 typedef Scsi_Host_Template  *PSHT;
  34 typedef struct Scsi_Host    *PSH;
  35 typedef Scsi_Device     *PSCSIDEV;
  36 typedef Scsi_Cmnd       *PSCSICMD;
  37 typedef void            *PVOID;
  38 typedef struct scatterlist  *PSGL, SGL;
  39
  40
  41 /*;-----------------------------------------------------------------------*/
  42 typedef  struct  _SyncMsg
  43 {
  44 UCHAR           ExtendMsg;
  45 UCHAR           ExtMsgLen;
  46 UCHAR           SyncXferReq;
  47 UCHAR           Period;
  48 UCHAR           ReqOffset;
  49 } SyncMsg;
  50 /*;-----------------------------------------------------------------------*/
  51 typedef  struct  _Capacity
  52 {
  53 ULONG           BlockCount;
  54 ULONG           BlockLength;
  55 } Capacity;
  56 /*;-----------------------------------------------------------------------*/
  57 typedef  struct  _SGentry
  58 {
  59 ULONG           SGXferDataPtr;
  60 ULONG           SGXferDataLen;
  61 } SGentry;
  62
  63 typedef  struct  _SGentry1
  64 {
  65 ULONG           SGXLen;
  66 ULONG           SGXPtr;
  67 } SGentry1, *PSGE;
  68
  69
  70 /*
  71 ;-----------------------------------------------------------------------
  72 ; SCSI Request Block
  73 ;-----------------------------------------------------------------------
  74 */
  75 struct  _SRB
  76 {
  77 UCHAR           CmdBlock[12];
  78
  79 struct _SRB     *pNextSRB;
  80 struct _DCB     *pSRBDCB;
  81 PSCSICMD        pcmd;
  82 PSGL            pSegmentList;
  83
  84 ULONG           Segment0[2];
  85 ULONG           Segment1[2];
  86
  87 /* 0x2c:*/
  88 ULONG           TotalXferredLen;
  89 ULONG           SGBusAddr;      /*;a segment starting address as seen by AM53C974A*/
  90 ULONG           SGToBeXferLen;  /*; to be xfer length */
  91 ULONG           SRBState;
  92
  93 /* 0x3c: */
  94 UCHAR           MsgInBuf[6];
  95 UCHAR           MsgOutBuf[6];
  96
  97 /* 0x48: */
  98 SGL             Segmentx;       /* make a one entry of S/G list table */
  99
 100 UCHAR           ScsiCmdLen;
 101 UCHAR           ScsiPhase;
 102
 103 UCHAR           AdaptStatus;
 104 UCHAR           TargetStatus;
 105
 106 /* 0x58: */
 107 UCHAR           MsgCnt;
 108 UCHAR           EndMessage;
 109 UCHAR           RetryCnt;
 110 UCHAR           SRBFlag;        /*; b0-AutoReqSense,b6-Read,b7-write */
 111                                 /*; b4-settimeout,b5-Residual valid */
 112 UCHAR           TagNumber;
 113 UCHAR           SGcount;
 114 UCHAR           SGIndex;
 115 UCHAR           SRBStatus;
 116   //UCHAR               IORBFlag;       /*;81h-Reset, 2-retry */
 117
 118 /* 0x60: */
 119 };
 120
 121
 122 typedef  struct  _SRB    DC390_SRB, *PSRB;
 123
 124 /*
 125 ;-----------------------------------------------------------------------
 126 ; Device Control Block
 127 ;-----------------------------------------------------------------------
 128 */
 129 struct  _DCB
 130 {
 131 struct _DCB     *pNextDCB;
 132 struct _ACB     *pDCBACB;
 133
 134 PSCSICMD        pQIORBhead;
 135 PSCSICMD        pQIORBtail;
 136 PSCSICMD        AboIORBhead;
 137 PSCSICMD        AboIORBtail;
 138 ULONG           QIORBCnt;
 139 ULONG           AboIORBcnt;
 140
 141 /* 0x20: */
 142 PSRB            pWaitingSRB;
 143 PSRB            pWaitLast;
 144 PSRB            pGoingSRB;
 145 PSRB            pGoingLast;
 146 PSRB            pActiveSRB;
 147 UCHAR           GoingSRBCnt;
 148 UCHAR           WaitSRBCnt;     /* ??? */
 149 UCHAR           DevType;
 150 UCHAR           MaxCommand;
 151
 152 /* 0x38: */
 153 ULONG           TagMask;
 154
 155 UCHAR           UnitSCSIID;     /*; SCSI Target ID  (SCSI Only) */
 156 UCHAR           UnitSCSILUN;    /*; SCSI Log.  Unit (SCSI Only) */
 157 UCHAR           DevMode;
 158 UCHAR           IdentifyMsg;
 159
 160 UCHAR           CtrlR1;
 161 UCHAR           CtrlR3;
 162 UCHAR           CtrlR4;
 163
 164 UCHAR           DCBFlag;
 165
 166 /* 0x44: */
 167 UCHAR           SyncMode;       /*; 0:async mode */
 168 UCHAR           NegoPeriod;     /*;for nego. */
 169 UCHAR           SyncPeriod;     /*;for reg. */
 170 UCHAR           SyncOffset;     /*;for reg. and nego.(low nibble) */
 171
 172 /* 0x48:*/
 173 //UCHAR         InqDataBuf[8];
 174 //UCHAR         CapacityBuf[8];
 175 /* 0x58: */
 176 };
 177
 178 typedef  struct  _DCB    DC390_DCB, *PDCB;
 179 /*
 180 ;-----------------------------------------------------------------------
 181 ; Adapter Control Block
 182 ;-----------------------------------------------------------------------
 183 */
 184 struct  _ACB
 185 {
 186 PSH             pScsiHost;
 187 struct _ACB     *pNextACB;
 188 USHORT          IOPortBase;
 189 UCHAR           IRQLevel;
 190 UCHAR           status;
 191
 192 UCHAR           SRBCount;
 193 UCHAR           AdapterIndex;   /*; nth Adapter this driver */
 194 UCHAR           DeviceCnt;
 195 UCHAR           DCBCnt;
 196
 197 /* 0x10: */
 198 UCHAR           TagMaxNum;
 199 UCHAR           ACBFlag;
 200 UCHAR           Gmode2;
 201 UCHAR           scan_devices;
 202
 203 PDCB            pLinkDCB;
 204 PDCB            pLastDCB;
 205 PDCB            pDCBRunRobin;
 206 PDCB            pActiveDCB;
 207 PSRB            pFreeSRB;
 208 PSRB            pTmpSRB;
 209
 210 /* 0x2c: */
 211
 212 UCHAR           msgin123[4];
 213 UCHAR           DCBmap[MAX_SCSI_ID];
 214
 215 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
 216 spinlock_t      lock;
 217 #endif
 218 UCHAR           sel_timeout;
 219 UCHAR           glitch_cfg;
 220
 221 UCHAR           MsgLen;
 222 UCHAR           Ignore_IRQ;     /* Not used */
 223
 224 PDEVDECL1;                      /* Pointer to PCI cfg. space */
 225 /* 0x40/0x3c: */
 226 ULONG           Cmds;
 227 ULONG           CmdInQ;
 228 ULONG           CmdOutOfSRB;
 229 ULONG           SelLost;
 230
 231
 232 /* 0x50/0x4c: */
 233 DC390_SRB       TmpSRB;
 234 /* 0xb4/0xb0: */
 235 DC390_SRB       SRB_array[MAX_SRB_CNT];         /* 18 SRBs */
 236 /* 0x7bc/0x7b8: */
 237 };
 238
 239 typedef  struct  _ACB    DC390_ACB, *PACB;
 240
 241 /*;-----------------------------------------------------------------------*/
 242
 243
 244 #define BIT31   0x80000000
 245 #define BIT30   0x40000000
 246 #define BIT29   0x20000000
 247 #define BIT28   0x10000000
 248 #define BIT27   0x08000000
 249 #define BIT26   0x04000000
 250 #define BIT25   0x02000000
 251 #define BIT24   0x01000000
 252 #define BIT23   0x00800000
 253 #define BIT22   0x00400000
 254 #define BIT21   0x00200000
 255 #define BIT20   0x00100000
 256 #define BIT19   0x00080000
 257 #define BIT18   0x00040000
 258 #define BIT17   0x00020000
 259 #define BIT16   0x00010000
 260 #define BIT15   0x00008000
 261 #define BIT14   0x00004000
 262 #define BIT13   0x00002000
 263 #define BIT12   0x00001000
 264 #define BIT11   0x00000800
 265 #define BIT10   0x00000400
 266 #define BIT9    0x00000200
 267 #define BIT8    0x00000100
 268 #define BIT7    0x00000080
 269 #define BIT6    0x00000040
 270 #define BIT5    0x00000020
 271 #define BIT4    0x00000010
 272 #define BIT3    0x00000008
 273 #define BIT2    0x00000004
 274 #define BIT1    0x00000002
 275 #define BIT0    0x00000001
 276
 277 /*;---UnitCtrlFlag */
 278 #define UNIT_ALLOCATED  BIT0
 279 #define UNIT_INFO_CHANGED BIT1
 280 #define FORMATING_MEDIA BIT2
 281 #define UNIT_RETRY      BIT3
 282
 283 /*;---UnitFlags */
 284 #define DASD_SUPPORT    BIT0
 285 #define SCSI_SUPPORT    BIT1
 286 #define ASPI_SUPPORT    BIT2
 287
 288 /*;----SRBState machine definition */
 289 #define SRB_FREE        0
 290 #define SRB_WAIT        BIT0
 291 #define SRB_READY       BIT1
 292 #define SRB_MSGOUT      BIT2    /*;arbitration+msg_out 1st byte*/
 293 #define SRB_MSGIN       BIT3
 294 #define SRB_MSGIN_MULTI BIT4
 295 #define SRB_COMMAND     BIT5
 296 #define SRB_START_      BIT6    /*;arbitration+msg_out+command_out*/
 297 #define SRB_DISCONNECT  BIT7
 298 #define SRB_DATA_XFER   BIT8
 299 #define SRB_XFERPAD     BIT9
 300 #define SRB_STATUS      BIT10
 301 #define SRB_COMPLETED   BIT11
 302 #define SRB_ABORT_SENT  BIT12
 303 #define DO_SYNC_NEGO    BIT13
 304 #define SRB_UNEXPECT_RESEL BIT14
 305
 306 /*;---SRBstatus */
 307 #define SRB_OK          BIT0
 308 #define ABORTION        BIT1
 309 #define OVER_RUN        BIT2
 310 #define UNDER_RUN       BIT3
 311 #define PARITY_ERROR    BIT4
 312 #define SRB_ERROR       BIT5
 313
 314 /*;---ACBFlag */
 315 #define RESET_DEV       BIT0
 316 #define RESET_DETECT    BIT1
 317 #define RESET_DONE      BIT2
 318
 319 /*;---DCBFlag */
 320 #define ABORT_DEV_      BIT0
 321
 322 /*;---SRBFlag */
 323 #define DATAOUT         BIT7
 324 #define DATAIN          BIT6
 325 #define RESIDUAL_VALID  BIT5
 326 #define ENABLE_TIMER    BIT4
 327 #define RESET_DEV0      BIT2
 328 #define ABORT_DEV       BIT1
 329 #define AUTO_REQSENSE   BIT0
 330
 331 /*;---Adapter status */
 332 #define H_STATUS_GOOD    0
 333 #define H_SEL_TIMEOUT    0x11
 334 #define H_OVER_UNDER_RUN 0x12
 335 #define H_UNEXP_BUS_FREE 0x13
 336 #define H_TARGET_PHASE_F 0x14
 337 #define H_INVALID_CCB_OP 0x16
 338 #define H_LINK_CCB_BAD   0x17
 339 #define H_BAD_TARGET_DIR 0x18
 340 #define H_DUPLICATE_CCB  0x19
 341 #define H_BAD_CCB_OR_SG  0x1A
 342 #define H_ABORT          0x0FF
 343
 344 /*; SCSI Status byte codes*/ /* Twice the values defined in scsi/scsi.h */
 345 #define SCSI_STAT_GOOD          0x0     /*;  Good status */
 346 #define SCSI_STAT_CHECKCOND     0x02    /*;  SCSI Check Condition */
 347 #define SCSI_STAT_CONDMET       0x04    /*;  Condition Met */
 348 #define SCSI_STAT_BUSY          0x08    /*;  Target busy status */
 349 #define SCSI_STAT_INTER         0x10    /*;  Intermediate status */
 350 #define SCSI_STAT_INTERCONDMET  0x14    /*;  Intermediate condition met */
 351 #define SCSI_STAT_RESCONFLICT   0x18    /*;  Reservation conflict */
 352 #define SCSI_STAT_CMDTERM       0x22    /*;  Command Terminated */
 353 #define SCSI_STAT_QUEUEFULL     0x28    /*;  Queue Full */
 354
 355 #define SCSI_STAT_UNEXP_BUS_F   0xFD    /*;  Unexpect Bus Free */
 356 #define SCSI_STAT_BUS_RST_DETECT 0xFE   /*;  Scsi Bus Reset detected */
 357 #define SCSI_STAT_SEL_TIMEOUT   0xFF    /*;  Selection Time out */
 358
 359 /*;---Sync_Mode */
 360 #define SYNC_DISABLE    0
 361 #define SYNC_ENABLE     BIT0
 362 #define SYNC_NEGO_DONE  BIT1
 363 #define WIDE_ENABLE     BIT2    /* Not used ;-) */
 364 #define WIDE_NEGO_DONE  BIT3    /* Not used ;-) */
 365 #define EN_TAG_QUEUEING BIT4
 366 #define EN_ATN_STOP     BIT5
 367
 368 #define SYNC_NEGO_OFFSET 15
 369
 370 /*;---SCSI bus phase*/
 371 #define SCSI_DATA_OUT   0
 372 #define SCSI_DATA_IN    1
 373 #define SCSI_COMMAND    2
 374 #define SCSI_STATUS_    3
 375 #define SCSI_NOP0       4
 376 #define SCSI_NOP1       5
 377 #define SCSI_MSG_OUT    6
 378 #define SCSI_MSG_IN     7
 379
 380 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */
 381 #define MSG_COMPLETE            0x00
 382 #define MSG_EXTENDED            0x01
 383 #define MSG_SAVE_PTR            0x02
 384 #define MSG_RESTORE_PTR         0x03
 385 #define MSG_DISCONNECT          0x04
 386 #define MSG_INITIATOR_ERROR     0x05
 387 #define MSG_ABORT               0x06
 388 #define MSG_REJECT_             0x07
 389 #define MSG_NOP                 0x08
 390 #define MSG_PARITY_ERROR        0x09
 391 #define MSG_LINK_CMD_COMPL      0x0A
 392 #define MSG_LINK_CMD_COMPL_FLG  0x0B
 393 #define MSG_BUS_RESET           0x0C
 394 #define MSG_ABORT_TAG           0x0D
 395 #define MSG_SIMPLE_QTAG         0x20
 396 #define MSG_HEAD_QTAG           0x21
 397 #define MSG_ORDER_QTAG          0x22
 398 #define MSG_IDENTIFY            0x80
 399 #define MSG_HOST_ID             0x0C0
 400
 401 /* cmd->result */
 402 #define STATUS_MASK_            0xFF
 403 #define MSG_MASK                0xFF00
 404 #define RETURN_MASK             0xFF0000
 405
 406 /*
 407 **  Inquiry Data format
 408 */
 409
 410 typedef struct  _SCSIInqData { /* INQUIRY */
 411
 412         UCHAR    DevType;               /* Periph Qualifier & Periph Dev Type*/
 413         UCHAR    RMB_TypeMod;           /* rem media bit & Dev Type Modifier */
 414         UCHAR    Vers;                  /* ISO, ECMA, & ANSI versions        */
 415         UCHAR    RDF;                   /* AEN, TRMIOP, & response data format*/
 416         UCHAR    AddLen;                /* length of additional data         */
 417         UCHAR    Res1;                  /* reserved                          */
 418         UCHAR    Res2;                  /* reserved                          */
 419         UCHAR    Flags;                 /* RelADr,Wbus32,Wbus16,Sync,etc.    */
 420         UCHAR    VendorID[8];           /* Vendor Identification             */
 421         UCHAR    ProductID[16];         /* Product Identification            */
 422         UCHAR    ProductRev[4];         /* Product Revision                  */
 423
 424
 425 } SCSI_INQDATA, *PSCSI_INQDATA;
 426
 427
 428 /*  Inquiry byte 0 masks */
 429
 430
 431 #define SCSI_DEVTYPE        0x1F      /* Peripheral Device Type             */
 432 #define SCSI_PERIPHQUAL     0xE0      /* Peripheral Qualifier               */
 433 #define TYPE_NODEV          SCSI_DEVTYPE    /* Unknown or no device type    */
 434
 435
 436 /*  Inquiry byte 1 mask */
 437
 438 #define SCSI_REMOVABLE_MEDIA  0x80    /* Removable Media bit (1=removable)  */
 439
 440
 441 /*  Peripheral Device Type definitions */
 442 /*  see include/scsi/scsi.h for the rest */
 443
 444 #define TYPE_PRINTER             0x02      /* Printer device               */
 445
 446 /*
 447 ** Inquiry flag definitions (Inq data byte 7)
 448 */
 449
 450 #define SCSI_INQ_RELADR       0x80    /* device supports relative addressing*/
 451 #define SCSI_INQ_WBUS32       0x40    /* device supports 32 bit data xfers  */
 452 #define SCSI_INQ_WBUS16       0x20    /* device supports 16 bit data xfers  */
 453 #define SCSI_INQ_SYNC         0x10    /* device supports synchronous xfer   */
 454 #define SCSI_INQ_LINKED       0x08    /* device supports linked commands    */
 455 #define SCSI_INQ_CMDQUEUE     0x02    /* device supports command queueing   */
 456 #define SCSI_INQ_SFTRE        0x01    /* device supports soft resets */
 457
 458
 459 /*
 460 ;==========================================================
 461 ; EEPROM byte offset
 462 ;==========================================================
 463 */
 464 typedef  struct  _EEprom
 465 {
 466 UCHAR   EE_MODE1;
 467 UCHAR   EE_SPEED;
 468 UCHAR   xx1;
 469 UCHAR   xx2;
 470 } EEprom, *PEEprom;
 471
 472 #define REAL_EE_ADAPT_SCSI_ID 64
 473 #define REAL_EE_MODE2   65
 474 #define REAL_EE_DELAY   66
 475 #define REAL_EE_TAG_CMD_NUM     67
 476
 477 #define EE_ADAPT_SCSI_ID 32
 478 #define EE_MODE2        33
 479 #define EE_DELAY        34
 480 #define EE_TAG_CMD_NUM  35
 481
 482 #define EE_LEN          40
 483
 484 /*; EE_MODE1 bits definition*/
 485 #define PARITY_CHK_     BIT0
 486 #define SYNC_NEGO_      BIT1
 487 #define EN_DISCONNECT_  BIT2
 488 #define SEND_START_     BIT3
 489 #define TAG_QUEUEING_   BIT4
 490
 491 /*; EE_MODE2 bits definition*/
 492 #define MORE2_DRV       BIT0
 493 #define GREATER_1G      BIT1
 494 #define RST_SCSI_BUS    BIT2
 495 #define ACTIVE_NEGATION BIT3
 496 #define NO_SEEK         BIT4
 497 #define LUN_CHECK       BIT5
 498
 499 #define ENABLE_CE       1
 500 #define DISABLE_CE      0
 501 #define EEPROM_READ     0x80
 502
 503 /*
 504 ;==========================================================
 505 ;       AMD 53C974 Registers bit Definition
 506 ;==========================================================
 507 */
 508 /*
 509 ;====================
 510 ; SCSI Register
 511 ;====================
 512 */
 513
 514 /*; Command Reg.(+0CH) (rw) */
 515 #define DMA_COMMAND             BIT7
 516 #define NOP_CMD                 0
 517 #define CLEAR_FIFO_CMD          1
 518 #define RST_DEVICE_CMD          2
 519 #define RST_SCSI_BUS_CMD        3
 520
 521 #define INFO_XFER_CMD           0x10
 522 #define INITIATOR_CMD_CMPLTE    0x11
 523 #define MSG_ACCEPTED_CMD        0x12
 524 #define XFER_PAD_BYTE           0x18
 525 #define SET_ATN_CMD             0x1A
 526 #define RESET_ATN_CMD           0x1B
 527
 528 #define SEL_WO_ATN              0x41    /* currently not used */
 529 #define SEL_W_ATN               0x42
 530 #define SEL_W_ATN_STOP          0x43
 531 #define SEL_W_ATN3              0x46
 532 #define EN_SEL_RESEL            0x44
 533 #define DIS_SEL_RESEL           0x45    /* currently not used */
 534 #define RESEL                   0x40    /* " */
 535 #define RESEL_ATN3              0x47    /* " */
 536
 537 #define DATA_XFER_CMD           INFO_XFER_CMD
 538
 539
 540 /*; SCSI Status Reg.(+10H) (r) */
 541 #define INTERRUPT               BIT7
 542 #define ILLEGAL_OP_ERR          BIT6
 543 #define PARITY_ERR              BIT5
 544 #define COUNT_2_ZERO            BIT4
 545 #define GROUP_CODE_VALID        BIT3
 546 #define SCSI_PHASE_MASK         (BIT2+BIT1+BIT0)
 547 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
 548
 549 /*; Interrupt Status Reg.(+14H) (r) */
 550 #define SCSI_RESET              BIT7
 551 #define INVALID_CMD             BIT6
 552 #define DISCONNECTED            BIT5
 553 #define SERVICE_REQUEST         BIT4
 554 #define SUCCESSFUL_OP           BIT3
 555 #define RESELECTED              BIT2
 556 #define SEL_ATTENTION           BIT1
 557 #define SELECTED                BIT0
 558
 559 /*; Internal State Reg.(+18H) (r) */
 560 #define SYNC_OFFSET_FLAG        BIT3
 561 #define INTRN_STATE_MASK        (BIT2+BIT1+BIT0)
 562 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
 563
 564 /*; Clock Factor Reg.(+24H) (w) */
 565 #define CLK_FREQ_40MHZ          0
 566 #define CLK_FREQ_35MHZ          (BIT2+BIT1+BIT0)
 567 #define CLK_FREQ_30MHZ          (BIT2+BIT1)
 568 #define CLK_FREQ_25MHZ          (BIT2+BIT0)
 569 #define CLK_FREQ_20MHZ          BIT2
 570 #define CLK_FREQ_15MHZ          (BIT1+BIT0)
 571 #define CLK_FREQ_10MHZ          BIT1
 572
 573 /*; Control Reg. 1(+20H) (rw) */
 574 #define EXTENDED_TIMING         BIT7
 575 #define DIS_INT_ON_SCSI_RST     BIT6
 576 #define PARITY_ERR_REPO         BIT4
 577 #define SCSI_ID_ON_BUS          (BIT2+BIT1+BIT0) /* host adapter ID */
 578
 579 /*; Control Reg. 2(+2CH) (rw) */
 580 #define EN_FEATURE              BIT6
 581 #define EN_SCSI2_CMD            BIT3
 582
 583 /*; Control Reg. 3(+30H) (rw) */
 584 #define ID_MSG_CHECK            BIT7
 585 #define EN_QTAG_MSG             BIT6
 586 #define EN_GRP2_CMD             BIT5
 587 #define FAST_SCSI               BIT4    /* ;10MB/SEC */
 588 #define FAST_CLK                BIT3    /* ;25 - 40 MHZ */
 589
 590 /*; Control Reg. 4(+34H) (rw) */
 591 #define EATER_12NS              0
 592 #define EATER_25NS              BIT7
 593 #define EATER_35NS              BIT6
 594 #define EATER_0NS               (BIT7+BIT6)
 595 #define REDUCED_POWER           BIT5
 596 #define CTRL4_RESERVED          BIT4    /* must be 1 acc. to AM53C974.c */
 597 #define NEGATE_REQACKDATA       BIT2
 598 #define NEGATE_REQACK           BIT3
 599
 600 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
 601 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
 602
 603 /*
 604 ;====================
 605 ; DMA Register
 606 ;====================
 607 */
 608 /*; DMA Command Reg.(+40H) (rw) */
 609 #define READ_DIRECTION          BIT7
 610 #define WRITE_DIRECTION         0
 611 #define EN_DMA_INT              BIT6
 612 #define EN_PAGE_INT             BIT5    /* page transfer interrupt enable */
 613 #define MAP_TO_MDL              BIT4
 614 #define DIAGNOSTIC              BIT2
 615 #define DMA_IDLE_CMD            0
 616 #define DMA_BLAST_CMD           BIT0
 617 #define DMA_ABORT_CMD           BIT1
 618 #define DMA_START_CMD           (BIT1+BIT0)
 619
 620 /*; DMA Status Reg.(+54H) (r) */
 621 #define PCI_MS_ABORT            BIT6
 622 #define BLAST_COMPLETE          BIT5
 623 #define SCSI_INTERRUPT          BIT4
 624 #define DMA_XFER_DONE           BIT3
 625 #define DMA_XFER_ABORT          BIT2
 626 #define DMA_XFER_ERROR          BIT1
 627 #define POWER_DOWN              BIT0
 628
 629 /*; DMA SCSI Bus and Ctrl.(+70H) */
 630 #define EN_INT_ON_PCI_ABORT     BIT25
 631 #define WRT_ERASE_DMA_STAT      BIT24
 632 #define PW_DOWN_CTRL            BIT21
 633 #define SCSI_BUSY               BIT20
 634 #define SCLK                    BIT19
 635 #define SCAM                    BIT18
 636 #define SCSI_LINES              0x0003ffff
 637
 638 /*
 639 ;==========================================================
 640 ; SCSI Chip register address offset
 641 ;==========================================================
 642 ;Registers are rw unless declared otherwise
 643 */
 644 #define CtcReg_Low      0x00    /* r    curr. transfer count */
 645 #define CtcReg_Mid      0x04    /* r */
 646 #define CtcReg_High     0x38    /* r */
 647 #define ScsiFifo        0x08
 648 #define ScsiCmd         0x0C
 649 #define Scsi_Status     0x10    /* r */
 650 #define INT_Status      0x14    /* r */
 651 #define Sync_Period     0x18    /* w */
 652 #define Sync_Offset     0x1C    /* w */
 653 #define Clk_Factor      0x24    /* w */
 654 #define CtrlReg1        0x20
 655 #define CtrlReg2        0x2C
 656 #define CtrlReg3        0x30
 657 #define CtrlReg4        0x34
 658 #define DMA_Cmd         0x40
 659 #define DMA_XferCnt     0x44    /* rw   starting transfer count (32 bit) */
 660 #define DMA_XferAddr    0x48    /* rw   starting physical address (32 bit) */
 661 #define DMA_Wk_ByteCntr 0x4C    /* r    working byte counter */
 662 #define DMA_Wk_AddrCntr 0x50    /* r    working address counter */
 663 #define DMA_Status      0x54    /* r */
 664 #define DMA_MDL_Addr    0x58    /* rw   starting MDL address */
 665 #define DMA_Wk_MDL_Cntr 0x5C    /* r    working MDL counter */
 666 #define DMA_ScsiBusCtrl 0x70    /* rw   SCSI Bus, PCI/DMA Ctrl */
 667
 668 #define StcReg_Low      CtcReg_Low      /* w    start transfer count */
 669 #define StcReg_Mid      CtcReg_Mid      /* w */
 670 #define StcReg_High     CtcReg_High     /* w */
 671 #define Scsi_Dest_ID    Scsi_Status     /* w */
 672 #define Scsi_TimeOut    INT_Status      /* w */
 673 #define Intern_State    Sync_Period     /* r */
 674 #define Current_Fifo    Sync_Offset     /* r    Curr. FIFO / int. state */
 675
 676
 677 #define DC390_read8(address)                    \
 678         (inb (pACB->IOPortBase + (address)))
 679
 680 #define DC390_read8_(address, base)             \
 681         (inb ((USHORT)(base) + (address)))
 682
 683 #define DC390_read16(address)                   \
 684         (inw (pACB->IOPortBase + (address)))
 685
 686 #define DC390_read32(address)                   \
 687         (inl (pACB->IOPortBase + (address)))
 688
 689 #define DC390_write8(address,value)             \
 690         outb ((value), pACB->IOPortBase + (address))
 691
 692 #define DC390_write8_(address,value,base)       \
 693         outb ((value), (USHORT)(base) + (address))
 694
 695 #define DC390_write16(address,value)            \
 696         outw ((value), pACB->IOPortBase + (address))
 697
 698 #define DC390_write32(address,value)            \
 699         outl ((value), pACB->IOPortBase + (address))
 700
 701
 702 #endif /* _TMSCSIM_H */