drivers/scsi/3w-xxxx.h

   1 /*
   2    3w-xxxx.h -- 3ware Storage Controller device driver for Linux.
   3
   4    Written By: Adam Radford <linux@3ware.com>
   5    Modifications By: Joel Jacobson <linux@3ware.com>
   6
   7    Copyright (C) 1999 3ware Inc.
   8
   9    Kernel compatablity By:      Andre Hedrick <andre@suse.com>
  10    Non-Copyright (C) 2000       Andre Hedrick <andre@suse.com>
  11
  12    This program is free software; you can redistribute it and/or modify
  13    it under the terms of the GNU General Public License as published by
  14    the Free Software Foundation; version 2 of the License.
  15
  16    This program is distributed in the hope that it will be useful,
  17    but WITHOUT ANY WARRANTY; without even the implied warranty of
  18    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19    GNU General Public License for more details.
  20
  21    NO WARRANTY
  22    THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  23    CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  24    LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  25    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  26    solely responsible for determining the appropriateness of using and
  27    distributing the Program and assumes all risks associated with its
  28    exercise of rights under this Agreement, including but not limited to
  29    the risks and costs of program errors, damage to or loss of data,
  30    programs or equipment, and unavailability or interruption of operations.
  31
  32    DISCLAIMER OF LIABILITY
  33    NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  34    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  35    DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  36    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  37    TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  38    USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  39    HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  40
  41    You should have received a copy of the GNU General Public License
  42    along with this program; if not, write to the Free Software
  43    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  44
  45    Bugs/Comments/Suggestions should be mailed to:
  46    linux@3ware.com
  47
  48    For more information, goto:
  49    http://www.3ware.com
  50 */
  51
  52 #ifndef _3W_XXXX_H
  53 #define _3W_XXXX_H
  54
  55 #include <linux/version.h>
  56 #include <linux/types.h>
  57 #include <linux/kdev_t.h>
  58
  59 /* Control register bit definitions */
  60 #define TW_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
  61 #define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
  62 #define TW_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
  63 #define TW_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
  64 #define TW_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
  65 #define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
  66 #define TW_CONTROL_CLEAR_ERROR_STATUS          0x00000200
  67 #define TW_CONTROL_ISSUE_SOFT_RESET            0x00000100
  68 #define TW_CONTROL_ENABLE_INTERRUPTS           0x00000080
  69 #define TW_CONTROL_DISABLE_INTERRUPTS          0x00000040
  70 #define TW_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
  71
  72 /* Status register bit definitions */
  73 #define TW_STATUS_MAJOR_VERSION_MASK           0xF0000000
  74 #define TW_STATUS_MINOR_VERSION_MASK           0x0F000000
  75 #define TW_STATUS_PCI_PARITY_ERROR             0x00800000
  76 #define TW_STATUS_QUEUE_ERROR                  0x00400000
  77 #define TW_STATUS_MICROCONTROLLER_ERROR        0x00200000
  78 #define TW_STATUS_PCI_ABORT                    0x00100000
  79 #define TW_STATUS_HOST_INTERRUPT               0x00080000
  80 #define TW_STATUS_ATTENTION_INTERRUPT          0x00040000
  81 #define TW_STATUS_COMMAND_INTERRUPT            0x00020000
  82 #define TW_STATUS_RESPONSE_INTERRUPT           0x00010000
  83 #define TW_STATUS_COMMAND_QUEUE_FULL           0x00008000
  84 #define TW_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
  85 #define TW_STATUS_MICROCONTROLLER_READY        0x00002000
  86 #define TW_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
  87 #define TW_STATUS_ALL_INTERRUPTS               0x000F0000
  88 #define TW_STATUS_CLEARABLE_BITS               0x00D00000
  89 #define TW_STATUS_EXPECTED_BITS                0x00002000
  90 #define TW_STATUS_UNEXPECTED_BITS              0x00F80000
  91
  92 /* RESPONSE QUEUE BIT DEFINITIONS */
  93 #define TW_RESPONSE_ID_MASK                    0x00000FF0
  94
  95 /* PCI related defines */
  96 #define TW_IO_ADDRESS_RANGE                    0xD
  97 #define TW_DEVICE_NAME                         "3ware Storage Controller"
  98 #define TW_VENDOR_ID (0x13C1)   /* 3ware */
  99 #define TW_DEVICE_ID (0x1000)   /* Storage Controller */
 100
 101 /* Command packet opcodes */
 102 #define TW_OP_NOP             0x0
 103 #define TW_OP_INIT_CONNECTION 0x1
 104 #define TW_OP_READ            0x2
 105 #define TW_OP_WRITE           0x3
 106 #define TW_OP_VERIFY          0x4
 107 #define TW_OP_GET_PARAM       0x12
 108 #define TW_OP_SET_PARAM       0x13
 109 #define TW_OP_SECTOR_INFO     0x1a
 110 #define TW_OP_AEN_LISTEN      0x1c
 111 #define TW_CMD_PACKET         0x1d
 112
 113 /* Asynchronous Event Notification (AEN) Codes */
 114 #define TW_AEN_QUEUE_EMPTY       0x0000
 115 #define TW_AEN_SOFT_RESET        0x0001
 116 #define TW_AEN_DEGRADED_MIRROR   0x0002
 117 #define TW_AEN_CONTROLLER_ERROR  0x0003
 118 #define TW_AEN_REBUILD_FAIL      0x0004
 119 #define TW_AEN_REBUILD_DONE      0x0005
 120 #define TW_AEN_QUEUE_FULL        0x00ff
 121 #define TW_AEN_TABLE_UNDEFINED   0x15
 122
 123 /* Misc defines */
 124 #define TW_ALIGNMENT                          0x200 /* 16 D-WORDS */
 125 #define TW_MAX_UNITS                          16
 126 #define TW_COMMAND_ALIGNMENT_MASK             0x1ff
 127 #define TW_INIT_MESSAGE_CREDITS               0x100
 128 #define TW_INIT_COMMAND_PACKET_SIZE           0x3
 129 #define TW_POLL_MAX_RETRIES                   10000
 130 #define TW_MAX_SGL_LENGTH                     62
 131 #define TW_Q_LENGTH                           256
 132 #define TW_Q_START                            0
 133 #define TW_MAX_SLOT                           32
 134 #define TW_MAX_PCI_BUSES                      255
 135 #define TW_MAX_RESET_TRIES                    3
 136 #define TW_UNIT_INFORMATION_TABLE_BASE        0x300
 137 #define TW_MAX_CMDS_PER_LUN                   (TW_Q_LENGTH-2)/TW_MAX_UNITS
 138 #define TW_BLOCK_SIZE                         0x200 /* 512-byte blocks */
 139 #define TW_IOCTL                              0x80
 140 #define TW_MAX_AEN_TRIES                      100
 141 #define TW_UNIT_ONLINE                        1
 142 #define TW_IN_INTR                            1
 143
 144 /* Macros */
 145 #define TW_STATUS_ERRORS(x) \
 146         (((x & TW_STATUS_PCI_ABORT) || \
 147         (x & TW_STATUS_PCI_PARITY_ERROR) || \
 148         (x & TW_STATUS_QUEUE_ERROR) || \
 149         (x & TW_STATUS_MICROCONTROLLER_ERROR)) && \
 150         (x & TW_STATUS_MICROCONTROLLER_READY))
 151
 152 #ifdef TW_DEBUG
 153 #define dprintk(msg...) printk(msg)
 154 #else
 155 #define dprintk(msg...) do { } while(0);
 156 #endif
 157
 158 /* Scatter Gather List Entry */
 159 typedef struct TAG_TW_SG_Entry {
 160         unsigned long address;
 161         unsigned long length;
 162 } TW_SG_Entry;
 163
 164 typedef unsigned char TW_Sector[512];
 165
 166 /* Command Packet */
 167 typedef struct TW_Command {
 168         /* First DWORD */
 169         struct {
 170                 unsigned char opcode:5;
 171                 unsigned char sgl_offset:3;
 172         } byte0;
 173         unsigned char size;
 174         unsigned char request_id;
 175         struct {
 176                 unsigned char unit:4;
 177                 unsigned char host_id:4;
 178         } byte3;
 179         /* Second DWORD */
 180         unsigned char status;
 181         unsigned char flags;
 182         union {
 183                 unsigned short block_count;
 184                 unsigned short parameter_count;
 185                 unsigned short message_credits;
 186         } byte6;
 187         union {
 188                 struct {
 189                         unsigned long lba;
 190                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 191                         unsigned long padding;  /* pad to 512 bytes */
 192                 } io;
 193                 struct {
 194                         TW_SG_Entry sgl[TW_MAX_SGL_LENGTH];
 195                         unsigned long padding[2];
 196                 } param;
 197                 struct {
 198                         unsigned long response_queue_pointer;
 199                         unsigned long padding[125];
 200                 } init_connection;
 201                 struct {
 202                         char version[504];
 203                 } ioctl_miniport_version;
 204         } byte8;
 205 } TW_Command;
 206
 207 typedef struct TAG_TW_Ioctl {
 208         int buffer;
 209         unsigned char opcode;
 210         unsigned short table_id;
 211         unsigned char parameter_id;
 212         unsigned char parameter_size_bytes;
 213         unsigned char data[1];
 214 } TW_Ioctl;
 215
 216 /* GetParam descriptor */
 217 typedef struct {
 218         unsigned short  table_id;
 219         unsigned char   parameter_id;
 220         unsigned char   parameter_size_bytes;
 221         unsigned char   data[1];
 222 } TW_Param, *PTW_Param;
 223
 224 /* Response queue */
 225 typedef union TAG_TW_Response_Queue {
 226         struct {
 227                 u32 undefined_1: 4;
 228                 u32 response_id: 8;
 229                 u32 undefined_2: 20;
 230         } u;
 231         u32 value;
 232 } TW_Response_Queue;
 233
 234 typedef struct TAG_TW_Registers {
 235         u32 base_addr;
 236         u32 control_reg_addr;
 237         u32 status_reg_addr;
 238         u32 command_que_addr;
 239         u32 response_que_addr;
 240 } TW_Registers;
 241
 242 typedef struct TAG_TW_Info {
 243         char *buffer;
 244         int length;
 245         int offset;
 246         int position;
 247 } TW_Info;
 248
 249 typedef enum TAG_TW_Cmd_State {
 250         TW_S_INITIAL,           /* Initial state */
 251         TW_S_STARTED,           /* Id in use */
 252         TW_S_POSTED,            /* Posted to the controller */
 253         TW_S_PENDING,           /* Waiting to be posted in isr */
 254         TW_S_COMPLETED,         /* Completed by isr */
 255         TW_S_FINISHED,          /* I/O completely done */
 256 } TW_Cmd_State;
 257
 258 typedef struct TAG_TW_Device_Extension {
 259         TW_Registers            registers;
 260         u32                     *alignment_virtual_address[TW_Q_LENGTH];
 261         u32                     alignment_physical_address[TW_Q_LENGTH];
 262         int                     is_unit_present[TW_MAX_UNITS];
 263         int                     num_units;
 264         u32                     *command_packet_virtual_address[TW_Q_LENGTH];
 265         u32                     command_packet_physical_address[TW_Q_LENGTH];
 266         struct pci_dev          *tw_pci_dev;
 267         Scsi_Cmnd               *srb[TW_Q_LENGTH];
 268         unsigned char           free_queue[TW_Q_LENGTH];
 269         unsigned char           free_head;
 270         unsigned char           free_tail;
 271         unsigned char           pending_queue[TW_Q_LENGTH];
 272         unsigned char           pending_head;
 273         unsigned char           pending_tail;
 274         TW_Cmd_State            state[TW_Q_LENGTH];
 275         u32                     posted_request_count;
 276         u32                     max_posted_request_count;
 277         u32                     request_count_marked_pending;
 278         u32                     pending_request_count;
 279         u32                     max_pending_request_count;
 280         u32                     max_sgl_entries;
 281         u32                     sgl_entries;
 282         u32                     num_aborts;
 283         u32                     num_resets;
 284         u32                     sector_count;
 285         u32                     max_sector_count;
 286         struct Scsi_Host        *host;
 287         spinlock_t              tw_lock;
 288         unsigned char           ioctl_size[TW_Q_LENGTH];
 289         unsigned short          aen_queue[TW_Q_LENGTH];
 290         unsigned char           aen_head;
 291         unsigned char           aen_tail;
 292         u32                     flags;
 293 } TW_Device_Extension;
 294
 295 /* Function prototypes */
 296 int tw_aen_complete(TW_Device_Extension *tw_dev, int request_id);
 297 int tw_aen_drain_queue(TW_Device_Extension *tw_dev);
 298 int tw_aen_read_queue(TW_Device_Extension *tw_dev, int request_id);
 299 int tw_allocate_memory(TW_Device_Extension *tw_dev, int request_id, int size, int which);
 300 int tw_check_bits(u32 status_reg_value);
 301 int tw_check_errors(TW_Device_Extension *tw_dev);
 302 void tw_clear_attention_interrupt(TW_Device_Extension *tw_dev);
 303 void tw_clear_host_interrupt(TW_Device_Extension *tw_dev);
 304 void tw_disable_interrupts(TW_Device_Extension *tw_dev);
 305 int tw_empty_response_que(TW_Device_Extension *tw_dev);
 306 void tw_enable_interrupts(TW_Device_Extension *tw_dev);
 307 int tw_findcards(Scsi_Host_Template *tw_host);
 308 void tw_free_device_extension(TW_Device_Extension *tw_dev);
 309 int tw_initconnection(TW_Device_Extension *tw_dev, int message_credits);
 310 int tw_initialize_device_extension(TW_Device_Extension *tw_dev);
 311 int tw_initialize_units(TW_Device_Extension *tw_dev);
 312 int tw_ioctl(TW_Device_Extension *tw_dev, int request_id);
 313 int tw_ioctl_complete(TW_Device_Extension *tw_dev, int request_id);
 314 void tw_mask_command_interrupt(TW_Device_Extension *tw_dev);
 315 int tw_poll_status(TW_Device_Extension *tw_dev, u32 flag, int seconds);
 316 int tw_post_command_packet(TW_Device_Extension *tw_dev, int request_id);
 317 int tw_reset_device_extension(TW_Device_Extension *tw_dev);
 318 int tw_reset_sequence(TW_Device_Extension *tw_dev);
 319 int tw_scsi_biosparam(Disk *disk, kdev_t dev, int geom[]);
 320 int tw_scsi_detect(Scsi_Host_Template *tw_host);
 321 int tw_scsi_eh_abort(Scsi_Cmnd *SCpnt);
 322 int tw_scsi_eh_reset(Scsi_Cmnd *SCpnt);
 323 int tw_scsi_proc_info(char *buffer, char **start, off_t offset, int length, int inode, int inout);
 324 int tw_scsi_queue(Scsi_Cmnd *cmd, void (*done) (Scsi_Cmnd *));
 325 int tw_scsi_release(struct Scsi_Host *tw_host);
 326 int tw_scsiop_inquiry(TW_Device_Extension *tw_dev, int request_id);
 327 int tw_scsiop_inquiry_complete(TW_Device_Extension *tw_dev, int request_id);
 328 int tw_scsiop_read_capacity(TW_Device_Extension *tw_dev, int request_id);
 329 int tw_scsiop_read_capacity_complete(TW_Device_Extension *tw_dev, int request_id);
 330 int tw_scsiop_read_write(TW_Device_Extension *tw_dev, int request_id);
 331 int tw_scsiop_test_unit_ready(TW_Device_Extension *tw_dev, int request_id);
 332 int tw_setfeature(TW_Device_Extension *tw_dev, int parm, int param_size,
 333                   unsigned char *val);
 334 int tw_setup_irq(TW_Device_Extension *tw_dev);
 335 int tw_shutdown_device(TW_Device_Extension *tw_dev);
 336 void tw_soft_reset(TW_Device_Extension *tw_dev);
 337 int tw_state_request_finish(TW_Device_Extension *tw_dev,int request_id);
 338 int tw_state_request_start(TW_Device_Extension *tw_dev, int *request_id);
 339 void tw_unmask_command_interrupt(TW_Device_Extension *tw_dev);
 340
 341 /* Scsi_Host_Template Initializer */
 342 #define TWXXXX {                                        \
 343         next : NULL,                                    \
 344         module : NULL,                                  \
 345         proc_name : "3w-xxxx",                          \
 346         proc_info : tw_scsi_proc_info,                  \
 347         name : "3ware Storage Controller",              \
 348         detect : tw_scsi_detect,                        \
 349         release : tw_scsi_release,                      \
 350         info : NULL,                                    \
 351         ioctl : NULL,                                   \
 352         command : NULL,                                 \
 353         queuecommand : tw_scsi_queue,                   \
 354         eh_strategy_handler : NULL,                     \
 355         eh_abort_handler : tw_scsi_eh_abort,            \
 356         eh_device_reset_handler : NULL,                 \
 357         eh_bus_reset_handler : NULL,                    \
 358         eh_host_reset_handler : tw_scsi_eh_reset,       \
 359         abort : NULL,                                   \
 360         reset : NULL,                                   \
 361         slave_attach : NULL,                            \
 362         bios_param : tw_scsi_biosparam,                 \
 363         can_queue : TW_Q_LENGTH,                        \
 364         this_id: -1,                                    \
 365         sg_tablesize : TW_MAX_SGL_LENGTH,               \
 366         cmd_per_lun: TW_MAX_CMDS_PER_LUN,               \
 367         present : 0,                                    \
 368         unchecked_isa_dma : 0,                          \
 369         use_clustering : ENABLE_CLUSTERING,             \
 370         use_new_eh_code : 1,                            \
 371         emulated : 1                                    \
 372 }
 373 #endif /* _3W_XXXX_H */