include/asm-m68k/mac_psc.h

   1 /*
   2  * Apple Peripheral System Controller (PSC)
   3  *
   4  * The PSC is used on the AV Macs to control IO functions not handled
   5  * by the VIAs (Ethernet, DSP, SCC, Sound). This includes nine DMA
   6  * channels.
   7  *
   8  * The first seven DMA channels appear to be "one-shot" and are actually
   9  * sets of two channels; one member is active while the other is being
  10  * configured, and then you flip the active member and start all over again.
  11  * The one-shot channels are grouped together and are:
  12  *
  13  * 1. SCSI
  14  * 2. Ethernet Read
  15  * 3. Ethernet Write
  16  * 4. Floppy Disk Controller
  17  * 5. SCC Channel A Receive
  18  * 6. SCC Channel B Receive
  19  * 7. SCC Channel A Transmit
  20  *
  21  * The remaining two channels are handled somewhat differently. They appear
  22  * to be closely tied and share one set of registers. They also seem to run
  23  * continuously, although how you keep the buffer filled in this scenario is
  24  * not understood as there seems to be only one input and one output buffer
  25  * pointer.
  26  *
  27  * Much of this was extrapolated from what was known about the Ethernet
  28  * registers and subsequently confirmed using MacsBug (ie by pinging the
  29  * machine with easy-to-find patterns and looking for them in the DMA
  30  * buffers, or by sending a file over the serial ports and finding the
  31  * file in the buffers.)
  32  *
  33  * 1999-05-25 (jmt)
  34  */
  35
  36 #define PSC_BASE        (0x50F31000)
  37
  38 /*
  39  * The IER/IFR registers work like the VIA, except that it has 4
  40  * of them each on different interrupt levels, and each register
  41  * set only seems to handle four interrupts instead of seven.
  42  *
  43  * To access a particular set of registers, add 0xn0 to the base
  44  * where n = 3,4,5 or 6.
  45  */
  46
  47 #define pIFRbase        0x100
  48 #define pIERbase        0x104
  49
  50 /*
  51  * One-shot DMA control registers
  52  */
  53
  54 #define PSC_CTL_BASE    0xC00
  55
  56 #define PSC_SCSI_CTL    0xC00
  57 #define PSC_ENETRD_CTL  0xC10
  58 #define PSC_ENETWR_CTL  0xC20
  59 #define PSC_FDC_CTL     0xC30
  60 #define PSC_SCCA_CTL    0xC40
  61 #define PSC_SCCB_CTL    0xC50
  62 #define PSC_SCCATX_CTL  0xC60
  63
  64 /*
  65  * DMA channels. Add +0x10 for the second channel in the set.
  66  * You're supposed to use one channel while the other runs and
  67  * then flip channels and do the whole thing again.
  68  */
  69
  70 #define PSC_ADDR_BASE   0x1000
  71 #define PSC_LEN_BASE    0x1004
  72 #define PSC_CMD_BASE    0x1008
  73
  74 #define PSC_SCSI_ADDR   0x1000  /* confirmed */
  75 #define PSC_SCSI_LEN    0x1004  /* confirmed */
  76 #define PSC_SCSI_CMD    0x1008  /* confirmed */
  77 #define PSC_ENETRD_ADDR 0x1020  /* confirmed */
  78 #define PSC_ENETRD_LEN  0x1024  /* confirmed */
  79 #define PSC_ENETRD_CMD  0x1028  /* confirmed */
  80 #define PSC_ENETWR_ADDR 0x1040  /* confirmed */
  81 #define PSC_ENETWR_LEN  0x1044  /* confirmed */
  82 #define PSC_ENETWR_CMD  0x1048  /* confirmed */
  83 #define PSC_FDC_ADDR    0x1060  /* strongly suspected */
  84 #define PSC_FDC_LEN     0x1064  /* strongly suspected */
  85 #define PSC_FDC_CMD     0x1068  /* strongly suspected */
  86 #define PSC_SCCA_ADDR   0x1080  /* confirmed */
  87 #define PSC_SCCA_LEN    0x1084  /* confirmed */
  88 #define PSC_SCCA_CMD    0x1088  /* confirmed */
  89 #define PSC_SCCB_ADDR   0x10A0  /* confirmed */
  90 #define PSC_SCCB_LEN    0x10A4  /* confirmed */
  91 #define PSC_SCCB_CMD    0x10A8  /* confirmed */
  92 #define PSC_SCCATX_ADDR 0x10C0  /* confirmed */
  93 #define PSC_SCCATX_LEN  0x10C4  /* confirmed */
  94 #define PSC_SCCATX_CMD  0x10C8  /* confirmed */
  95
  96 /*
  97  * Free-running DMA registers. The only part known for sure are the bits in
  98  * the control register, the buffer addresses and the buffer length. Everything
  99  * else is anybody's guess.
 100  *
 101  * These registers seem to be mirrored every thirty-two bytes up until offset
 102  * 0x300. It's safe to assume then that a new set of registers starts there.
 103  */
 104
 105 #define PSC_SND_CTL     0x200   /*
 106                                  * [ 16-bit ]
 107                                  * Sound (Singer?) control register.
 108                                  *
 109                                  * bit 0  : ????
 110                                  * bit 1  : ????
 111                                  * bit 2  : Set to one to enable sound
 112                                  *          output. Possibly a mute flag.
 113                                  * bit 3  : ????
 114                                  * bit 4  : ????
 115                                  * bit 5  : ????
 116                                  * bit 6  : Set to one to enable pass-thru
 117                                  *          audio. In this mode the audio data
 118                                  *          seems to appear in both the input
 119                                  *          buffer and the output buffer.
 120                                  * bit 7  : Set to one to activate the
 121                                  *          sound input DMA or zero to
 122                                  *          disable it.
 123                                  * bit 8  : Set to one to activate the
 124                                  *          sound output DMA or zero to
 125                                  *          disable it.
 126                                  * bit 9  : \
 127                                  * bit 11 :  |
 128                                  *          These two bits control the sample
 129                                  *          rate. Usually set to binary 10 and
 130                                  *          MacOS 8.0 says I'm at 48 KHz. Using
 131                                  *          a binary value of 01 makes things
 132                                  *          sound about 1/2 speed (24 KHz?) and
 133                                  *          binary 00 is slower still (22 KHz?)
 134                                  *
 135                                  * Setting this to 0x0000 is a good way to
 136                                  * kill all DMA at boot time so that the
 137                                  * PSC won't overwrite the kernel image
 138                                  * with sound data.
 139                                  */
 140
 141 /*
 142  * 0x0202 - 0x0203 is unused. Writing there
 143  * seems to clobber the control register.
 144  */
 145
 146 #define PSC_SND_SOURCE  0x204   /*
 147                                  * [ 32-bit ]
 148                                  * Controls input source and volume:
 149                                  *
 150                                  * bits 12-15 : input source volume, 0 - F
 151                                  * bits 16-19 : unknown, always 0x5
 152                                  * bits 20-23 : input source selection:
 153                                  *                  0x3 = CD Audio
 154                                  *                  0x4 = External Audio
 155                                  *
 156                                  * The volume is definately not the general
 157                                  * output volume as it doesn't affect the
 158                                  * alert sound volume.
 159                                  */
 160 #define PSC_SND_STATUS1 0x208   /*
 161                                  * [ 32-bit ]
 162                                  * Appears to be a read-only status register.
 163                                  * The usual value is 0x00400002.
 164                                  */
 165 #define PSC_SND_HUH3    0x20C   /*
 166                                  * [ 16-bit ]
 167                                  * Unknown 16-bit value, always 0x0000.
 168                                  */
 169 #define PSC_SND_BITS2GO 0x20E   /*
 170                                  * [ 16-bit ]
 171                                  * Counts down to zero from some constant
 172                                  * value. The value appears to be the
 173                                  * number of _bits_ remaining before the
 174                                  * buffer is full, which would make sense
 175                                  * since Apple's docs say the sound DMA
 176                                  * channels are 1 bit wide.
 177                                  */
 178 #define PSC_SND_INADDR  0x210   /*
 179                                  * [ 32-bit ]
 180                                  * Address of the sound input DMA buffer
 181                                  */
 182 #define PSC_SND_OUTADDR 0x214   /*
 183                                  * [ 32-bit ]
 184                                  * Address of the sound output DMA buffer
 185                                  */
 186 #define PSC_SND_LEN     0x218   /*
 187                                  * [ 16-bit ]
 188                                  * Length of both buffers in eight-byte units.
 189                                  */
 190 #define PSC_SND_HUH4    0x21A   /*
 191                                  * [ 16-bit ]
 192                                  * Unknown, always 0x0000.
 193                                  */
 194 #define PSC_SND_STATUS2 0x21C   /*
 195                                  * [ 16-bit ]
 196                                  * Appears to e a read-only status register.
 197                                  * The usual value is 0x0200.
 198                                  */
 199 #define PSC_SND_HUH5    0x21E   /*
 200                                  * [ 16-bit ]
 201                                  * Unknown, always 0x0000.
 202                                  */
 203
 204 #ifndef __ASSEMBLY__
 205
 206 extern volatile __u8 *psc;
 207 extern int psc_present;
 208
 209 /*
 210  *      Access functions
 211  */
 212
 213 extern inline void psc_write_byte(int offset, __u8 data)
 214 {
 215         *((volatile __u8 *)(psc + offset)) = data;
 216 }
 217
 218 extern inline void psc_write_word(int offset, __u16 data)
 219 {
 220         *((volatile __u16 *)(psc + offset)) = data;
 221 }
 222
 223 extern inline void psc_write_long(int offset, __u32 data)
 224 {
 225         *((volatile __u32 *)(psc + offset)) = data;
 226 }
 227
 228 extern inline u8 psc_read_byte(int offset)
 229 {
 230         return *((volatile __u8 *)(psc + offset));
 231 }
 232
 233 extern inline u16 psc_read_word(int offset)
 234 {
 235         return *((volatile __u16 *)(psc + offset));
 236 }
 237
 238 extern inline u32 psc_read_long(int offset)
 239 {
 240         return *((volatile __u32 *)(psc + offset));
 241 }
 242
 243 #endif /* __ASSEMBLY__ */