2 * Sound driver for Silicon Graphics 320 and 540 Visual Workstations'
3 * onboard audio. See notes in ../../Documentation/sound/vwsnd .
5 * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #undef VWSND_DEBUG /* define for debugging */
28 * Rename swbuf, hwbuf, u&i, hwptr&swptr to something rational.
29 * Bug - if select() called before read(), pcm_setup() not called.
30 * Bug - output doesn't stop soon enough if process killed.
36 * Will readv/writev work? Write a test.
38 * insmod/rmmod 100 million times.
40 * Run I/O until int ptrs wrap around (roughly 6.2 hours @ DAT
43 * Concurrent threads banging on mixer simultaneously, both UP
44 * and SMP kernels. Especially, watch for thread A changing
45 * OUTSRC while thread B changes gain -- both write to the same
48 * What happens if a client opens /dev/audio then forks?
49 * Do two procs have /dev/audio open? Test.
51 * Pump audio through the CD, MIC and line inputs and verify that
52 * they mix/mute into the output.
61 * need more input apps
63 * Run tests while bombarding with signals. setitimer(2) will do it... */
66 * This driver is organized in nine sections.
67 * The nine sections are:
70 * low level lithium access
71 * high level lithium access
77 * initialization and loadable kernel module interface
79 * That is roughly the order of increasing abstraction, so forward
80 * dependencies are minimal.
86 * INC_USE_COUNT and DEC_USE_COUNT keep track of the number of
87 * open descriptors to this driver. They store it in vwsnd_use_count.
88 * The global device list, vwsnd_dev_list, is immutable when the IN_USE
91 * devc->open_lock is a semaphore that is used to enforce the
92 * single reader/single writer rule for /dev/audio. The rule is
93 * that each device may have at most one reader and one writer.
94 * Open will block until the previous client has closed the
95 * device, unless O_NONBLOCK is specified.
97 * The semaphore devc->io_sema serializes PCM I/O syscalls. This
98 * is unnecessary in Linux 2.2, because the kernel lock
99 * serializes read, write, and ioctl globally, but it's there,
100 * ready for the brave, new post-kernel-lock world.
102 * Locking between interrupt and baselevel is handled by the
103 * "lock" spinlock in vwsnd_port (one lock each for read and
104 * write). Each half holds the lock just long enough to see what
105 * area it owns and update its pointers. See pcm_output() and
106 * pcm_input() for most of the gory stuff.
108 * devc->mix_sema serializes all mixer ioctls. This is also
109 * redundant because of the kernel lock.
111 * The lowest level lock is lith->lithium_lock. It is a
112 * spinlock which is held during the two-register tango of
113 * reading/writing an AD1843 register. See
114 * li_{read,write}_ad1843_reg().
118 * Sample Format Notes
120 * Lithium's DMA engine has two formats: 16-bit 2's complement
121 * and 8-bit unsigned . 16-bit transfers the data unmodified, 2
122 * bytes per sample. 8-bit unsigned transfers 1 byte per sample
123 * and XORs each byte with 0x80. Lithium can input or output
124 * either mono or stereo in either format.
126 * The AD1843 has four formats: 16-bit 2's complement, 8-bit
127 * unsigned, 8-bit mu-Law and 8-bit A-Law.
129 * This driver supports five formats: AFMT_S8, AFMT_U8,
130 * AFMT_MU_LAW, AFMT_A_LAW, and AFMT_S16_LE.
132 * For AFMT_U8 output, we keep the AD1843 in 16-bit mode, and
133 * rely on Lithium's XOR to translate between U8 and S8.
135 * For AFMT_S8, AFMT_MU_LAW and AFMT_A_LAW output, we have to XOR
136 * the 0x80 bit in software to compensate for Lithium's XOR.
137 * This happens in pcm_copy_{in,out}().
140 * 11-10-2000 Bartlomiej Zolnierkiewicz <bkz@linux-ide.org>
141 * Added some __init/__exit
144 #include <linux/module.h>
145 #include <linux/init.h>
147 #include <linux/sched.h>
148 #include <linux/semaphore.h>
149 #include <linux/stddef.h>
150 #include <linux/spinlock.h>
151 #include <linux/smp_lock.h>
152 #include <asm/fixmap.h>
153 #include <asm/cobalt.h>
154 #include <asm/semaphore.h>
156 #include "sound_config.h"
158 /*****************************************************************************/
163 #include <linux/interrupt.h> /* for in_interrupt() */
165 static int shut_up
= 1;
168 * dbgassert - called when an assertion fails.
171 static void dbgassert(const char *fcn
, int line
, const char *expr
)
174 panic("ASSERTION FAILED IN INTERRUPT, %s:%s:%d %s\n",
175 __FILE__
, fcn
, line
, expr
);
178 printk(KERN_ERR
"ASSERTION FAILED, %s:%s:%d %s\n",
179 __FILE__
, fcn
, line
, expr
);
180 x
= * (volatile int *) 0; /* force proc to exit */
185 * Bunch of useful debug macros:
187 * ASSERT - print unless e nonzero (panic if in interrupt)
188 * DBGDO - include arbitrary code if debugging
189 * DBGX - debug print raw (w/o function name)
190 * DBGP - debug print w/ function name
191 * DBGE - debug print function entry
192 * DBGC - debug print function call
193 * DBGR - debug print function return
194 * DBGXV - debug print raw when verbose
195 * DBGPV - debug print when verbose
196 * DBGEV - debug print function entry when verbose
197 * DBGRV - debug print function return when verbose
200 #define ASSERT(e) ((e) ? (void) 0 : dbgassert(__FUNCTION__, __LINE__, #e))
202 #define DBGX(fmt, args...) (in_interrupt() ? 0 : printk(KERN_ERR fmt, ##args))
203 #define DBGP(fmt, args...) (DBGX(__FUNCTION__ ": " fmt, ##args))
204 #define DBGE(fmt, args...) (DBGX(__FUNCTION__ fmt, ##args))
205 #define DBGC(rtn) (DBGP("calling %s\n", rtn))
206 #define DBGR() (DBGP("returning\n"))
207 #define DBGXV(fmt, args...) (shut_up ? 0 : DBGX(fmt, ##args))
208 #define DBGPV(fmt, args...) (shut_up ? 0 : DBGP(fmt, ##args))
209 #define DBGEV(fmt, args...) (shut_up ? 0 : DBGE(fmt, ##args))
210 #define DBGCV(rtn) (shut_up ? 0 : DBGC(rtn))
211 #define DBGRV() (shut_up ? 0 : DBGR())
213 #else /* !VWSND_DEBUG */
215 #define ASSERT(e) ((void) 0)
216 #define DBGDO(x) /* don't */
217 #define DBGX(fmt, args...) ((void) 0)
218 #define DBGP(fmt, args...) ((void) 0)
219 #define DBGE(fmt, args...) ((void) 0)
220 #define DBGC(rtn) ((void) 0)
221 #define DBGR() ((void) 0)
222 #define DBGPV(fmt, args...) ((void) 0)
223 #define DBGXV(fmt, args...) ((void) 0)
224 #define DBGEV(fmt, args...) ((void) 0)
225 #define DBGCV(rtn) ((void) 0)
226 #define DBGRV() ((void) 0)
228 #endif /* !VWSND_DEBUG */
230 /*****************************************************************************/
231 /* low level lithium access */
234 * We need to talk to Lithium registers on three pages. Here are
235 * the pages' offsets from the base address (0xFF001000).
239 LI_PAGE0_OFFSET
= 0x01000 - 0x1000, /* FF001000 */
240 LI_PAGE1_OFFSET
= 0x0F000 - 0x1000, /* FF00F000 */
241 LI_PAGE2_OFFSET
= 0x10000 - 0x1000, /* FF010000 */
244 /* low-level lithium data */
246 typedef struct lithium
{
247 caddr_t page0
; /* virtual addresses */
250 spinlock_t lock
; /* protects codec and UST/MSC access */
254 * li_create initializes the lithium_t structure and sets up vm mappings
255 * to access the registers.
256 * Returns 0 on success, -errno on failure.
259 static int li_create(lithium_t
*lith
, unsigned long baseaddr
)
261 static void li_destroy(lithium_t
*);
263 lith
->lock
= SPIN_LOCK_UNLOCKED
;
264 lith
->page0
= ioremap_nocache(baseaddr
+ LI_PAGE0_OFFSET
, PAGE_SIZE
);
265 lith
->page1
= ioremap_nocache(baseaddr
+ LI_PAGE1_OFFSET
, PAGE_SIZE
);
266 lith
->page2
= ioremap_nocache(baseaddr
+ LI_PAGE2_OFFSET
, PAGE_SIZE
);
267 if (!lith
->page0
|| !lith
->page1
|| !lith
->page2
) {
275 * li_destroy destroys the lithium_t structure and vm mappings.
278 static void li_destroy(lithium_t
*lith
)
281 iounmap(lith
->page0
);
285 iounmap(lith
->page1
);
289 iounmap(lith
->page2
);
295 * basic register accessors - read/write long/byte
298 static __inline__
unsigned long li_readl(lithium_t
*lith
, int off
)
300 return * (volatile unsigned long *) (lith
->page0
+ off
);
303 static __inline__
unsigned char li_readb(lithium_t
*lith
, int off
)
305 return * (volatile unsigned char *) (lith
->page0
+ off
);
308 static __inline__
void li_writel(lithium_t
*lith
, int off
, unsigned long val
)
310 * (volatile unsigned long *) (lith
->page0
+ off
) = val
;
313 static __inline__
void li_writeb(lithium_t
*lith
, int off
, unsigned char val
)
315 * (volatile unsigned char *) (lith
->page0
+ off
) = val
;
318 /*****************************************************************************/
319 /* High Level Lithium Access */
324 * Lithium has two dedicated DMA channels for audio. They are known
325 * as comm1 and comm2 (communication areas 1 and 2). Comm1 is for
326 * input, and comm2 is for output. Each is controlled by three
327 * registers: BASE (base address), CFG (config) and CCTL
330 * Each DMA channel points to a physically contiguous ring buffer in
331 * main memory of up to 8 Kbytes. (This driver always uses 8 Kb.)
332 * There are three pointers into the ring buffer: read, write, and
333 * trigger. The pointers are 8 bits each. Each pointer points to
334 * 32-byte "chunks" of data. The DMA engine moves 32 bytes at a time,
335 * so there is no finer-granularity control.
337 * In comm1, the hardware updates the write ptr, and software updates
338 * the read ptr. In comm2, it's the opposite: hardware updates the
339 * read ptr, and software updates the write ptr. I designate the
340 * hardware-updated ptr as the hwptr, and the software-updated ptr as
343 * The trigger ptr and trigger mask are used to trigger interrupts.
344 * From the Lithium spec, section 5.6.8, revision of 12/15/1998:
348 * A three bit wide field that represents a power of two mask
349 * that is used whenever the trigger pointer is compared to its
350 * respective read or write pointer. A value of zero here
351 * implies a mask of 0xFF and a value of seven implies a mask
352 * 0x01. This value can be used to sub-divide the ring buffer
353 * into pie sections so that interrupts monitor the progress of
354 * hardware from section to section.
356 * My interpretation of that is, whenever the hw ptr is updated, it is
357 * compared with the trigger ptr, and the result is masked by the
358 * trigger mask. (Actually, by the complement of the trigger mask.)
359 * If the result is zero, an interrupt is triggered. I.e., interrupt
360 * if ((hwptr & ~mask) == (trptr & ~mask)). The mask is formed from
361 * the trigger register value as mask = (1 << (8 - tmreg)) - 1.
363 * In yet different words, setting tmreg to 0 causes an interrupt after
364 * every 256 DMA chunks (8192 bytes) or once per traversal of the
365 * ring buffer. Setting it to 7 caues an interrupt every 2 DMA chunks
366 * (64 bytes) or 128 times per traversal of the ring buffer.
369 /* Lithium register offsets and bit definitions */
371 #define LI_HOST_CONTROLLER 0x000
372 # define LI_HC_RESET 0x00008000
373 # define LI_HC_LINK_ENABLE 0x00004000
374 # define LI_HC_LINK_FAILURE 0x00000004
375 # define LI_HC_LINK_CODEC 0x00000002
376 # define LI_HC_LINK_READY 0x00000001
378 #define LI_INTR_STATUS 0x010
379 #define LI_INTR_MASK 0x014
380 # define LI_INTR_LINK_ERR 0x00008000
381 # define LI_INTR_COMM2_TRIG 0x00000008
382 # define LI_INTR_COMM2_UNDERFLOW 0x00000004
383 # define LI_INTR_COMM1_TRIG 0x00000002
384 # define LI_INTR_COMM1_OVERFLOW 0x00000001
386 #define LI_CODEC_COMMAND 0x018
387 # define LI_CC_BUSY 0x00008000
388 # define LI_CC_DIR 0x00000080
389 # define LI_CC_DIR_RD LI_CC_DIR
390 # define LI_CC_DIR_WR (!LI_CC_DIR)
391 # define LI_CC_ADDR_MASK 0x0000007F
393 #define LI_CODEC_DATA 0x01C
395 #define LI_COMM1_BASE 0x100
396 #define LI_COMM1_CTL 0x104
397 # define LI_CCTL_RESET 0x80000000
398 # define LI_CCTL_SIZE 0x70000000
399 # define LI_CCTL_DMA_ENABLE 0x08000000
400 # define LI_CCTL_TMASK 0x07000000 /* trigger mask */
401 # define LI_CCTL_TPTR 0x00FF0000 /* trigger pointer */
402 # define LI_CCTL_RPTR 0x0000FF00
403 # define LI_CCTL_WPTR 0x000000FF
404 #define LI_COMM1_CFG 0x108
405 # define LI_CCFG_LOCK 0x00008000
406 # define LI_CCFG_SLOT 0x00000070
407 # define LI_CCFG_DIRECTION 0x00000008
408 # define LI_CCFG_DIR_IN (!LI_CCFG_DIRECTION)
409 # define LI_CCFG_DIR_OUT LI_CCFG_DIRECTION
410 # define LI_CCFG_MODE 0x00000004
411 # define LI_CCFG_MODE_MONO (!LI_CCFG_MODE)
412 # define LI_CCFG_MODE_STEREO LI_CCFG_MODE
413 # define LI_CCFG_FORMAT 0x00000003
414 # define LI_CCFG_FMT_8BIT 0x00000000
415 # define LI_CCFG_FMT_16BIT 0x00000001
416 #define LI_COMM2_BASE 0x10C
417 #define LI_COMM2_CTL 0x110
418 /* bit definitions are the same as LI_COMM1_CTL */
419 #define LI_COMM2_CFG 0x114
420 /* bit definitions are the same as LI_COMM1_CFG */
422 #define LI_UST_LOW 0x200 /* 64-bit Unadjusted System Time is */
423 #define LI_UST_HIGH 0x204 /* microseconds since boot */
425 #define LI_AUDIO1_UST 0x300 /* UST-MSC pairs */
426 #define LI_AUDIO1_MSC 0x304 /* MSC (Media Stream Counter) */
427 #define LI_AUDIO2_UST 0x308 /* counts samples actually */
428 #define LI_AUDIO2_MSC 0x30C /* processed as of time UST */
431 * Lithium's DMA engine operates on chunks of 32 bytes. We call that
435 #define DMACHUNK_SHIFT 5
436 #define DMACHUNK_SIZE (1 << DMACHUNK_SHIFT)
437 #define BYTES_TO_CHUNKS(bytes) ((bytes) >> DMACHUNK_SHIFT)
438 #define CHUNKS_TO_BYTES(chunks) ((chunks) << DMACHUNK_SHIFT)
441 * Two convenient macros to shift bitfields into/out of position.
443 * Observe that (mask & -mask) is (1 << low_set_bit_of(mask)).
444 * As long as mask is constant, we trust the compiler will change the
445 * multipy and divide into shifts.
448 #define SHIFT_FIELD(val, mask) (((val) * ((mask) & -(mask))) & (mask))
449 #define UNSHIFT_FIELD(val, mask) (((val) & (mask)) / ((mask) & -(mask)))
452 * dma_chan_desc is invariant information about a Lithium
453 * DMA channel. There are two instances, li_comm1 and li_comm2.
455 * Note that the CCTL register fields are write ptr and read ptr, but what
456 * we care about are which pointer is updated by software and which by
460 typedef struct dma_chan_desc
{
468 unsigned long swptrmask
;
470 int direction
; /* LI_CCTL_DIR_IN/OUT */
473 static const dma_chan_desc_t li_comm1
= {
474 LI_COMM1_BASE
, /* base register offset */
475 LI_COMM1_CFG
, /* config register offset */
476 LI_COMM1_CTL
, /* control register offset */
477 LI_COMM1_CTL
+ 0, /* hw ptr reg offset (write ptr) */
478 LI_COMM1_CTL
+ 1, /* sw ptr reg offset (read ptr) */
479 LI_AUDIO1_UST
, /* ust reg offset */
480 LI_AUDIO1_MSC
, /* msc reg offset */
481 LI_CCTL_RPTR
, /* sw ptr bitmask in ctlval */
482 2, /* ad1843 serial slot */
483 LI_CCFG_DIR_IN
/* direction */
486 static const dma_chan_desc_t li_comm2
= {
487 LI_COMM2_BASE
, /* base register offset */
488 LI_COMM2_CFG
, /* config register offset */
489 LI_COMM2_CTL
, /* control register offset */
490 LI_COMM2_CTL
+ 1, /* hw ptr reg offset (read ptr) */
491 LI_COMM2_CTL
+ 0, /* sw ptr reg offset (writr ptr) */
492 LI_AUDIO2_UST
, /* ust reg offset */
493 LI_AUDIO2_MSC
, /* msc reg offset */
494 LI_CCTL_WPTR
, /* sw ptr bitmask in ctlval */
495 2, /* ad1843 serial slot */
496 LI_CCFG_DIR_OUT
/* direction */
500 * dma_chan is variable information about a Lithium DMA channel.
502 * The desc field points to invariant information.
503 * The lith field points to a lithium_t which is passed
504 * to li_read* and li_write* to access the registers.
505 * The *val fields shadow the lithium registers' contents.
508 typedef struct dma_chan
{
509 const dma_chan_desc_t
*desc
;
511 unsigned long baseval
;
512 unsigned long cfgval
;
513 unsigned long ctlval
;
517 * ustmsc is a UST/MSC pair (Unadjusted System Time/Media Stream Counter).
518 * UST is time in microseconds since the system booted, and MSC is a
519 * counter that increments with every audio sample.
522 typedef struct ustmsc
{
523 unsigned long long ust
;
528 * li_ad1843_wait waits until lithium says the AD1843 register
529 * exchange is not busy. Returns 0 on success, -EBUSY on timeout.
531 * Locking: must be called with lithium_lock held.
534 static int li_ad1843_wait(lithium_t
*lith
)
536 unsigned long later
= jiffies
+ 2;
537 while (li_readl(lith
, LI_CODEC_COMMAND
) & LI_CC_BUSY
)
538 if (jiffies
>= later
)
544 * li_read_ad1843_reg returns the current contents of a 16 bit AD1843 register.
546 * Returns unsigned register value on success, -errno on failure.
549 static int li_read_ad1843_reg(lithium_t
*lith
, int reg
)
553 ASSERT(!in_interrupt());
554 spin_lock(&lith
->lock
);
556 val
= li_ad1843_wait(lith
);
558 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_RD
| reg
);
559 val
= li_ad1843_wait(lith
);
562 val
= li_readl(lith
, LI_CODEC_DATA
);
564 spin_unlock(&lith
->lock
);
566 DBGXV("li_read_ad1843_reg(lith=0x%p, reg=%d) returns 0x%04x\n",
573 * li_write_ad1843_reg writes the specified value to a 16 bit AD1843 register.
576 static void li_write_ad1843_reg(lithium_t
*lith
, int reg
, int newval
)
578 spin_lock(&lith
->lock
);
580 if (li_ad1843_wait(lith
) == 0) {
581 li_writel(lith
, LI_CODEC_DATA
, newval
);
582 li_writel(lith
, LI_CODEC_COMMAND
, LI_CC_DIR_WR
| reg
);
585 spin_unlock(&lith
->lock
);
589 * li_setup_dma calculates all the register settings for DMA in a particular
590 * mode. It takes too many arguments.
593 static void li_setup_dma(dma_chan_t
*chan
,
594 const dma_chan_desc_t
*desc
,
596 unsigned long buffer_paddr
,
602 unsigned long mode
, format
;
603 unsigned long size
, tmask
;
605 DBGEV("(chan=0x%p, desc=0x%p, lith=0x%p, buffer_paddr=0x%lx, "
606 "bufshift=%d, fragshift=%d, channels=%d, sampsize=%d)\n",
607 chan
, desc
, lith
, buffer_paddr
,
608 bufshift
, fragshift
, channels
, sampsize
);
610 /* Reset the channel first. */
612 li_writel(lith
, desc
->ctlreg
, LI_CCTL_RESET
);
614 ASSERT(channels
== 1 || channels
== 2);
616 mode
= LI_CCFG_MODE_STEREO
;
618 mode
= LI_CCFG_MODE_MONO
;
619 ASSERT(sampsize
== 1 || sampsize
== 2);
621 format
= LI_CCFG_FMT_16BIT
;
623 format
= LI_CCFG_FMT_8BIT
;
628 * Lithium DMA address register takes a 40-bit physical
629 * address, right-shifted by 8 so it fits in 32 bits. Bit 37
630 * must be set -- it enables cache coherence.
633 ASSERT(!(buffer_paddr
& 0xFF));
634 chan
->baseval
= (buffer_paddr
>> 8) | 1 << (37 - 8);
636 chan
->cfgval
= (!LI_CCFG_LOCK
|
637 SHIFT_FIELD(desc
->ad1843_slot
, LI_CCFG_SLOT
) |
643 tmask
= 13 - fragshift
; /* See Lithium DMA Notes above. */
644 ASSERT(size
>= 2 && size
<= 7);
645 ASSERT(tmask
>= 1 && tmask
<= 7);
646 chan
->ctlval
= (!LI_CCTL_RESET
|
647 SHIFT_FIELD(size
, LI_CCTL_SIZE
) |
648 !LI_CCTL_DMA_ENABLE
|
649 SHIFT_FIELD(tmask
, LI_CCTL_TMASK
) |
650 SHIFT_FIELD(0, LI_CCTL_TPTR
));
652 DBGPV("basereg 0x%x = 0x%lx\n", desc
->basereg
, chan
->baseval
);
653 DBGPV("cfgreg 0x%x = 0x%lx\n", desc
->cfgreg
, chan
->cfgval
);
654 DBGPV("ctlreg 0x%x = 0x%lx\n", desc
->ctlreg
, chan
->ctlval
);
656 li_writel(lith
, desc
->basereg
, chan
->baseval
);
657 li_writel(lith
, desc
->cfgreg
, chan
->cfgval
);
658 li_writel(lith
, desc
->ctlreg
, chan
->ctlval
);
663 static void li_shutdown_dma(dma_chan_t
*chan
)
665 lithium_t
*lith
= chan
->lith
;
666 caddr_t lith1
= lith
->page1
;
668 DBGEV("(chan=0x%p)\n", chan
);
670 chan
->ctlval
&= ~LI_CCTL_DMA_ENABLE
;
671 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
672 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
675 * Offset 0x500 on Lithium page 1 is an undocumented,
676 * unsupported register that holds the zero sample value.
677 * Lithium is supposed to output zero samples when DMA is
678 * inactive, and repeat the last sample when DMA underflows.
679 * But it has a bug, where, after underflow occurs, the zero
680 * sample is not reset.
682 * I expect this to break in a future rev of Lithium.
685 if (lith1
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
)
686 * (volatile unsigned long *) (lith1
+ 0x500) = 0;
690 * li_activate_dma always starts dma at the beginning of the buffer.
692 * N.B., these may be called from interrupt.
695 static __inline__
void li_activate_dma(dma_chan_t
*chan
)
697 chan
->ctlval
|= LI_CCTL_DMA_ENABLE
;
698 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
699 li_writel(chan
->lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
702 static void li_deactivate_dma(dma_chan_t
*chan
)
704 lithium_t
*lith
= chan
->lith
;
705 caddr_t lith2
= lith
->page2
;
707 chan
->ctlval
&= ~(LI_CCTL_DMA_ENABLE
| LI_CCTL_RPTR
| LI_CCTL_WPTR
);
708 DBGPV("ctlval = 0x%lx\n", chan
->ctlval
);
709 DBGPV("ctlreg 0x%x = 0x%lx\n", chan
->desc
->ctlreg
, chan
->ctlval
);
710 li_writel(lith
, chan
->desc
->ctlreg
, chan
->ctlval
);
713 * Offsets 0x98 and 0x9C on Lithium page 2 are undocumented,
714 * unsupported registers that are internal copies of the DMA
715 * read and write pointers. Because of a Lithium bug, these
716 * registers aren't zeroed correctly when DMA is shut off. So
717 * we whack them directly.
719 * I expect this to break in a future rev of Lithium.
722 if (lith2
&& chan
->desc
->direction
== LI_CCFG_DIR_OUT
) {
723 * (volatile unsigned long *) (lith2
+ 0x98) = 0;
724 * (volatile unsigned long *) (lith2
+ 0x9C) = 0;
729 * read/write the ring buffer pointers. These routines' arguments and results
730 * are byte offsets from the beginning of the ring buffer.
733 static __inline__
int li_read_swptr(dma_chan_t
*chan
)
735 const unsigned long mask
= chan
->desc
->swptrmask
;
737 return CHUNKS_TO_BYTES(UNSHIFT_FIELD(chan
->ctlval
, mask
));
740 static __inline__
int li_read_hwptr(dma_chan_t
*chan
)
742 return CHUNKS_TO_BYTES(li_readb(chan
->lith
, chan
->desc
->hwptrreg
));
745 static __inline__
void li_write_swptr(dma_chan_t
*chan
, int val
)
747 const unsigned long mask
= chan
->desc
->swptrmask
;
749 ASSERT(!(val
& ~CHUNKS_TO_BYTES(0xFF)));
750 val
= BYTES_TO_CHUNKS(val
);
751 chan
->ctlval
= (chan
->ctlval
& ~mask
) | SHIFT_FIELD(val
, mask
);
752 li_writeb(chan
->lith
, chan
->desc
->swptrreg
, val
);
755 /* li_read_USTMSC() returns a UST/MSC pair for the given channel. */
757 static void li_read_USTMSC(dma_chan_t
*chan
, ustmsc_t
*ustmsc
)
759 lithium_t
*lith
= chan
->lith
;
760 const dma_chan_desc_t
*desc
= chan
->desc
;
761 unsigned long now_low
, now_high0
, now_high1
, chan_ust
;
763 spin_lock(&lith
->lock
);
766 * retry until we do all five reads without the
767 * high word changing. (High word increments
768 * every 2^32 microseconds, i.e., not often)
771 now_high0
= li_readl(lith
, LI_UST_HIGH
);
772 now_low
= li_readl(lith
, LI_UST_LOW
);
775 * Lithium guarantees these two reads will be
776 * atomic -- ust will not increment after msc
780 ustmsc
->msc
= li_readl(lith
, desc
->mscreg
);
781 chan_ust
= li_readl(lith
, desc
->ustreg
);
783 now_high1
= li_readl(lith
, LI_UST_HIGH
);
784 } while (now_high0
!= now_high1
);
786 spin_unlock(&lith
->lock
);
787 ustmsc
->ust
= ((unsigned long long) now_high0
<< 32 | chan_ust
);
790 static void li_enable_interrupts(lithium_t
*lith
, unsigned int mask
)
792 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
794 /* clear any already-pending interrupts. */
796 li_writel(lith
, LI_INTR_STATUS
, mask
);
798 /* enable the interrupts. */
800 mask
|= li_readl(lith
, LI_INTR_MASK
);
801 li_writel(lith
, LI_INTR_MASK
, mask
);
804 static void li_disable_interrupts(lithium_t
*lith
, unsigned int mask
)
806 unsigned int keepmask
;
808 DBGEV("(lith=0x%p, mask=0x%x)\n", lith
, mask
);
810 /* disable the interrupts */
812 keepmask
= li_readl(lith
, LI_INTR_MASK
) & ~mask
;
813 li_writel(lith
, LI_INTR_MASK
, keepmask
);
815 /* clear any pending interrupts. */
817 li_writel(lith
, LI_INTR_STATUS
, mask
);
820 /* Get the interrupt status and clear all pending interrupts. */
822 static unsigned int li_get_clear_intr_status(lithium_t
*lith
)
826 status
= li_readl(lith
, LI_INTR_STATUS
);
827 li_writel(lith
, LI_INTR_STATUS
, ~0);
828 return status
& li_readl(lith
, LI_INTR_MASK
);
831 static int li_init(lithium_t
*lith
)
833 /* 1. System power supplies stabilize. */
835 /* 2. Assert the ~RESET signal. */
837 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_RESET
);
840 /* 3. Deassert the ~RESET signal and enter a wait period to allow
841 the AD1843 internal clocks and the external crystal oscillator
844 li_writel(lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
850 /*****************************************************************************/
854 * AD1843 bitfield definitions. All are named as in the AD1843 data
855 * sheet, with ad1843_ prepended and individual bit numbers removed.
857 * E.g., bits LSS0 through LSS2 become ad1843_LSS.
859 * Only the bitfields we need are defined.
862 typedef struct ad1843_bitfield
{
868 static const ad1843_bitfield_t
869 ad1843_PDNO
= { 0, 14, 1 }, /* Converter Power-Down Flag */
870 ad1843_INIT
= { 0, 15, 1 }, /* Clock Initialization Flag */
871 ad1843_RIG
= { 2, 0, 4 }, /* Right ADC Input Gain */
872 ad1843_RMGE
= { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
873 ad1843_RSS
= { 2, 5, 3 }, /* Right ADC Source Select */
874 ad1843_LIG
= { 2, 8, 4 }, /* Left ADC Input Gain */
875 ad1843_LMGE
= { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
876 ad1843_LSS
= { 2, 13, 3 }, /* Left ADC Source Select */
877 ad1843_RX1M
= { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
878 ad1843_RX1MM
= { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
879 ad1843_LX1M
= { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
880 ad1843_LX1MM
= { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
881 ad1843_RX2M
= { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
882 ad1843_RX2MM
= { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
883 ad1843_LX2M
= { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
884 ad1843_LX2MM
= { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
885 ad1843_RMCM
= { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
886 ad1843_RMCMM
= { 7, 7, 1 }, /* Right Mic Mix Mute */
887 ad1843_LMCM
= { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
888 ad1843_LMCMM
= { 7, 15, 1 }, /* Left Mic Mix Mute */
889 ad1843_HPOS
= { 8, 4, 1 }, /* Headphone Output Voltage Swing */
890 ad1843_HPOM
= { 8, 5, 1 }, /* Headphone Output Mute */
891 ad1843_RDA1G
= { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
892 ad1843_RDA1GM
= { 9, 7, 1 }, /* Right DAC1 Analog Mute */
893 ad1843_LDA1G
= { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
894 ad1843_LDA1GM
= { 9, 15, 1 }, /* Left DAC1 Analog Mute */
895 ad1843_RDA1AM
= { 11, 7, 1 }, /* Right DAC1 Digital Mute */
896 ad1843_LDA1AM
= { 11, 15, 1 }, /* Left DAC1 Digital Mute */
897 ad1843_ADLC
= { 15, 0, 2 }, /* ADC Left Sample Rate Source */
898 ad1843_ADRC
= { 15, 2, 2 }, /* ADC Right Sample Rate Source */
899 ad1843_DA1C
= { 15, 8, 2 }, /* DAC1 Sample Rate Source */
900 ad1843_C1C
= { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
901 ad1843_C2C
= { 20, 0, 16 }, /* Clock 1 Sample Rate Select */
902 ad1843_DAADL
= { 25, 4, 2 }, /* Digital ADC Left Source Select */
903 ad1843_DAADR
= { 25, 6, 2 }, /* Digital ADC Right Source Select */
904 ad1843_DRSFLT
= { 25, 15, 1 }, /* Digital Reampler Filter Mode */
905 ad1843_ADLF
= { 26, 0, 2 }, /* ADC Left Channel Data Format */
906 ad1843_ADRF
= { 26, 2, 2 }, /* ADC Right Channel Data Format */
907 ad1843_ADTLK
= { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
908 ad1843_SCF
= { 26, 7, 1 }, /* SCLK Frequency Select */
909 ad1843_DA1F
= { 26, 8, 2 }, /* DAC1 Data Format Select */
910 ad1843_DA1SM
= { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
911 ad1843_ADLEN
= { 27, 0, 1 }, /* ADC Left Channel Enable */
912 ad1843_ADREN
= { 27, 1, 1 }, /* ADC Right Channel Enable */
913 ad1843_AAMEN
= { 27, 4, 1 }, /* Analog to Analog Mix Enable */
914 ad1843_ANAEN
= { 27, 7, 1 }, /* Analog Channel Enable */
915 ad1843_DA1EN
= { 27, 8, 1 }, /* DAC1 Enable */
916 ad1843_DA2EN
= { 27, 9, 1 }, /* DAC2 Enable */
917 ad1843_C1EN
= { 28, 11, 1 }, /* Clock Generator 1 Enable */
918 ad1843_C2EN
= { 28, 12, 1 }, /* Clock Generator 2 Enable */
919 ad1843_PDNI
= { 28, 15, 1 }; /* Converter Power Down */
922 * The various registers of the AD1843 use three different formats for
923 * specifying gain. The ad1843_gain structure parameterizes the
927 typedef struct ad1843_gain
{
929 int negative
; /* nonzero if gain is negative. */
930 const ad1843_bitfield_t
*lfield
;
931 const ad1843_bitfield_t
*rfield
;
935 static const ad1843_gain_t ad1843_gain_RECLEV
936 = { 0, &ad1843_LIG
, &ad1843_RIG
};
937 static const ad1843_gain_t ad1843_gain_LINE
938 = { 1, &ad1843_LX1M
, &ad1843_RX1M
};
939 static const ad1843_gain_t ad1843_gain_CD
940 = { 1, &ad1843_LX2M
, &ad1843_RX2M
};
941 static const ad1843_gain_t ad1843_gain_MIC
942 = { 1, &ad1843_LMCM
, &ad1843_RMCM
};
943 static const ad1843_gain_t ad1843_gain_PCM
944 = { 1, &ad1843_LDA1G
, &ad1843_RDA1G
};
946 /* read the current value of an AD1843 bitfield. */
948 static int ad1843_read_bits(lithium_t
*lith
, const ad1843_bitfield_t
*field
)
950 int w
= li_read_ad1843_reg(lith
, field
->reg
);
951 int val
= w
>> field
->lo_bit
& ((1 << field
->nbits
) - 1);
953 DBGXV("ad1843_read_bits(lith=0x%p, field->{%d %d %d}) returns 0x%x\n",
954 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, val
);
960 * write a new value to an AD1843 bitfield and return the old value.
963 static int ad1843_write_bits(lithium_t
*lith
,
964 const ad1843_bitfield_t
*field
,
967 int w
= li_read_ad1843_reg(lith
, field
->reg
);
968 int mask
= ((1 << field
->nbits
) - 1) << field
->lo_bit
;
969 int oldval
= (w
& mask
) >> field
->lo_bit
;
970 int newbits
= (newval
<< field
->lo_bit
) & mask
;
971 w
= (w
& ~mask
) | newbits
;
972 (void) li_write_ad1843_reg(lith
, field
->reg
, w
);
974 DBGXV("ad1843_write_bits(lith=0x%p, field->{%d %d %d}, val=0x%x) "
976 lith
, field
->reg
, field
->lo_bit
, field
->nbits
, newval
,
983 * ad1843_read_multi reads multiple bitfields from the same AD1843
984 * register. It uses a single read cycle to do it. (Reading the
985 * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
990 * ad1843_read_multi(lith, nfields,
991 * &ad1843_FIELD1, &val1,
992 * &ad1843_FIELD2, &val2, ...);
995 static void ad1843_read_multi(lithium_t
*lith
, int argcount
, ...)
998 const ad1843_bitfield_t
*fp
;
999 int w
= 0, mask
, *value
, reg
= -1;
1001 va_start(ap
, argcount
);
1002 while (--argcount
>= 0) {
1003 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
1004 value
= va_arg(ap
, int *);
1007 w
= li_read_ad1843_reg(lith
, reg
);
1009 ASSERT(reg
== fp
->reg
);
1010 mask
= (1 << fp
->nbits
) - 1;
1011 *value
= w
>> fp
->lo_bit
& mask
;
1017 * ad1843_write_multi stores multiple bitfields into the same AD1843
1018 * register. It uses one read and one write cycle to do it.
1022 * ad1843_write_multi(lith, nfields,
1023 * &ad1843_FIELD1, val1,
1024 * &ad1843_FIELF2, val2, ...);
1027 static void ad1843_write_multi(lithium_t
*lith
, int argcount
, ...)
1031 const ad1843_bitfield_t
*fp
;
1033 int w
, m
, mask
, bits
;
1039 va_start(ap
, argcount
);
1040 while (--argcount
>= 0) {
1041 fp
= va_arg(ap
, const ad1843_bitfield_t
*);
1042 value
= va_arg(ap
, int);
1045 ASSERT(fp
->reg
== reg
);
1046 m
= ((1 << fp
->nbits
) - 1) << fp
->lo_bit
;
1048 bits
|= (value
<< fp
->lo_bit
) & m
;
1051 ASSERT(!(bits
& ~mask
));
1053 w
= li_read_ad1843_reg(lith
, reg
);
1056 w
= (w
& ~mask
) | bits
;
1057 (void) li_write_ad1843_reg(lith
, reg
, w
);
1061 * ad1843_get_gain reads the specified register and extracts the gain value
1062 * using the supplied gain type. It returns the gain in OSS format.
1065 static int ad1843_get_gain(lithium_t
*lith
, const ad1843_gain_t
*gp
)
1068 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1070 ad1843_read_multi(lith
, 2, gp
->lfield
, &lg
, gp
->rfield
, &rg
);
1075 lg
= (lg
* 100 + (mask
>> 1)) / mask
;
1076 rg
= (rg
* 100 + (mask
>> 1)) / mask
;
1077 return lg
<< 0 | rg
<< 8;
1081 * Set an audio channel's gain. Converts from OSS format to AD1843's
1084 * Returns the new gain, which may be lower than the old gain.
1087 static int ad1843_set_gain(lithium_t
*lith
,
1088 const ad1843_gain_t
*gp
,
1091 unsigned short mask
= (1 << gp
->lfield
->nbits
) - 1;
1093 int lg
= newval
>> 0 & 0xFF;
1094 int rg
= newval
>> 8;
1095 if (lg
< 0 || lg
> 100 || rg
< 0 || rg
> 100)
1097 lg
= (lg
* mask
+ (mask
>> 1)) / 100;
1098 rg
= (rg
* mask
+ (mask
>> 1)) / 100;
1103 ad1843_write_multi(lith
, 2, gp
->lfield
, lg
, gp
->rfield
, rg
);
1104 return ad1843_get_gain(lith
, gp
);
1107 /* Returns the current recording source, in OSS format. */
1109 static int ad1843_get_recsrc(lithium_t
*lith
)
1111 int ls
= ad1843_read_bits(lith
, &ad1843_LSS
);
1115 return SOUND_MASK_MIC
;
1117 return SOUND_MASK_LINE
;
1119 return SOUND_MASK_CD
;
1121 return SOUND_MASK_PCM
;
1129 * Enable/disable digital resample mode in the AD1843.
1131 * The AD1843 requires that ADL, ADR, DA1 and DA2 be powered down
1132 * while switching modes. So we save DA1's state (DA2's state is not
1133 * interesting), power them down, switch into/out of resample mode,
1134 * power them up, and restore state.
1136 * This will cause audible glitches if D/A or A/D is going on, so the
1137 * driver disallows that (in mixer_write_ioctl()).
1139 * The open question is, is this worth doing? I'm leaving it in,
1140 * because it's written, but...
1143 static void ad1843_set_resample_mode(lithium_t
*lith
, int onoff
)
1145 /* Save DA1 mute and gain (addr 9 is DA1 analog gain/attenuation) */
1146 int save_da1
= li_read_ad1843_reg(lith
, 9);
1148 /* Power down A/D and D/A. */
1149 ad1843_write_multi(lith
, 4,
1156 ASSERT(onoff
== 0 || onoff
== 1);
1157 ad1843_write_bits(lith
, &ad1843_DRSFLT
, onoff
);
1159 /* Power up A/D and D/A. */
1160 ad1843_write_multi(lith
, 3,
1165 /* Restore DA1 mute and gain. */
1166 li_write_ad1843_reg(lith
, 9, save_da1
);
1170 * Set recording source. Arg newsrc specifies an OSS channel mask.
1172 * The complication is that when we switch into/out of loopback mode
1173 * (i.e., src = SOUND_MASK_PCM), we change the AD1843 into/out of
1174 * digital resampling mode.
1176 * Returns newsrc on success, -errno on failure.
1179 static int ad1843_set_recsrc(lithium_t
*lith
, int newsrc
)
1185 case SOUND_MASK_PCM
:
1189 case SOUND_MASK_MIC
:
1193 case SOUND_MASK_LINE
:
1204 oldbits
= ad1843_read_bits(lith
, &ad1843_LSS
);
1205 if (newsrc
== SOUND_MASK_PCM
&& oldbits
!= 6) {
1206 DBGP("enabling digital resample mode\n");
1207 ad1843_set_resample_mode(lith
, 1);
1208 ad1843_write_multi(lith
, 2,
1211 } else if (newsrc
!= SOUND_MASK_PCM
&& oldbits
== 6) {
1212 DBGP("disabling digital resample mode\n");
1213 ad1843_set_resample_mode(lith
, 0);
1214 ad1843_write_multi(lith
, 2,
1218 ad1843_write_multi(lith
, 2, &ad1843_LSS
, bits
, &ad1843_RSS
, bits
);
1223 * Return current output sources, in OSS format.
1226 static int ad1843_get_outsrc(lithium_t
*lith
)
1228 int pcm
, line
, mic
, cd
;
1230 pcm
= ad1843_read_bits(lith
, &ad1843_LDA1GM
) ? 0 : SOUND_MASK_PCM
;
1231 line
= ad1843_read_bits(lith
, &ad1843_LX1MM
) ? 0 : SOUND_MASK_LINE
;
1232 cd
= ad1843_read_bits(lith
, &ad1843_LX2MM
) ? 0 : SOUND_MASK_CD
;
1233 mic
= ad1843_read_bits(lith
, &ad1843_LMCMM
) ? 0 : SOUND_MASK_MIC
;
1235 return pcm
| line
| cd
| mic
;
1239 * Set output sources. Arg is a mask of active sources in OSS format.
1241 * Returns source mask on success, -errno on failure.
1244 static int ad1843_set_outsrc(lithium_t
*lith
, int mask
)
1246 int pcm
, line
, mic
, cd
;
1248 if (mask
& ~(SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1249 SOUND_MASK_CD
| SOUND_MASK_MIC
))
1251 pcm
= (mask
& SOUND_MASK_PCM
) ? 0 : 1;
1252 line
= (mask
& SOUND_MASK_LINE
) ? 0 : 1;
1253 mic
= (mask
& SOUND_MASK_MIC
) ? 0 : 1;
1254 cd
= (mask
& SOUND_MASK_CD
) ? 0 : 1;
1256 ad1843_write_multi(lith
, 2, &ad1843_LDA1GM
, pcm
, &ad1843_RDA1GM
, pcm
);
1257 ad1843_write_multi(lith
, 2, &ad1843_LX1MM
, line
, &ad1843_RX1MM
, line
);
1258 ad1843_write_multi(lith
, 2, &ad1843_LX2MM
, cd
, &ad1843_RX2MM
, cd
);
1259 ad1843_write_multi(lith
, 2, &ad1843_LMCMM
, mic
, &ad1843_RMCMM
, mic
);
1264 /* Setup ad1843 for D/A conversion. */
1266 static void ad1843_setup_dac(lithium_t
*lith
,
1271 int ad_fmt
= 0, ad_mode
= 0;
1273 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1274 lith
, framerate
, fmt
, channels
);
1277 case AFMT_S8
: ad_fmt
= 1; break;
1278 case AFMT_U8
: ad_fmt
= 1; break;
1279 case AFMT_S16_LE
: ad_fmt
= 1; break;
1280 case AFMT_MU_LAW
: ad_fmt
= 2; break;
1281 case AFMT_A_LAW
: ad_fmt
= 3; break;
1286 case 2: ad_mode
= 0; break;
1287 case 1: ad_mode
= 1; break;
1291 DBGPV("ad_mode = %d, ad_fmt = %d\n", ad_mode
, ad_fmt
);
1292 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1293 ad1843_write_bits(lith
, &ad1843_C1C
, framerate
);
1294 ad1843_write_multi(lith
, 2,
1295 &ad1843_DA1SM
, ad_mode
, &ad1843_DA1F
, ad_fmt
);
1298 static void ad1843_shutdown_dac(lithium_t
*lith
)
1300 ad1843_write_bits(lith
, &ad1843_DA1F
, 1);
1303 static void ad1843_setup_adc(lithium_t
*lith
, int framerate
, int fmt
, int channels
)
1307 DBGEV("(lith=0x%p, framerate=%d, fmt=%d, channels=%d)\n",
1308 lith
, framerate
, fmt
, channels
);
1311 case AFMT_S8
: da_fmt
= 1; break;
1312 case AFMT_U8
: da_fmt
= 1; break;
1313 case AFMT_S16_LE
: da_fmt
= 1; break;
1314 case AFMT_MU_LAW
: da_fmt
= 2; break;
1315 case AFMT_A_LAW
: da_fmt
= 3; break;
1319 DBGPV("da_fmt = %d\n", da_fmt
);
1320 ASSERT(framerate
>= 4000 && framerate
<= 49000);
1321 ad1843_write_bits(lith
, &ad1843_C2C
, framerate
);
1322 ad1843_write_multi(lith
, 2,
1323 &ad1843_ADLF
, da_fmt
, &ad1843_ADRF
, da_fmt
);
1326 static void ad1843_shutdown_adc(lithium_t
*lith
)
1332 * Fully initialize the ad1843. As described in the AD1843 data
1333 * sheet, section "START-UP SEQUENCE". The numbered comments are
1334 * subsection headings from the data sheet. See the data sheet, pages
1335 * 52-54, for more info.
1337 * return 0 on success, -errno on failure. */
1339 static int __init
ad1843_init(lithium_t
*lith
)
1341 unsigned long later
;
1344 err
= li_init(lith
);
1348 if (ad1843_read_bits(lith
, &ad1843_INIT
) != 0) {
1349 printk(KERN_ERR
"vwsnd sound: AD1843 won't initialize\n");
1353 ad1843_write_bits(lith
, &ad1843_SCF
, 1);
1355 /* 4. Put the conversion resources into standby. */
1357 ad1843_write_bits(lith
, &ad1843_PDNI
, 0);
1358 later
= jiffies
+ HZ
/ 2; /* roughly half a second */
1360 while (ad1843_read_bits(lith
, &ad1843_PDNO
)) {
1361 if (jiffies
> later
) {
1363 "vwsnd audio: AD1843 won't power up\n");
1370 /* 5. Power up the clock generators and enable clock output pins. */
1372 ad1843_write_multi(lith
, 2, &ad1843_C1EN
, 1, &ad1843_C2EN
, 1);
1374 /* 6. Configure conversion resources while they are in standby. */
1376 /* DAC1 uses clock 1 as source, ADC uses clock 2. Always. */
1378 ad1843_write_multi(lith
, 3,
1383 /* 7. Enable conversion resources. */
1385 ad1843_write_bits(lith
, &ad1843_ADTLK
, 1);
1386 ad1843_write_multi(lith
, 5,
1393 /* 8. Configure conversion resources while they are enabled. */
1395 ad1843_write_bits(lith
, &ad1843_DA1C
, 1);
1397 /* Unmute all channels. */
1399 ad1843_set_outsrc(lith
,
1400 (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
1401 SOUND_MASK_MIC
| SOUND_MASK_CD
));
1402 ad1843_write_multi(lith
, 2, &ad1843_LDA1AM
, 0, &ad1843_RDA1AM
, 0);
1404 /* Set default recording source to Line In and set
1405 * mic gain to +20 dB.
1408 ad1843_set_recsrc(lith
, SOUND_MASK_LINE
);
1409 ad1843_write_multi(lith
, 2, &ad1843_LMGE
, 1, &ad1843_RMGE
, 1);
1411 /* Set Speaker Out level to +/- 4V and unmute it. */
1413 ad1843_write_multi(lith
, 2, &ad1843_HPOS
, 1, &ad1843_HPOM
, 0);
1418 /*****************************************************************************/
1421 #define READ_INTR_MASK (LI_INTR_COMM1_TRIG | LI_INTR_COMM1_OVERFLOW)
1422 #define WRITE_INTR_MASK (LI_INTR_COMM2_TRIG | LI_INTR_COMM2_UNDERFLOW)
1424 typedef enum vwsnd_port_swstate
{ /* software state */
1429 } vwsnd_port_swstate_t
;
1431 typedef enum vwsnd_port_hwstate
{ /* hardware state */
1434 } vwsnd_port_hwstate_t
;
1437 * These flags are read by ISR, but only written at baseline.
1440 typedef enum vwsnd_port_flags
{
1442 ERFLOWN
= 1 << 1, /* overflown or underflown */
1444 } vwsnd_port_flags_t
;
1447 * vwsnd_port is the per-port data structure. Each device has two
1448 * ports, one for input and one for output.
1452 * port->lock protects: hwstate, flags, swb_[iu]_avail.
1454 * devc->io_sema protects: swstate, sw_*, swb_[iu]_idx.
1456 * everything else is only written by open/release or
1457 * pcm_{setup,shutdown}(), which are serialized by a
1458 * combination of devc->open_sema and devc->io_sema.
1461 typedef struct vwsnd_port
{
1464 wait_queue_head_t queue
;
1465 vwsnd_port_swstate_t swstate
;
1466 vwsnd_port_hwstate_t hwstate
;
1467 vwsnd_port_flags_t flags
;
1474 unsigned int zero_word
; /* zero for the sample format */
1480 unsigned int hw_fragshift
;
1481 unsigned int hw_fragsize
;
1482 unsigned int hw_fragcount
;
1485 unsigned long hwbuf_paddr
;
1486 unsigned long hwbuf_vaddr
;
1487 caddr_t hwbuf
; /* hwbuf == hwbuf_vaddr */
1488 int hwbuf_max
; /* max bytes to preload */
1491 unsigned int swbuf_size
; /* size in bytes */
1492 unsigned int swb_u_idx
; /* index of next user byte */
1493 unsigned int swb_i_idx
; /* index of next intr byte */
1494 unsigned int swb_u_avail
; /* # bytes avail to user */
1495 unsigned int swb_i_avail
; /* # bytes avail to intr */
1507 /* vwsnd_dev is the per-device data structure. */
1509 typedef struct vwsnd_dev
{
1510 struct vwsnd_dev
*next_dev
;
1511 int audio_minor
; /* minor number of audio device */
1512 int mixer_minor
; /* minor number of mixer device */
1514 struct semaphore open_sema
;
1515 struct semaphore io_sema
;
1516 struct semaphore mix_sema
;
1518 wait_queue_head_t open_wait
;
1526 static vwsnd_dev_t
*vwsnd_dev_list
; /* linked list of all devices */
1528 static atomic_t vwsnd_use_count
= ATOMIC_INIT(0);
1530 # define INC_USE_COUNT (atomic_inc(&vwsnd_use_count))
1531 # define DEC_USE_COUNT (atomic_dec(&vwsnd_use_count))
1532 # define IN_USE (atomic_read(&vwsnd_use_count) != 0)
1535 * Lithium can only DMA multiples of 32 bytes. Its DMA buffer may
1536 * be up to 8 Kb. This driver always uses 8 Kb.
1538 * Memory bug workaround -- I'm not sure what's going on here, but
1539 * somehow pcm_copy_out() was triggering segv's going on to the next
1540 * page of the hw buffer. So, I make the hw buffer one size bigger
1541 * than we actually use. That way, the following page is allocated
1542 * and mapped, and no error. I suspect that something is broken
1543 * in Cobalt, but haven't really investigated. HBO is the actual
1544 * size of the buffer, and HWBUF_ORDER is what we allocate.
1547 #define HWBUF_SHIFT 13
1548 #define HWBUF_SIZE (1 << HWBUF_SHIFT)
1549 # define HBO (HWBUF_SHIFT > PAGE_SHIFT ? HWBUF_SHIFT - PAGE_SHIFT : 0)
1550 # define HWBUF_ORDER (HBO + 1) /* next size bigger */
1551 #define MIN_SPEED 4000
1552 #define MAX_SPEED 49000
1554 #define MIN_FRAGSHIFT (DMACHUNK_SHIFT + 1)
1555 #define MAX_FRAGSHIFT (PAGE_SHIFT)
1556 #define MIN_FRAGSIZE (1 << MIN_FRAGSHIFT)
1557 #define MAX_FRAGSIZE (1 << MAX_FRAGSHIFT)
1558 #define MIN_FRAGCOUNT(fragsize) 3
1559 #define MAX_FRAGCOUNT(fragsize) (32 * PAGE_SIZE / (fragsize))
1560 #define DEFAULT_FRAGSHIFT 12
1561 #define DEFAULT_FRAGCOUNT 16
1562 #define DEFAULT_SUBDIVSHIFT 0
1565 * The software buffer (swbuf) is a ring buffer shared between user
1566 * level and interrupt level. Each level owns some of the bytes in
1567 * the buffer, and may give bytes away by calling swb_inc_{u,i}().
1568 * User level calls _u for user, and interrupt level calls _i for
1571 * port->swb_{u,i}_avail is the number of bytes available to that level.
1573 * port->swb_{u,i}_idx is the index of the first available byte in the
1576 * Each level calls swb_inc_{u,i}() to atomically increment its index,
1577 * recalculate the number of bytes available for both sides, and
1578 * return the number of bytes available. Since each side can only
1579 * give away bytes, the other side can only increase the number of
1580 * bytes available to this side. Each side updates its own index
1581 * variable, swb_{u,i}_idx, so no lock is needed to read it.
1583 * To query the number of bytes available, call swb_inc_{u,i} with an
1584 * increment of zero.
1587 static __inline__
unsigned int __swb_inc_u(vwsnd_port_t
*port
, int inc
)
1590 port
->swb_u_idx
+= inc
;
1591 port
->swb_u_idx
%= port
->swbuf_size
;
1592 port
->swb_u_avail
-= inc
;
1593 port
->swb_i_avail
+= inc
;
1595 return port
->swb_u_avail
;
1598 static __inline__
unsigned int swb_inc_u(vwsnd_port_t
*port
, int inc
)
1600 unsigned long flags
;
1603 spin_lock_irqsave(&port
->lock
, flags
);
1605 ret
= __swb_inc_u(port
, inc
);
1607 spin_unlock_irqrestore(&port
->lock
, flags
);
1611 static __inline__
unsigned int __swb_inc_i(vwsnd_port_t
*port
, int inc
)
1614 port
->swb_i_idx
+= inc
;
1615 port
->swb_i_idx
%= port
->swbuf_size
;
1616 port
->swb_i_avail
-= inc
;
1617 port
->swb_u_avail
+= inc
;
1619 return port
->swb_i_avail
;
1622 static __inline__
unsigned int swb_inc_i(vwsnd_port_t
*port
, int inc
)
1624 unsigned long flags
;
1627 spin_lock_irqsave(&port
->lock
, flags
);
1629 ret
= __swb_inc_i(port
, inc
);
1631 spin_unlock_irqrestore(&port
->lock
, flags
);
1636 * pcm_setup - this routine initializes all port state after
1637 * mode-setting ioctls have been done, but before the first I/O is
1640 * Locking: called with devc->io_sema held.
1642 * Returns 0 on success, -errno on failure.
1645 static int pcm_setup(vwsnd_dev_t
*devc
,
1646 vwsnd_port_t
*rport
,
1647 vwsnd_port_t
*wport
)
1649 vwsnd_port_t
*aport
= rport
? rport
: wport
;
1651 unsigned int zero_word
;
1653 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1655 ASSERT(aport
!= NULL
);
1656 if (aport
->swbuf
!= NULL
)
1658 switch (aport
->sw_samplefmt
) {
1661 zero_word
= 0xFFFFFFFF ^ 0x80808080;
1666 zero_word
= 0xD5D5D5D5 ^ 0x80808080;
1671 zero_word
= 0x80808080;
1676 zero_word
= 0x00000000;
1681 zero_word
= 0x00000000;
1685 sample_size
= 0; /* prevent compiler warning */
1689 aport
->sample_size
= sample_size
;
1690 aport
->zero_word
= zero_word
;
1691 aport
->frame_size
= aport
->sw_channels
* aport
->sample_size
;
1692 aport
->hw_fragshift
= aport
->sw_fragshift
- aport
->sw_subdivshift
;
1693 aport
->hw_fragsize
= 1 << aport
->hw_fragshift
;
1694 aport
->hw_fragcount
= aport
->sw_fragcount
<< aport
->sw_subdivshift
;
1695 ASSERT(aport
->hw_fragsize
>= MIN_FRAGSIZE
);
1696 ASSERT(aport
->hw_fragsize
<= MAX_FRAGSIZE
);
1697 ASSERT(aport
->hw_fragcount
>= MIN_FRAGCOUNT(aport
->hw_fragsize
));
1698 ASSERT(aport
->hw_fragcount
<= MAX_FRAGCOUNT(aport
->hw_fragsize
));
1700 int hwfrags
, swfrags
;
1701 rport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1702 hwfrags
= rport
->hwbuf_max
>> aport
->hw_fragshift
;
1703 swfrags
= aport
->hw_fragcount
- hwfrags
;
1706 rport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1707 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1708 DBGPV("read hwbuf_max = %d, swbuf_size = %d\n",
1709 rport
->hwbuf_max
, rport
->swbuf_size
);
1712 int hwfrags
, swfrags
;
1713 int total_bytes
= aport
->hw_fragcount
* aport
->hw_fragsize
;
1714 wport
->hwbuf_max
= aport
->hwbuf_size
- DMACHUNK_SIZE
;
1715 if (wport
->hwbuf_max
> total_bytes
)
1716 wport
->hwbuf_max
= total_bytes
;
1717 hwfrags
= wport
->hwbuf_max
>> aport
->hw_fragshift
;
1718 DBGPV("hwfrags = %d\n", hwfrags
);
1719 swfrags
= aport
->hw_fragcount
- hwfrags
;
1722 wport
->swbuf_size
= swfrags
* aport
->hw_fragsize
;
1723 DBGPV("hwfrags = %d, swfrags = %d\n", hwfrags
, swfrags
);
1724 DBGPV("write hwbuf_max = %d, swbuf_size = %d\n",
1725 wport
->hwbuf_max
, wport
->swbuf_size
);
1728 aport
->swb_u_idx
= 0;
1729 aport
->swb_i_idx
= 0;
1730 aport
->byte_count
= 0;
1733 * Is this a Cobalt bug? We need to make this buffer extend
1734 * one page further than we actually use -- somehow memcpy
1735 * causes an exceptoin otherwise. I suspect there's a bug in
1736 * Cobalt (or somewhere) where it's generating a fault on a
1737 * speculative load or something. Obviously, I haven't taken
1738 * the time to track it down.
1741 aport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1744 if (rport
&& wport
) {
1745 ASSERT(aport
== rport
);
1746 ASSERT(wport
->swbuf
== NULL
);
1747 /* One extra page - see comment above. */
1748 wport
->swbuf
= vmalloc(aport
->swbuf_size
+ PAGE_SIZE
);
1749 if (!wport
->swbuf
) {
1750 vfree(aport
->swbuf
);
1751 aport
->swbuf
= NULL
;
1754 wport
->sample_size
= rport
->sample_size
;
1755 wport
->zero_word
= rport
->zero_word
;
1756 wport
->frame_size
= rport
->frame_size
;
1757 wport
->hw_fragshift
= rport
->hw_fragshift
;
1758 wport
->hw_fragsize
= rport
->hw_fragsize
;
1759 wport
->hw_fragcount
= rport
->hw_fragcount
;
1760 wport
->swbuf_size
= rport
->swbuf_size
;
1761 wport
->hwbuf_max
= rport
->hwbuf_max
;
1762 wport
->swb_u_idx
= rport
->swb_u_idx
;
1763 wport
->swb_i_idx
= rport
->swb_i_idx
;
1764 wport
->byte_count
= rport
->byte_count
;
1767 rport
->swb_u_avail
= 0;
1768 rport
->swb_i_avail
= rport
->swbuf_size
;
1769 rport
->swstate
= SW_RUN
;
1770 li_setup_dma(&rport
->chan
,
1775 rport
->hw_fragshift
,
1777 rport
->sample_size
);
1778 ad1843_setup_adc(&devc
->lith
,
1779 rport
->sw_framerate
,
1780 rport
->sw_samplefmt
,
1781 rport
->sw_channels
);
1782 li_enable_interrupts(&devc
->lith
, READ_INTR_MASK
);
1783 if (!(rport
->flags
& DISABLED
)) {
1785 rport
->hwstate
= HW_RUNNING
;
1786 li_activate_dma(&rport
->chan
);
1787 li_read_USTMSC(&rport
->chan
, &ustmsc
);
1788 rport
->MSC_offset
= ustmsc
.msc
;
1792 if (wport
->hwbuf_max
> wport
->swbuf_size
)
1793 wport
->hwbuf_max
= wport
->swbuf_size
;
1794 wport
->flags
&= ~ERFLOWN
;
1795 wport
->swb_u_avail
= wport
->swbuf_size
;
1796 wport
->swb_i_avail
= 0;
1797 wport
->swstate
= SW_RUN
;
1798 li_setup_dma(&wport
->chan
,
1803 wport
->hw_fragshift
,
1805 wport
->sample_size
);
1806 ad1843_setup_dac(&devc
->lith
,
1807 wport
->sw_framerate
,
1808 wport
->sw_samplefmt
,
1809 wport
->sw_channels
);
1810 li_enable_interrupts(&devc
->lith
, WRITE_INTR_MASK
);
1817 * pcm_shutdown_port - shut down one port (direction) for PCM I/O.
1818 * Only called from pcm_shutdown.
1821 static void pcm_shutdown_port(vwsnd_dev_t
*devc
,
1822 vwsnd_port_t
*aport
,
1825 unsigned long flags
;
1826 vwsnd_port_hwstate_t hwstate
;
1827 DECLARE_WAITQUEUE(wait
, current
);
1829 aport
->swstate
= SW_INITIAL
;
1830 add_wait_queue(&aport
->queue
, &wait
);
1832 set_current_state(TASK_UNINTERRUPTIBLE
);
1833 spin_lock_irqsave(&aport
->lock
, flags
);
1835 hwstate
= aport
->hwstate
;
1837 spin_unlock_irqrestore(&aport
->lock
, flags
);
1838 if (hwstate
== HW_STOPPED
)
1842 current
->state
= TASK_RUNNING
;
1843 remove_wait_queue(&aport
->queue
, &wait
);
1844 li_disable_interrupts(&devc
->lith
, mask
);
1845 if (aport
== &devc
->rport
)
1846 ad1843_shutdown_adc(&devc
->lith
);
1847 else /* aport == &devc->wport) */
1848 ad1843_shutdown_dac(&devc
->lith
);
1849 li_shutdown_dma(&aport
->chan
);
1850 vfree(aport
->swbuf
);
1851 aport
->swbuf
= NULL
;
1852 aport
->byte_count
= 0;
1856 * pcm_shutdown undoes what pcm_setup did.
1857 * Also sets the ports' swstate to newstate.
1860 static void pcm_shutdown(vwsnd_dev_t
*devc
,
1861 vwsnd_port_t
*rport
,
1862 vwsnd_port_t
*wport
)
1864 DBGEV("(devc=0x%p, rport=0x%p, wport=0x%p)\n", devc
, rport
, wport
);
1866 if (rport
&& rport
->swbuf
) {
1867 DBGPV("shutting down rport\n");
1868 pcm_shutdown_port(devc
, rport
, READ_INTR_MASK
);
1870 if (wport
&& wport
->swbuf
) {
1871 DBGPV("shutting down wport\n");
1872 pcm_shutdown_port(devc
, wport
, WRITE_INTR_MASK
);
1877 static void pcm_copy_in(vwsnd_port_t
*rport
, int swidx
, int hwidx
, int nb
)
1879 char *src
= rport
->hwbuf
+ hwidx
;
1880 char *dst
= rport
->swbuf
+ swidx
;
1881 int fmt
= rport
->sw_samplefmt
;
1883 DBGPV("swidx = %d, hwidx = %d\n", swidx
, hwidx
);
1884 ASSERT(rport
->hwbuf
!= NULL
);
1885 ASSERT(rport
->swbuf
!= NULL
);
1886 ASSERT(nb
> 0 && (nb
% 32) == 0);
1887 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1888 ASSERT(swidx
>= 0 && swidx
+ nb
<= rport
->swbuf_size
);
1889 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= rport
->hwbuf_size
);
1891 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1893 /* See Sample Format Notes above. */
1895 char *end
= src
+ nb
;
1897 *dst
++ = *src
++ ^ 0x80;
1899 memcpy(dst
, src
, nb
);
1902 static void pcm_copy_out(vwsnd_port_t
*wport
, int swidx
, int hwidx
, int nb
)
1904 char *src
= wport
->swbuf
+ swidx
;
1905 char *dst
= wport
->hwbuf
+ hwidx
;
1906 int fmt
= wport
->sw_samplefmt
;
1908 ASSERT(nb
> 0 && (nb
% 32) == 0);
1909 ASSERT(wport
->hwbuf
!= NULL
);
1910 ASSERT(wport
->swbuf
!= NULL
);
1911 ASSERT(swidx
% 32 == 0 && hwidx
% 32 == 0);
1912 ASSERT(swidx
>= 0 && swidx
+ nb
<= wport
->swbuf_size
);
1913 ASSERT(hwidx
>= 0 && hwidx
+ nb
<= wport
->hwbuf_size
);
1914 if (fmt
== AFMT_MU_LAW
|| fmt
== AFMT_A_LAW
|| fmt
== AFMT_S8
) {
1916 /* See Sample Format Notes above. */
1918 char *end
= src
+ nb
;
1920 *dst
++ = *src
++ ^ 0x80;
1922 memcpy(dst
, src
, nb
);
1926 * pcm_output() is called both from baselevel and from interrupt level.
1927 * This is where audio frames are copied into the hardware-accessible
1930 * Locking note: The part of this routine that figures out what to do
1931 * holds wport->lock. The longer part releases wport->lock, but sets
1932 * wport->flags & HW_BUSY. Afterward, it reacquires wport->lock, and
1933 * checks for more work to do.
1935 * If another thread calls pcm_output() while HW_BUSY is set, it
1936 * returns immediately, knowing that the thread that set HW_BUSY will
1937 * look for more work to do before returning.
1939 * This has the advantage that port->lock is held for several short
1940 * periods instead of one long period. Also, when pcm_output is
1941 * called from base level, it reenables interrupts.
1944 static void pcm_output(vwsnd_dev_t
*devc
, int erflown
, int nb
)
1946 vwsnd_port_t
*wport
= &devc
->wport
;
1947 const int hwmax
= wport
->hwbuf_max
;
1948 const int hwsize
= wport
->hwbuf_size
;
1949 const int swsize
= wport
->swbuf_size
;
1950 const int fragsize
= wport
->hw_fragsize
;
1951 unsigned long iflags
;
1953 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
1954 spin_lock_irqsave(&wport
->lock
, iflags
);
1956 wport
->flags
|= ERFLOWN
;
1957 (void) __swb_inc_u(wport
, nb
);
1958 if (wport
->flags
& HW_BUSY
) {
1959 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1960 DBGPV("returning: HW BUSY\n");
1963 if (wport
->flags
& DISABLED
) {
1964 spin_unlock_irqrestore(&wport
->lock
, iflags
);
1965 DBGPV("returning: DISABLED\n");
1968 wport
->flags
|= HW_BUSY
;
1970 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
1971 vwsnd_port_hwstate_t hwstate
= wport
->hwstate
;
1972 vwsnd_port_swstate_t swstate
= wport
->swstate
;
1976 hwptr
= li_read_hwptr(&wport
->chan
);
1977 swptr
= li_read_swptr(&wport
->chan
);
1978 hw_unavail
= (swptr
- hwptr
+ hwsize
) % hwsize
;
1979 hw_avail
= (hwmax
- hw_unavail
) & -fragsize
;
1980 sw_avail
= wport
->swb_i_avail
& -fragsize
;
1981 if (sw_avail
&& swstate
== SW_RUN
) {
1982 if (wport
->flags
& ERFLOWN
) {
1983 wport
->flags
&= ~ERFLOWN
;
1985 } else if (swstate
== SW_INITIAL
||
1986 swstate
== SW_OFF
||
1987 (swstate
== SW_DRAIN
&&
1989 (wport
->flags
& ERFLOWN
))) {
1990 DBGP("stopping. hwstate = %d\n", hwstate
);
1991 if (hwstate
!= HW_STOPPED
) {
1992 li_deactivate_dma(&wport
->chan
);
1993 wport
->hwstate
= HW_STOPPED
;
1995 wake_up(&wport
->queue
);
1998 if (!sw_avail
|| !hw_avail
)
2000 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2003 * We gave up the port lock, but we have the HW_BUSY flag.
2004 * Proceed without accessing any nonlocal state.
2005 * Do not exit the loop -- must check for more work.
2008 swidx
= wport
->swb_i_idx
;
2012 if (nb
> hwsize
- swptr
)
2013 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2014 if (nb
> swsize
- swidx
)
2015 nb
= swsize
- swidx
; /* don't overflow swbuf */
2017 if (nb
% fragsize
) {
2018 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2019 DBGP("hw_avail = %d\n", hw_avail
);
2020 DBGP("sw_avail = %d\n", sw_avail
);
2021 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2022 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2024 ASSERT(!(nb
% fragsize
));
2025 DBGPV("copying swb[%d..%d] to hwb[%d..%d]\n",
2026 swidx
, swidx
+ nb
, swptr
, swptr
+ nb
);
2027 pcm_copy_out(wport
, swidx
, swptr
, nb
);
2028 li_write_swptr(&wport
->chan
, (swptr
+ nb
) % hwsize
);
2029 spin_lock_irqsave(&wport
->lock
, iflags
);
2030 if (hwstate
== HW_STOPPED
) {
2031 DBGPV("starting\n");
2032 li_activate_dma(&wport
->chan
);
2033 wport
->hwstate
= HW_RUNNING
;
2034 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2035 ASSERT(wport
->byte_count
% wport
->frame_size
== 0);
2036 wport
->MSC_offset
= ustmsc
.msc
- wport
->byte_count
/ wport
->frame_size
;
2038 __swb_inc_i(wport
, nb
);
2039 wport
->byte_count
+= nb
;
2040 wport
->frag_count
+= nb
/ fragsize
;
2041 ASSERT(nb
% fragsize
== 0);
2042 wake_up(&wport
->queue
);
2044 wport
->flags
&= ~HW_BUSY
;
2045 spin_unlock_irqrestore(&wport
->lock
, iflags
);
2050 * pcm_input() is called both from baselevel and from interrupt level.
2051 * This is where audio frames are copied out of the hardware-accessible
2054 * Locking note: The part of this routine that figures out what to do
2055 * holds rport->lock. The longer part releases rport->lock, but sets
2056 * rport->flags & HW_BUSY. Afterward, it reacquires rport->lock, and
2057 * checks for more work to do.
2059 * If another thread calls pcm_input() while HW_BUSY is set, it
2060 * returns immediately, knowing that the thread that set HW_BUSY will
2061 * look for more work to do before returning.
2063 * This has the advantage that port->lock is held for several short
2064 * periods instead of one long period. Also, when pcm_input is
2065 * called from base level, it reenables interrupts.
2068 static void pcm_input(vwsnd_dev_t
*devc
, int erflown
, int nb
)
2070 vwsnd_port_t
*rport
= &devc
->rport
;
2071 const int hwmax
= rport
->hwbuf_max
;
2072 const int hwsize
= rport
->hwbuf_size
;
2073 const int swsize
= rport
->swbuf_size
;
2074 const int fragsize
= rport
->hw_fragsize
;
2075 unsigned long iflags
;
2077 DBGEV("(devc=0x%p, erflown=%d, nb=%d)\n", devc
, erflown
, nb
);
2079 spin_lock_irqsave(&rport
->lock
, iflags
);
2081 rport
->flags
|= ERFLOWN
;
2082 (void) __swb_inc_u(rport
, nb
);
2083 if (rport
->flags
& HW_BUSY
|| !rport
->swbuf
) {
2084 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2085 DBGPV("returning: HW BUSY or !swbuf\n");
2088 if (rport
->flags
& DISABLED
) {
2089 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2090 DBGPV("returning: DISABLED\n");
2093 rport
->flags
|= HW_BUSY
;
2095 int swptr
, hwptr
, hw_avail
, sw_avail
, swidx
;
2096 vwsnd_port_hwstate_t hwstate
= rport
->hwstate
;
2097 vwsnd_port_swstate_t swstate
= rport
->swstate
;
2099 hwptr
= li_read_hwptr(&rport
->chan
);
2100 swptr
= li_read_swptr(&rport
->chan
);
2101 hw_avail
= (hwptr
- swptr
+ hwsize
) % hwsize
& -fragsize
;
2102 if (hw_avail
> hwmax
)
2104 sw_avail
= rport
->swb_i_avail
& -fragsize
;
2105 if (swstate
!= SW_RUN
) {
2106 DBGP("stopping. hwstate = %d\n", hwstate
);
2107 if (hwstate
!= HW_STOPPED
) {
2108 li_deactivate_dma(&rport
->chan
);
2109 rport
->hwstate
= HW_STOPPED
;
2111 wake_up(&rport
->queue
);
2114 if (!sw_avail
|| !hw_avail
)
2116 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2119 * We gave up the port lock, but we have the HW_BUSY flag.
2120 * Proceed without accessing any nonlocal state.
2121 * Do not exit the loop -- must check for more work.
2124 swidx
= rport
->swb_i_idx
;
2128 if (nb
> hwsize
- swptr
)
2129 nb
= hwsize
- swptr
; /* don't overflow hwbuf */
2130 if (nb
> swsize
- swidx
)
2131 nb
= swsize
- swidx
; /* don't overflow swbuf */
2133 if (nb
% fragsize
) {
2134 DBGP("nb = %d, fragsize = %d\n", nb
, fragsize
);
2135 DBGP("hw_avail = %d\n", hw_avail
);
2136 DBGP("sw_avail = %d\n", sw_avail
);
2137 DBGP("hwsize = %d, swptr = %d\n", hwsize
, swptr
);
2138 DBGP("swsize = %d, swidx = %d\n", swsize
, swidx
);
2140 ASSERT(!(nb
% fragsize
));
2141 DBGPV("copying hwb[%d..%d] to swb[%d..%d]\n",
2142 swptr
, swptr
+ nb
, swidx
, swidx
+ nb
);
2143 pcm_copy_in(rport
, swidx
, swptr
, nb
);
2144 li_write_swptr(&rport
->chan
, (swptr
+ nb
) % hwsize
);
2145 spin_lock_irqsave(&rport
->lock
, iflags
);
2146 __swb_inc_i(rport
, nb
);
2147 rport
->byte_count
+= nb
;
2148 rport
->frag_count
+= nb
/ fragsize
;
2149 ASSERT(nb
% fragsize
== 0);
2150 wake_up(&rport
->queue
);
2152 rport
->flags
&= ~HW_BUSY
;
2153 spin_unlock_irqrestore(&rport
->lock
, iflags
);
2158 * pcm_flush_frag() writes zero samples to fill the current fragment,
2159 * then flushes it to the hardware.
2161 * It is only meaningful to flush output, not input.
2164 static void pcm_flush_frag(vwsnd_dev_t
*devc
)
2166 vwsnd_port_t
*wport
= &devc
->wport
;
2168 DBGPV("swstate = %d\n", wport
->swstate
);
2169 if (wport
->swstate
== SW_RUN
) {
2170 int idx
= wport
->swb_u_idx
;
2171 int end
= (idx
+ wport
->hw_fragsize
- 1)
2172 >> wport
->hw_fragshift
2173 << wport
->hw_fragshift
;
2175 DBGPV("clearing %d bytes\n", nb
);
2177 memset(wport
->swbuf
+ idx
,
2178 (char) wport
->zero_word
,
2180 wport
->swstate
= SW_DRAIN
;
2181 pcm_output(devc
, 0, nb
);
2187 * Wait for output to drain. This sleeps uninterruptibly because
2188 * there is nothing intelligent we can do if interrupted. This
2189 * means the process will be delayed in responding to the signal.
2192 static void pcm_write_sync(vwsnd_dev_t
*devc
)
2194 vwsnd_port_t
*wport
= &devc
->wport
;
2195 DECLARE_WAITQUEUE(wait
, current
);
2196 unsigned long flags
;
2197 vwsnd_port_hwstate_t hwstate
;
2199 DBGEV("(devc=0x%p)\n", devc
);
2200 add_wait_queue(&wport
->queue
, &wait
);
2202 set_current_state(TASK_UNINTERRUPTIBLE
);
2203 spin_lock_irqsave(&wport
->lock
, flags
);
2205 hwstate
= wport
->hwstate
;
2207 spin_unlock_irqrestore(&wport
->lock
, flags
);
2208 if (hwstate
== HW_STOPPED
)
2212 current
->state
= TASK_RUNNING
;
2213 remove_wait_queue(&wport
->queue
, &wait
);
2214 DBGPV("swstate = %d, hwstate = %d\n", wport
->swstate
, wport
->hwstate
);
2218 /*****************************************************************************/
2222 * seek on an audio device always fails.
2225 static void vwsnd_audio_read_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2227 int overflown
= status
& LI_INTR_COMM1_OVERFLOW
;
2229 if (status
& READ_INTR_MASK
)
2230 pcm_input(devc
, overflown
, 0);
2233 static void vwsnd_audio_write_intr(vwsnd_dev_t
*devc
, unsigned int status
)
2235 int underflown
= status
& LI_INTR_COMM2_UNDERFLOW
;
2237 if (status
& WRITE_INTR_MASK
)
2238 pcm_output(devc
, underflown
, 0);
2241 static void vwsnd_audio_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
2243 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) dev_id
;
2244 unsigned int status
;
2246 DBGEV("(irq=%d, dev_id=0x%p, regs=0x%p)\n", irq
, dev_id
, regs
);
2248 status
= li_get_clear_intr_status(&devc
->lith
);
2249 vwsnd_audio_read_intr(devc
, status
);
2250 vwsnd_audio_write_intr(devc
, status
);
2253 static loff_t
vwsnd_audio_llseek(struct file
*file
, loff_t offset
, int whence
)
2255 DBGEV("(file=0x%p, offset=%Ld, whence=%d)\n", file
, offset
, whence
);
2259 static ssize_t
vwsnd_audio_do_read(struct file
*file
,
2264 vwsnd_dev_t
*devc
= file
->private_data
;
2265 vwsnd_port_t
*rport
= ((file
->f_mode
& FMODE_READ
) ?
2266 &devc
->rport
: NULL
);
2269 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2270 file
, buffer
, count
, ppos
);
2275 if (rport
->swbuf
== NULL
) {
2276 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2277 &devc
->wport
: NULL
;
2278 ret
= pcm_setup(devc
, rport
, wport
);
2283 if (!access_ok(VERIFY_READ
, buffer
, count
))
2287 DECLARE_WAITQUEUE(wait
, current
);
2288 add_wait_queue(&rport
->queue
, &wait
);
2289 while ((nb
= swb_inc_u(rport
, 0)) == 0) {
2290 DBGPV("blocking\n");
2291 set_current_state(TASK_INTERRUPTIBLE
);
2292 if (rport
->flags
& DISABLED
||
2293 file
->f_flags
& O_NONBLOCK
) {
2294 current
->state
= TASK_RUNNING
;
2295 remove_wait_queue(&rport
->queue
, &wait
);
2296 return ret
? ret
: -EAGAIN
;
2299 if (signal_pending(current
)) {
2300 current
->state
= TASK_RUNNING
;
2301 remove_wait_queue(&rport
->queue
, &wait
);
2302 return ret
? ret
: -ERESTARTSYS
;
2305 current
->state
= TASK_RUNNING
;
2306 remove_wait_queue(&rport
->queue
, &wait
);
2307 pcm_input(devc
, 0, 0);
2308 /* nb bytes are available in userbuf. */
2311 DBGPV("nb = %d\n", nb
);
2312 copy_to_user(buffer
, rport
->swbuf
+ rport
->swb_u_idx
, nb
);
2313 (void) swb_inc_u(rport
, nb
);
2318 DBGPV("returning %d\n", ret
);
2322 static ssize_t
vwsnd_audio_read(struct file
*file
,
2327 vwsnd_dev_t
*devc
= file
->private_data
;
2330 down(&devc
->io_sema
);
2331 ret
= vwsnd_audio_do_read(file
, buffer
, count
, ppos
);
2336 static ssize_t
vwsnd_audio_do_write(struct file
*file
,
2341 vwsnd_dev_t
*devc
= file
->private_data
;
2342 vwsnd_port_t
*wport
= ((file
->f_mode
& FMODE_WRITE
) ?
2343 &devc
->wport
: NULL
);
2346 DBGEV("(file=0x%p, buffer=0x%p, count=%d, ppos=0x%p)\n",
2347 file
, buffer
, count
, ppos
);
2352 if (wport
->swbuf
== NULL
) {
2353 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2354 &devc
->rport
: NULL
;
2355 ret
= pcm_setup(devc
, rport
, wport
);
2359 if (!access_ok(VERIFY_WRITE
, buffer
, count
))
2363 DECLARE_WAITQUEUE(wait
, current
);
2364 add_wait_queue(&wport
->queue
, &wait
);
2365 while ((nb
= swb_inc_u(wport
, 0)) == 0) {
2366 set_current_state(TASK_INTERRUPTIBLE
);
2367 if (wport
->flags
& DISABLED
||
2368 file
->f_flags
& O_NONBLOCK
) {
2369 current
->state
= TASK_RUNNING
;
2370 remove_wait_queue(&wport
->queue
, &wait
);
2371 return ret
? ret
: -EAGAIN
;
2374 if (signal_pending(current
)) {
2375 current
->state
= TASK_RUNNING
;
2376 remove_wait_queue(&wport
->queue
, &wait
);
2377 return ret
? ret
: -ERESTARTSYS
;
2380 current
->state
= TASK_RUNNING
;
2381 remove_wait_queue(&wport
->queue
, &wait
);
2382 /* nb bytes are available in userbuf. */
2385 DBGPV("nb = %d\n", nb
);
2386 copy_from_user(wport
->swbuf
+ wport
->swb_u_idx
, buffer
, nb
);
2387 pcm_output(devc
, 0, nb
);
2392 DBGPV("returning %d\n", ret
);
2396 static ssize_t
vwsnd_audio_write(struct file
*file
,
2401 vwsnd_dev_t
*devc
= file
->private_data
;
2404 down(&devc
->io_sema
);
2405 ret
= vwsnd_audio_do_write(file
, buffer
, count
, ppos
);
2410 /* No kernel lock - fine */
2411 static unsigned int vwsnd_audio_poll(struct file
*file
,
2412 struct poll_table_struct
*wait
)
2414 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2415 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2416 &devc
->rport
: NULL
;
2417 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2418 &devc
->wport
: NULL
;
2419 unsigned int mask
= 0;
2421 DBGEV("(file=0x%p, wait=0x%p)\n", file
, wait
);
2423 ASSERT(rport
|| wport
);
2425 poll_wait(file
, &rport
->queue
, wait
);
2426 if (swb_inc_u(rport
, 0))
2427 mask
|= (POLLIN
| POLLRDNORM
);
2430 poll_wait(file
, &wport
->queue
, wait
);
2431 if (wport
->swbuf
== NULL
|| swb_inc_u(wport
, 0))
2432 mask
|= (POLLOUT
| POLLWRNORM
);
2435 DBGPV("returning 0x%x\n", mask
);
2439 static int vwsnd_audio_do_ioctl(struct inode
*inode
,
2444 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2445 vwsnd_port_t
*rport
= (file
->f_mode
& FMODE_READ
) ?
2446 &devc
->rport
: NULL
;
2447 vwsnd_port_t
*wport
= (file
->f_mode
& FMODE_WRITE
) ?
2448 &devc
->wport
: NULL
;
2449 vwsnd_port_t
*aport
= rport
? rport
: wport
;
2450 struct audio_buf_info buf_info
;
2451 struct count_info info
;
2452 unsigned long flags
;
2456 DBGEV("(inode=0x%p, file=0x%p, cmd=0x%x, arg=0x%lx)\n",
2457 inode
, file
, cmd
, arg
);
2459 case OSS_GETVERSION
: /* _SIOR ('M', 118, int) */
2460 DBGX("OSS_GETVERSION\n");
2461 ival
= SOUND_VERSION
;
2462 return put_user(ival
, (int *) arg
);
2464 case SNDCTL_DSP_GETCAPS
: /* _SIOR ('P',15, int) */
2465 DBGX("SNDCTL_DSP_GETCAPS\n");
2466 ival
= DSP_CAP_DUPLEX
| DSP_CAP_REALTIME
| DSP_CAP_TRIGGER
;
2467 return put_user(ival
, (int *) arg
);
2469 case SNDCTL_DSP_GETFMTS
: /* _SIOR ('P',11, int) */
2470 DBGX("SNDCTL_DSP_GETFMTS\n");
2471 ival
= (AFMT_S16_LE
| AFMT_MU_LAW
| AFMT_A_LAW
|
2473 return put_user(ival
, (int *) arg
);
2476 case SOUND_PCM_READ_RATE
: /* _SIOR ('P', 2, int) */
2477 DBGX("SOUND_PCM_READ_RATE\n");
2478 ival
= aport
->sw_framerate
;
2479 return put_user(ival
, (int *) arg
);
2481 case SOUND_PCM_READ_CHANNELS
: /* _SIOR ('P', 6, int) */
2482 DBGX("SOUND_PCM_READ_CHANNELS\n");
2483 ival
= aport
->sw_channels
;
2484 return put_user(ival
, (int *) arg
);
2486 case SNDCTL_DSP_SPEED
: /* _SIOWR('P', 2, int) */
2487 if (get_user(ival
, (int *) arg
))
2489 DBGX("SNDCTL_DSP_SPEED %d\n", ival
);
2491 if (aport
->swstate
!= SW_INITIAL
) {
2492 DBGX("SNDCTL_DSP_SPEED failed: swstate = %d\n",
2496 if (ival
< MIN_SPEED
)
2498 if (ival
> MAX_SPEED
)
2501 rport
->sw_framerate
= ival
;
2503 wport
->sw_framerate
= ival
;
2505 ival
= aport
->sw_framerate
;
2506 return put_user(ival
, (int *) arg
);
2508 case SNDCTL_DSP_STEREO
: /* _SIOWR('P', 3, int) */
2509 if (get_user(ival
, (int *) arg
))
2511 DBGX("SNDCTL_DSP_STEREO %d\n", ival
);
2512 if (ival
!= 0 && ival
!= 1)
2514 if (aport
->swstate
!= SW_INITIAL
)
2517 rport
->sw_channels
= ival
+ 1;
2519 wport
->sw_channels
= ival
+ 1;
2520 return put_user(ival
, (int *) arg
);
2522 case SNDCTL_DSP_CHANNELS
: /* _SIOWR('P', 6, int) */
2523 if (get_user(ival
, (int *) arg
))
2525 DBGX("SNDCTL_DSP_CHANNELS %d\n", ival
);
2526 if (ival
!= 1 && ival
!= 2)
2528 if (aport
->swstate
!= SW_INITIAL
)
2531 rport
->sw_channels
= ival
;
2533 wport
->sw_channels
= ival
;
2534 return put_user(ival
, (int *) arg
);
2536 case SNDCTL_DSP_GETBLKSIZE
: /* _SIOWR('P', 4, int) */
2537 ival
= pcm_setup(devc
, rport
, wport
);
2539 DBGX("SNDCTL_DSP_GETBLKSIZE failed, errno %d\n", ival
);
2542 ival
= 1 << aport
->sw_fragshift
;
2543 DBGX("SNDCTL_DSP_GETBLKSIZE returning %d\n", ival
);
2544 return put_user(ival
, (int *) arg
);
2546 case SNDCTL_DSP_SETFRAGMENT
: /* _SIOWR('P',10, int) */
2547 if (get_user(ival
, (int *) arg
))
2549 DBGX("SNDCTL_DSP_SETFRAGMENT %d:%d\n",
2550 ival
>> 16, ival
& 0xFFFF);
2551 if (aport
->swstate
!= SW_INITIAL
)
2554 int sw_fragshift
= ival
& 0xFFFF;
2555 int sw_subdivshift
= aport
->sw_subdivshift
;
2556 int hw_fragshift
= sw_fragshift
- sw_subdivshift
;
2557 int sw_fragcount
= (ival
>> 16) & 0xFFFF;
2559 if (hw_fragshift
< MIN_FRAGSHIFT
)
2560 hw_fragshift
= MIN_FRAGSHIFT
;
2561 if (hw_fragshift
> MAX_FRAGSHIFT
)
2562 hw_fragshift
= MAX_FRAGSHIFT
;
2563 sw_fragshift
= hw_fragshift
+ aport
->sw_subdivshift
;
2564 hw_fragsize
= 1 << hw_fragshift
;
2565 if (sw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
))
2566 sw_fragcount
= MIN_FRAGCOUNT(hw_fragsize
);
2567 if (sw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2568 sw_fragcount
= MAX_FRAGCOUNT(hw_fragsize
);
2569 DBGPV("sw_fragshift = %d\n", sw_fragshift
);
2570 DBGPV("rport = 0x%p, wport = 0x%p\n", rport
, wport
);
2572 rport
->sw_fragshift
= sw_fragshift
;
2573 rport
->sw_fragcount
= sw_fragcount
;
2576 wport
->sw_fragshift
= sw_fragshift
;
2577 wport
->sw_fragcount
= sw_fragcount
;
2579 ival
= sw_fragcount
<< 16 | sw_fragshift
;
2581 DBGX("SNDCTL_DSP_SETFRAGMENT returns %d:%d\n",
2582 ival
>> 16, ival
& 0xFFFF);
2583 return put_user(ival
, (int *) arg
);
2585 case SNDCTL_DSP_SUBDIVIDE
: /* _SIOWR('P', 9, int) */
2586 if (get_user(ival
, (int *) arg
))
2588 DBGX("SNDCTL_DSP_SUBDIVIDE %d\n", ival
);
2589 if (aport
->swstate
!= SW_INITIAL
)
2593 int hw_fragshift
, hw_fragsize
, hw_fragcount
;
2595 case 1: subdivshift
= 0; break;
2596 case 2: subdivshift
= 1; break;
2597 case 4: subdivshift
= 2; break;
2598 default: return -EINVAL
;
2600 hw_fragshift
= aport
->sw_fragshift
- subdivshift
;
2601 if (hw_fragshift
< MIN_FRAGSHIFT
||
2602 hw_fragshift
> MAX_FRAGSHIFT
)
2604 hw_fragsize
= 1 << hw_fragshift
;
2605 hw_fragcount
= aport
->sw_fragcount
>> subdivshift
;
2606 if (hw_fragcount
< MIN_FRAGCOUNT(hw_fragsize
) ||
2607 hw_fragcount
> MAX_FRAGCOUNT(hw_fragsize
))
2610 rport
->sw_subdivshift
= subdivshift
;
2612 wport
->sw_subdivshift
= subdivshift
;
2616 case SNDCTL_DSP_SETFMT
: /* _SIOWR('P',5, int) */
2617 if (get_user(ival
, (int *) arg
))
2619 DBGX("SNDCTL_DSP_SETFMT %d\n", ival
);
2620 if (ival
!= AFMT_QUERY
) {
2621 if (aport
->swstate
!= SW_INITIAL
) {
2622 DBGP("SETFMT failed, swstate = %d\n",
2633 rport
->sw_samplefmt
= ival
;
2635 wport
->sw_samplefmt
= ival
;
2641 ival
= aport
->sw_samplefmt
;
2642 return put_user(ival
, (int *) arg
);
2644 case SNDCTL_DSP_GETOSPACE
: /* _SIOR ('P',12, audio_buf_info) */
2645 DBGXV("SNDCTL_DSP_GETOSPACE\n");
2648 ival
= pcm_setup(devc
, rport
, wport
);
2651 ival
= swb_inc_u(wport
, 0);
2652 buf_info
.fragments
= ival
>> wport
->sw_fragshift
;
2653 buf_info
.fragstotal
= wport
->sw_fragcount
;
2654 buf_info
.fragsize
= 1 << wport
->sw_fragshift
;
2655 buf_info
.bytes
= ival
;
2656 DBGXV("SNDCTL_DSP_GETOSPACE returns { %d %d %d %d }\n",
2657 buf_info
.fragments
, buf_info
.fragstotal
,
2658 buf_info
.fragsize
, buf_info
.bytes
);
2659 return copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
);
2661 case SNDCTL_DSP_GETISPACE
: /* _SIOR ('P',13, audio_buf_info) */
2662 DBGX("SNDCTL_DSP_GETISPACE\n");
2665 ival
= pcm_setup(devc
, rport
, wport
);
2668 ival
= swb_inc_u(rport
, 0);
2669 buf_info
.fragments
= ival
>> rport
->sw_fragshift
;
2670 buf_info
.fragstotal
= rport
->sw_fragcount
;
2671 buf_info
.fragsize
= 1 << rport
->sw_fragshift
;
2672 buf_info
.bytes
= ival
;
2673 DBGX("SNDCTL_DSP_GETISPACE returns { %d %d %d %d }\n",
2674 buf_info
.fragments
, buf_info
.fragstotal
,
2675 buf_info
.fragsize
, buf_info
.bytes
);
2676 return copy_to_user((void *) arg
, &buf_info
, sizeof buf_info
);
2678 case SNDCTL_DSP_NONBLOCK
: /* _SIO ('P',14) */
2679 DBGX("SNDCTL_DSP_NONBLOCK\n");
2680 file
->f_flags
|= O_NONBLOCK
;
2683 case SNDCTL_DSP_RESET
: /* _SIO ('P', 0) */
2684 DBGX("SNDCTL_DSP_RESET\n");
2686 * Nothing special needs to be done for input. Input
2687 * samples sit in swbuf, but it will be reinitialized
2688 * to empty when pcm_setup() is called.
2690 if (wport
&& wport
->swbuf
) {
2691 wport
->swstate
= SW_INITIAL
;
2692 pcm_output(devc
, 0, 0);
2693 pcm_write_sync(devc
);
2695 pcm_shutdown(devc
, rport
, wport
);
2698 case SNDCTL_DSP_SYNC
: /* _SIO ('P', 1) */
2699 DBGX("SNDCTL_DSP_SYNC\n");
2701 pcm_flush_frag(devc
);
2702 pcm_write_sync(devc
);
2704 pcm_shutdown(devc
, rport
, wport
);
2707 case SNDCTL_DSP_POST
: /* _SIO ('P', 8) */
2708 DBGX("SNDCTL_DSP_POST\n");
2711 pcm_flush_frag(devc
);
2714 case SNDCTL_DSP_GETIPTR
: /* _SIOR ('P', 17, count_info) */
2715 DBGX("SNDCTL_DSP_GETIPTR\n");
2718 spin_lock_irqsave(&rport
->lock
, flags
);
2721 if (rport
->hwstate
== HW_RUNNING
) {
2722 ASSERT(rport
->swstate
== SW_RUN
);
2723 li_read_USTMSC(&rport
->chan
, &ustmsc
);
2724 info
.bytes
= ustmsc
.msc
- rport
->MSC_offset
;
2725 info
.bytes
*= rport
->frame_size
;
2727 info
.bytes
= rport
->byte_count
;
2729 info
.blocks
= rport
->frag_count
;
2730 info
.ptr
= 0; /* not implemented */
2731 rport
->frag_count
= 0;
2733 spin_unlock_irqrestore(&rport
->lock
, flags
);
2734 return copy_to_user((void *) arg
, &info
, sizeof info
);
2736 case SNDCTL_DSP_GETOPTR
: /* _SIOR ('P',18, count_info) */
2737 DBGX("SNDCTL_DSP_GETOPTR\n");
2740 spin_lock_irqsave(&wport
->lock
, flags
);
2743 if (wport
->hwstate
== HW_RUNNING
) {
2744 ASSERT(wport
->swstate
== SW_RUN
);
2745 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2746 info
.bytes
= ustmsc
.msc
- wport
->MSC_offset
;
2747 info
.bytes
*= wport
->frame_size
;
2749 info
.bytes
= wport
->byte_count
;
2751 info
.blocks
= wport
->frag_count
;
2752 info
.ptr
= 0; /* not implemented */
2753 wport
->frag_count
= 0;
2755 spin_unlock_irqrestore(&wport
->lock
, flags
);
2756 return copy_to_user((void *) arg
, &info
, sizeof info
);
2758 case SNDCTL_DSP_GETODELAY
: /* _SIOR ('P', 23, int) */
2759 DBGX("SNDCTL_DSP_GETODELAY\n");
2762 spin_lock_irqsave(&wport
->lock
, flags
);
2764 int fsize
= wport
->frame_size
;
2765 ival
= wport
->swb_i_avail
/ fsize
;
2766 if (wport
->hwstate
== HW_RUNNING
) {
2767 int swptr
, hwptr
, hwframes
, hwbytes
, hwsize
;
2771 hwsize
= wport
->hwbuf_size
;
2772 swptr
= li_read_swptr(&wport
->chan
);
2773 li_read_USTMSC(&wport
->chan
, &ustmsc
);
2774 hwframes
= ustmsc
.msc
- wport
->MSC_offset
;
2775 totalhwbytes
= hwframes
* fsize
;
2776 hwptr
= totalhwbytes
% hwsize
;
2777 hwbytes
= (swptr
- hwptr
+ hwsize
) % hwsize
;
2778 ival
+= hwbytes
/ fsize
;
2781 spin_unlock_irqrestore(&wport
->lock
, flags
);
2782 return put_user(ival
, (int *) arg
);
2784 case SNDCTL_DSP_PROFILE
: /* _SIOW ('P', 23, int) */
2785 DBGX("SNDCTL_DSP_PROFILE\n");
2788 * Thomas Sailer explains SNDCTL_DSP_PROFILE
2789 * (private email, March 24, 1999):
2791 * This gives the sound driver a hint on what it
2792 * should do with partial fragments
2793 * (i.e. fragments partially filled with write).
2794 * This can direct the driver to zero them or
2795 * leave them alone. But don't ask me what this
2796 * is good for, my driver just zeroes the last
2797 * fragment before the receiver stops, no idea
2798 * what good for any other behaviour could
2799 * be. Implementing it as NOP seems safe.
2804 case SNDCTL_DSP_GETTRIGGER
: /* _SIOR ('P',16, int) */
2805 DBGX("SNDCTL_DSP_GETTRIGGER\n");
2808 spin_lock_irqsave(&rport
->lock
, flags
);
2810 if (!(rport
->flags
& DISABLED
))
2811 ival
|= PCM_ENABLE_INPUT
;
2813 spin_unlock_irqrestore(&rport
->lock
, flags
);
2816 spin_lock_irqsave(&wport
->lock
, flags
);
2818 if (!(wport
->flags
& DISABLED
))
2819 ival
|= PCM_ENABLE_OUTPUT
;
2821 spin_unlock_irqrestore(&wport
->lock
, flags
);
2823 return put_user(ival
, (int *) arg
);
2825 case SNDCTL_DSP_SETTRIGGER
: /* _SIOW ('P',16, int) */
2826 if (get_user(ival
, (int *) arg
))
2828 DBGX("SNDCTL_DSP_SETTRIGGER %d\n", ival
);
2831 * If user is disabling I/O and port is not in initial
2832 * state, fail with EINVAL.
2835 if (((rport
&& !(ival
& PCM_ENABLE_INPUT
)) ||
2836 (wport
&& !(ival
& PCM_ENABLE_OUTPUT
))) &&
2837 aport
->swstate
!= SW_INITIAL
)
2841 vwsnd_port_hwstate_t hwstate
;
2842 spin_lock_irqsave(&rport
->lock
, flags
);
2844 hwstate
= rport
->hwstate
;
2845 if (ival
& PCM_ENABLE_INPUT
)
2846 rport
->flags
&= ~DISABLED
;
2848 rport
->flags
|= DISABLED
;
2850 spin_unlock_irqrestore(&rport
->lock
, flags
);
2851 if (hwstate
!= HW_RUNNING
&& ival
& PCM_ENABLE_INPUT
) {
2853 if (rport
->swstate
== SW_INITIAL
)
2854 pcm_setup(devc
, rport
, wport
);
2856 li_activate_dma(&rport
->chan
);
2860 vwsnd_port_flags_t pflags
;
2861 spin_lock_irqsave(&wport
->lock
, flags
);
2863 pflags
= wport
->flags
;
2864 if (ival
& PCM_ENABLE_OUTPUT
)
2865 wport
->flags
&= ~DISABLED
;
2867 wport
->flags
|= DISABLED
;
2869 spin_unlock_irqrestore(&wport
->lock
, flags
);
2870 if (pflags
& DISABLED
&& ival
& PCM_ENABLE_OUTPUT
) {
2871 if (wport
->swstate
== SW_RUN
)
2872 pcm_output(devc
, 0, 0);
2878 DBGP("unknown ioctl 0x%x\n", cmd
);
2881 DBGP("unimplemented ioctl 0x%x\n", cmd
);
2885 static int vwsnd_audio_ioctl(struct inode
*inode
,
2890 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
2893 down(&devc
->io_sema
);
2894 ret
= vwsnd_audio_do_ioctl(inode
, file
, cmd
, arg
);
2901 static int vwsnd_audio_mmap(struct file
*file
, struct vm_area_struct
*vma
)
2903 DBGE("(file=0x%p, vma=0x%p)\n", file
, vma
);
2908 * Open the audio device for read and/or write.
2910 * Returns 0 on success, -errno on failure.
2913 static int vwsnd_audio_open(struct inode
*inode
, struct file
*file
)
2916 dev_t minor
= MINOR(inode
->i_rdev
);
2919 DBGE("(inode=0x%p, file=0x%p)\n", inode
, file
);
2922 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
2923 if ((devc
->audio_minor
& ~0x0F) == (minor
& ~0x0F))
2931 down(&devc
->open_sema
);
2932 while (devc
->open_mode
& file
->f_mode
) {
2933 up(&devc
->open_sema
);
2934 if (file
->f_flags
& O_NONBLOCK
) {
2938 interruptible_sleep_on(&devc
->open_wait
);
2939 if (signal_pending(current
)) {
2941 return -ERESTARTSYS
;
2943 down(&devc
->open_sema
);
2945 devc
->open_mode
|= file
->f_mode
& (FMODE_READ
| FMODE_WRITE
);
2946 up(&devc
->open_sema
);
2948 /* get default sample format from minor number. */
2951 if ((minor
& 0xF) == SND_DEV_DSP
)
2952 sw_samplefmt
= AFMT_U8
;
2953 else if ((minor
& 0xF) == SND_DEV_AUDIO
)
2954 sw_samplefmt
= AFMT_MU_LAW
;
2955 else if ((minor
& 0xF) == SND_DEV_DSP16
)
2956 sw_samplefmt
= AFMT_S16_LE
;
2960 /* Initialize vwsnd_ports. */
2962 down(&devc
->io_sema
);
2964 if (file
->f_mode
& FMODE_READ
) {
2965 devc
->rport
.swstate
= SW_INITIAL
;
2966 devc
->rport
.flags
= 0;
2967 devc
->rport
.sw_channels
= 1;
2968 devc
->rport
.sw_samplefmt
= sw_samplefmt
;
2969 devc
->rport
.sw_framerate
= 8000;
2970 devc
->rport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2971 devc
->rport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2972 devc
->rport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2973 devc
->rport
.byte_count
= 0;
2974 devc
->rport
.frag_count
= 0;
2976 if (file
->f_mode
& FMODE_WRITE
) {
2977 devc
->wport
.swstate
= SW_INITIAL
;
2978 devc
->wport
.flags
= 0;
2979 devc
->wport
.sw_channels
= 1;
2980 devc
->wport
.sw_samplefmt
= sw_samplefmt
;
2981 devc
->wport
.sw_framerate
= 8000;
2982 devc
->wport
.sw_fragshift
= DEFAULT_FRAGSHIFT
;
2983 devc
->wport
.sw_fragcount
= DEFAULT_FRAGCOUNT
;
2984 devc
->wport
.sw_subdivshift
= DEFAULT_SUBDIVSHIFT
;
2985 devc
->wport
.byte_count
= 0;
2986 devc
->wport
.frag_count
= 0;
2991 file
->private_data
= devc
;
2997 * Release (close) the audio device.
3000 static int vwsnd_audio_release(struct inode
*inode
, struct file
*file
)
3002 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
3003 vwsnd_port_t
*wport
= NULL
, *rport
= NULL
;
3007 down(&devc
->io_sema
);
3009 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3011 if (file
->f_mode
& FMODE_READ
)
3012 rport
= &devc
->rport
;
3013 if (file
->f_mode
& FMODE_WRITE
) {
3014 wport
= &devc
->wport
;
3015 pcm_flush_frag(devc
);
3016 pcm_write_sync(devc
);
3018 pcm_shutdown(devc
, rport
, wport
);
3020 rport
->swstate
= SW_OFF
;
3022 wport
->swstate
= SW_OFF
;
3026 down(&devc
->open_sema
);
3028 devc
->open_mode
&= ~file
->f_mode
;
3030 up(&devc
->open_sema
);
3031 wake_up(&devc
->open_wait
);
3038 static struct file_operations vwsnd_audio_fops
= {
3040 llseek
: vwsnd_audio_llseek
,
3041 read
: vwsnd_audio_read
,
3042 write
: vwsnd_audio_write
,
3043 poll
: vwsnd_audio_poll
,
3044 ioctl
: vwsnd_audio_ioctl
,
3045 mmap
: vwsnd_audio_mmap
,
3046 open
: vwsnd_audio_open
,
3047 release
: vwsnd_audio_release
,
3050 /*****************************************************************************/
3053 /* open the mixer device. */
3055 static int vwsnd_mixer_open(struct inode
*inode
, struct file
*file
)
3059 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3062 for (devc
= vwsnd_dev_list
; devc
; devc
= devc
->next_dev
)
3063 if (devc
->mixer_minor
== MINOR(inode
->i_rdev
))
3070 file
->private_data
= devc
;
3074 /* release (close) the mixer device. */
3076 static int vwsnd_mixer_release(struct inode
*inode
, struct file
*file
)
3078 DBGEV("(inode=0x%p, file=0x%p)\n", inode
, file
);
3083 /* seek is illegal on mixer. */
3085 static loff_t
vwsnd_mixer_llseek(struct file
*file
, loff_t offset
, int whence
)
3090 /* mixer_read_ioctl handles all read ioctls on the mixer device. */
3092 static int mixer_read_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, caddr_t arg
)
3096 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3099 case SOUND_MIXER_CAPS
:
3100 val
= SOUND_CAP_EXCL_INPUT
;
3103 case SOUND_MIXER_DEVMASK
:
3104 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3105 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3108 case SOUND_MIXER_STEREODEVS
:
3109 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3110 SOUND_MASK_MIC
| SOUND_MASK_CD
| SOUND_MASK_RECLEV
);
3113 case SOUND_MIXER_OUTMASK
:
3114 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3115 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3118 case SOUND_MIXER_RECMASK
:
3119 val
= (SOUND_MASK_PCM
| SOUND_MASK_LINE
|
3120 SOUND_MASK_MIC
| SOUND_MASK_CD
);
3123 case SOUND_MIXER_PCM
:
3124 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_PCM
);
3127 case SOUND_MIXER_LINE
:
3128 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_LINE
);
3131 case SOUND_MIXER_MIC
:
3132 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_MIC
);
3135 case SOUND_MIXER_CD
:
3136 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_CD
);
3139 case SOUND_MIXER_RECLEV
:
3140 val
= ad1843_get_gain(&devc
->lith
, &ad1843_gain_RECLEV
);
3143 case SOUND_MIXER_RECSRC
:
3144 val
= ad1843_get_recsrc(&devc
->lith
);
3147 case SOUND_MIXER_OUTSRC
:
3148 val
= ad1843_get_outsrc(&devc
->lith
);
3154 return put_user(val
, (int *) arg
);
3157 /* mixer_write_ioctl handles all write ioctls on the mixer device. */
3159 static int mixer_write_ioctl(vwsnd_dev_t
*devc
, unsigned int nr
, caddr_t arg
)
3164 DBGEV("(devc=0x%p, nr=0x%x, arg=0x%p)\n", devc
, nr
, arg
);
3166 err
= get_user(val
, (int *) arg
);
3170 case SOUND_MIXER_PCM
:
3171 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_PCM
, val
);
3174 case SOUND_MIXER_LINE
:
3175 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_LINE
, val
);
3178 case SOUND_MIXER_MIC
:
3179 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_MIC
, val
);
3182 case SOUND_MIXER_CD
:
3183 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_CD
, val
);
3186 case SOUND_MIXER_RECLEV
:
3187 val
= ad1843_set_gain(&devc
->lith
, &ad1843_gain_RECLEV
, val
);
3190 case SOUND_MIXER_RECSRC
:
3191 if (devc
->rport
.swbuf
|| devc
->wport
.swbuf
)
3192 return -EBUSY
; /* can't change recsrc while running */
3193 val
= ad1843_set_recsrc(&devc
->lith
, val
);
3196 case SOUND_MIXER_OUTSRC
:
3197 val
= ad1843_set_outsrc(&devc
->lith
, val
);
3205 return put_user(val
, (int *) arg
);
3208 /* This is the ioctl entry to the mixer driver. */
3210 static int vwsnd_mixer_ioctl(struct inode
*ioctl
,
3215 vwsnd_dev_t
*devc
= (vwsnd_dev_t
*) file
->private_data
;
3216 const unsigned int nrmask
= _IOC_NRMASK
<< _IOC_NRSHIFT
;
3217 const unsigned int nr
= (cmd
& nrmask
) >> _IOC_NRSHIFT
;
3220 DBGEV("(devc=0x%p, cmd=0x%x, arg=0x%lx)\n", devc
, cmd
, arg
);
3222 down(&devc
->mix_sema
);
3224 if ((cmd
& ~nrmask
) == MIXER_READ(0))
3225 retval
= mixer_read_ioctl(devc
, nr
, (caddr_t
) arg
);
3226 else if ((cmd
& ~nrmask
) == MIXER_WRITE(0))
3227 retval
= mixer_write_ioctl(devc
, nr
, (caddr_t
) arg
);
3231 up(&devc
->mix_sema
);
3235 static struct file_operations vwsnd_mixer_fops
= {
3237 llseek
: vwsnd_mixer_llseek
,
3238 ioctl
: vwsnd_mixer_ioctl
,
3239 open
: vwsnd_mixer_open
,
3240 release
: vwsnd_mixer_release
,
3243 /*****************************************************************************/
3244 /* probe/attach/unload */
3246 /* driver probe routine. Return nonzero if hardware is found. */
3248 static int __init
probe_vwsnd(struct address_info
*hw_config
)
3252 unsigned long later
;
3254 DBGEV("(hw_config=0x%p)\n", hw_config
);
3256 /* XXX verify lithium present (to prevent crash on non-vw) */
3258 if (li_create(&lith
, hw_config
->io_base
) != 0) {
3259 printk(KERN_WARNING
"probe_vwsnd: can't map lithium\n");
3262 later
= jiffies
+ 2;
3263 li_writel(&lith
, LI_HOST_CONTROLLER
, LI_HC_LINK_ENABLE
);
3265 w
= li_readl(&lith
, LI_HOST_CONTROLLER
);
3266 } while (w
== LI_HC_LINK_ENABLE
&& jiffies
< later
);
3270 DBGPV("HC = 0x%04x\n", w
);
3272 if ((w
== LI_HC_LINK_ENABLE
) || (w
& LI_HC_LINK_CODEC
)) {
3274 /* This may indicate a beta machine with no audio,
3275 * or a future machine with different audio.
3276 * On beta-release 320 w/ no audio, HC == 0x4000 */
3278 printk(KERN_WARNING
"probe_vwsnd: audio codec not found\n");
3282 if (w
& LI_HC_LINK_FAILURE
) {
3283 printk(KERN_WARNING
"probe_vwsnd: can't init audio codec\n");
3287 printk(KERN_INFO
"probe_vwsnd: lithium audio found\n");
3293 * driver attach routine. Initialize driver data structures and
3294 * initialize hardware. A new vwsnd_dev_t is allocated and put
3295 * onto the global list, vwsnd_dev_list.
3297 * Return +minor_dev on success, -errno on failure.
3300 static int __init
attach_vwsnd(struct address_info
*hw_config
)
3302 vwsnd_dev_t
*devc
= NULL
;
3305 DBGEV("(hw_config=0x%p)\n", hw_config
);
3307 devc
= kmalloc(sizeof (vwsnd_dev_t
), GFP_KERNEL
);
3311 err
= li_create(&devc
->lith
, hw_config
->io_base
);
3315 init_waitqueue(&devc
->open_wait
);
3317 devc
->rport
.hwbuf_size
= HWBUF_SIZE
;
3318 devc
->rport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3319 if (!devc
->rport
.hwbuf_vaddr
)
3321 devc
->rport
.hwbuf
= (caddr_t
) devc
->rport
.hwbuf_vaddr
;
3322 devc
->rport
.hwbuf_paddr
= virt_to_phys(devc
->rport
.hwbuf
);
3325 * Quote from the NT driver:
3327 * // WARNING!!! HACK to setup output dma!!!
3328 * // This is required because even on output there is some data
3329 * // trickling into the input DMA channel. This is a bug in the
3330 * // Lithium microcode.
3333 * We set the input side's DMA base address here. It will remain
3334 * valid until the driver is unloaded.
3337 li_writel(&devc
->lith
, LI_COMM1_BASE
,
3338 devc
->rport
.hwbuf_paddr
>> 8 | 1 << (37 - 8));
3340 devc
->wport
.hwbuf_size
= HWBUF_SIZE
;
3341 devc
->wport
.hwbuf_vaddr
= __get_free_pages(GFP_KERNEL
, HWBUF_ORDER
);
3342 if (!devc
->wport
.hwbuf_vaddr
)
3344 devc
->wport
.hwbuf
= (caddr_t
) devc
->wport
.hwbuf_vaddr
;
3345 devc
->wport
.hwbuf_paddr
= virt_to_phys(devc
->wport
.hwbuf
);
3346 DBGP("wport hwbuf = 0x%p\n", devc
->wport
.hwbuf
);
3349 err
= ad1843_init(&devc
->lith
);
3354 /* install interrupt handler */
3356 err
= request_irq(hw_config
->irq
, vwsnd_audio_intr
, 0, "vwsnd", devc
);
3360 /* register this device's drivers. */
3362 devc
->audio_minor
= register_sound_dsp(&vwsnd_audio_fops
, -1);
3363 if ((err
= devc
->audio_minor
) < 0) {
3364 DBGDO(printk(KERN_WARNING
3365 "attach_vwsnd: register_sound_dsp error %d\n",
3369 devc
->mixer_minor
= register_sound_mixer(&vwsnd_mixer_fops
,
3370 devc
->audio_minor
>> 4);
3371 if ((err
= devc
->mixer_minor
) < 0) {
3372 DBGDO(printk(KERN_WARNING
3373 "attach_vwsnd: register_sound_mixer error %d\n",
3378 /* Squirrel away device indices for unload routine. */
3380 hw_config
->slots
[0] = devc
->audio_minor
;
3382 /* Initialize as much of *devc as possible */
3384 devc
->open_sema
= MUTEX
;
3385 devc
->io_sema
= MUTEX
;
3386 devc
->mix_sema
= MUTEX
;
3387 devc
->open_mode
= 0;
3388 devc
->rport
.lock
= SPIN_LOCK_UNLOCKED
;
3389 init_waitqueue(&devc
->rport
.queue
);
3390 devc
->rport
.swstate
= SW_OFF
;
3391 devc
->rport
.hwstate
= HW_STOPPED
;
3392 devc
->rport
.flags
= 0;
3393 devc
->rport
.swbuf
= NULL
;
3394 devc
->wport
.lock
= SPIN_LOCK_UNLOCKED
;
3395 init_waitqueue(&devc
->wport
.queue
);
3396 devc
->wport
.swstate
= SW_OFF
;
3397 devc
->wport
.hwstate
= HW_STOPPED
;
3398 devc
->wport
.flags
= 0;
3399 devc
->wport
.swbuf
= NULL
;
3401 /* Success. Link us onto the local device list. */
3403 devc
->next_dev
= vwsnd_dev_list
;
3404 vwsnd_dev_list
= devc
;
3405 return devc
->audio_minor
;
3407 /* So many ways to fail. Undo what we did. */
3410 unregister_sound_dsp(devc
->audio_minor
);
3412 free_irq(hw_config
->irq
, devc
);
3415 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3417 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3419 li_destroy(&devc
->lith
);
3426 static int __exit
unload_vwsnd(struct address_info
*hw_config
)
3428 vwsnd_dev_t
*devc
, **devcp
;
3432 devcp
= &vwsnd_dev_list
;
3433 while ((devc
= *devcp
)) {
3434 if (devc
->audio_minor
== hw_config
->slots
[0]) {
3435 *devcp
= devc
->next_dev
;
3438 devcp
= &devc
->next_dev
;
3444 unregister_sound_mixer(devc
->mixer_minor
);
3445 unregister_sound_dsp(devc
->audio_minor
);
3446 free_irq(hw_config
->irq
, devc
);
3447 free_pages(devc
->wport
.hwbuf_vaddr
, HWBUF_ORDER
);
3448 free_pages(devc
->rport
.hwbuf_vaddr
, HWBUF_ORDER
);
3449 li_destroy(&devc
->lith
);
3455 /*****************************************************************************/
3456 /* initialization and loadable kernel module interface */
3458 static struct address_info the_hw_config
= {
3459 0xFF001000, /* lithium phys addr */
3460 CO_IRQ(CO_APIC_LI_AUDIO
) /* irq */
3463 MODULE_DESCRIPTION("SGI Visual Workstation sound module");
3464 MODULE_AUTHOR("Bob Miller <kbob@sgi.com>");
3466 static int __init
init_vwsnd(void)
3471 DBGXV("sound::vwsnd::init_module()\n");
3473 if(!probe_vwsnd(&the_hw_config
))
3475 err
= attach_vwsnd(&the_hw_config
);
3481 static void __exit
cleanup_vwsnd(void)
3483 DBGX("sound::vwsnd::cleanup_module()\n");
3485 unload_vwsnd(&the_hw_config
);
3488 module_init(init_vwsnd
);
3489 module_exit(cleanup_vwsnd
);