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Ok. I didn't make 2.4.0 in 2000. Tough. I tried, but we had some
[davej-history.git] / drivers / scsi / qlogicisp.c
blob4f3350e996512347a3c9b927f3ce06ac0b9c46dd
1 /*
2 * QLogic ISP1020 Intelligent SCSI Processor Driver (PCI)
3 * Written by Erik H. Moe, ehm@cris.com
4 * Copyright 1995, Erik H. Moe
5 * Copyright 1996, 1997 Michael A. Griffith <grif@acm.org>
6 * Copyright 2000, Jayson C. Vantuyl <vantuyl@csc.smsu.edu>
7 * and Bryon W. Roche <bryon@csc.smsu.edu>
8 *
9 * 64-bit addressing added by Kanoj Sarcar <kanoj@sgi.com>
10 * and Leo Dagum <dagum@sgi.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2, or (at your option) any
15 * later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 */
22
23 #include <linux/blk.h>
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ioport.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/pci.h>
31 #include <linux/delay.h>
32 #include <linux/unistd.h>
33 #include <linux/spinlock.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/byteorder.h>
37
38 #include "sd.h"
39 #include "hosts.h"
40 #include "qlogicisp.h"
41
42 /* Configuration section *****************************************************/
43
44 /* Set the following macro to 1 to reload the ISP1020's firmware. This is
45 the latest firmware provided by QLogic. This may be an earlier/later
46 revision than supplied by your board. */
47
48 #define RELOAD_FIRMWARE 1
49
50 /* Set the following macro to 1 to reload the ISP1020's defaults from nvram.
51 If you are not sure of your settings, leave this alone, the driver will
52 use a set of 'safe' defaults */
53
54 #define USE_NVRAM_DEFAULTS 0
55
56 /* Macros used for debugging */
57
58 #define DEBUG_ISP1020 0
59 #define DEBUG_ISP1020_INTR 0
60 #define DEBUG_ISP1020_SETUP 0
61 #define TRACE_ISP 0
62
63 #define DEFAULT_LOOP_COUNT 1000000
64
65 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
66
67 /* End Configuration section *************************************************/
68
69 #include <linux/module.h>
70
71 #if TRACE_ISP
72
73 # define TRACE_BUF_LEN (32*1024)
74
75 struct {
76 u_long next;
77 struct {
78 u_long time;
79 u_int index;
80 u_int addr;
81 u_char * name;
82 } buf[TRACE_BUF_LEN];
83 } trace;
84
85 #define TRACE(w, i, a) \
86 { \
87 unsigned long flags; \
88 \
89 save_flags(flags); \
90 cli(); \
91 trace.buf[trace.next].name = (w); \
92 trace.buf[trace.next].time = jiffies; \
93 trace.buf[trace.next].index = (i); \
94 trace.buf[trace.next].addr = (long) (a); \
95 trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1); \
96 restore_flags(flags); \
97 }
98
99 #else
100 # define TRACE(w, i, a)
101 #endif
102
103 #if DEBUG_ISP1020
104 #define ENTER(x) printk("isp1020 : entering %s()\n", x);
105 #define LEAVE(x) printk("isp1020 : leaving %s()\n", x);
106 #define DEBUG(x) x
107 #else
108 #define ENTER(x)
109 #define LEAVE(x)
110 #define DEBUG(x)
111 #endif /* DEBUG_ISP1020 */
112
113 #if DEBUG_ISP1020_INTR
114 #define ENTER_INTR(x) printk("isp1020 : entering %s()\n", x);
115 #define LEAVE_INTR(x) printk("isp1020 : leaving %s()\n", x);
116 #define DEBUG_INTR(x) x
117 #else
118 #define ENTER_INTR(x)
119 #define LEAVE_INTR(x)
120 #define DEBUG_INTR(x)
121 #endif /* DEBUG ISP1020_INTR */
122
123 #define ISP1020_REV_ID 1
124
125 #define MAX_TARGETS 16
126 #define MAX_LUNS 8
127
128 /* host configuration and control registers */
129 #define HOST_HCCR 0xc0 /* host command and control */
130
131 /* pci bus interface registers */
132 #define PCI_ID_LOW 0x00 /* vendor id */
133 #define PCI_ID_HIGH 0x02 /* device id */
134 #define ISP_CFG0 0x04 /* configuration register #0 */
135 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
136 #define ISP_CFG0_1020 0x0001 /* ISP1020 */
137 #define ISP_CFG0_1020A 0x0002 /* ISP1020A */
138 #define ISP_CFG0_1040 0x0003 /* ISP1040 */
139 #define ISP_CFG0_1040A 0x0004 /* ISP1040A */
140 #define ISP_CFG0_1040B 0x0005 /* ISP1040B */
141 #define ISP_CFG0_1040C 0x0006 /* ISP1040C */
142 #define ISP_CFG1 0x06 /* configuration register #1 */
143 #define ISP_CFG1_F128 0x0040 /* 128-byte FIFO threshold */
144 #define ISP_CFG1_F64 0x0030 /* 128-byte FIFO threshold */
145 #define ISP_CFG1_F32 0x0020 /* 128-byte FIFO threshold */
146 #define ISP_CFG1_F16 0x0010 /* 128-byte FIFO threshold */
147 #define ISP_CFG1_BENAB 0x0004 /* Global Bus burst enable */
148 #define ISP_CFG1_SXP 0x0001 /* SXP register select */
149 #define PCI_INTF_CTL 0x08 /* pci interface control */
150 #define PCI_INTF_STS 0x0a /* pci interface status */
151 #define PCI_SEMAPHORE 0x0c /* pci semaphore */
152 #define PCI_NVRAM 0x0e /* pci nvram interface */
153 #define CDMA_CONF 0x20 /* Command DMA Config */
154 #define DDMA_CONF 0x40 /* Data DMA Config */
155 #define DMA_CONF_SENAB 0x0008 /* SXP to DMA Data enable */
156 #define DMA_CONF_RIRQ 0x0004 /* RISC interrupt enable */
157 #define DMA_CONF_BENAB 0x0002 /* Bus burst enable */
158 #define DMA_CONF_DIR 0x0001 /* DMA direction (0=fifo->host 1=host->fifo) */
159
160 /* mailbox registers */
161 #define MBOX0 0x70 /* mailbox 0 */
162 #define MBOX1 0x72 /* mailbox 1 */
163 #define MBOX2 0x74 /* mailbox 2 */
164 #define MBOX3 0x76 /* mailbox 3 */
165 #define MBOX4 0x78 /* mailbox 4 */
166 #define MBOX5 0x7a /* mailbox 5 */
167 #define MBOX6 0x7c /* mailbox 6 */
168 #define MBOX7 0x7e /* mailbox 7 */
169
170 /* mailbox command complete status codes */
171 #define MBOX_COMMAND_COMPLETE 0x4000
172 #define INVALID_COMMAND 0x4001
173 #define HOST_INTERFACE_ERROR 0x4002
174 #define TEST_FAILED 0x4003
175 #define COMMAND_ERROR 0x4005
176 #define COMMAND_PARAM_ERROR 0x4006
177
178 /* async event status codes */
179 #define ASYNC_SCSI_BUS_RESET 0x8001
180 #define SYSTEM_ERROR 0x8002
181 #define REQUEST_TRANSFER_ERROR 0x8003
182 #define RESPONSE_TRANSFER_ERROR 0x8004
183 #define REQUEST_QUEUE_WAKEUP 0x8005
184 #define EXECUTION_TIMEOUT_RESET 0x8006
185
186 #ifdef CONFIG_QL_ISP_A64
187 #define IOCB_SEGS 2
188 #define CONTINUATION_SEGS 5
189 #define MAX_CONTINUATION_ENTRIES 254
190 #else
191 #define IOCB_SEGS 4
192 #define CONTINUATION_SEGS 7
193 #endif /* CONFIG_QL_ISP_A64 */
194
195 struct Entry_header {
196 u_char entry_type;
197 u_char entry_cnt;
198 u_char sys_def_1;
199 u_char flags;
200 };
201
202 /* entry header type commands */
203 #ifdef CONFIG_QL_ISP_A64
204 #define ENTRY_COMMAND 9
205 #define ENTRY_CONTINUATION 0xa
206 #else
207 #define ENTRY_COMMAND 1
208 #define ENTRY_CONTINUATION 2
209 #endif /* CONFIG_QL_ISP_A64 */
210
211 #define ENTRY_STATUS 3
212 #define ENTRY_MARKER 4
213 #define ENTRY_EXTENDED_COMMAND 5
214
215 /* entry header flag definitions */
216 #define EFLAG_CONTINUATION 1
217 #define EFLAG_BUSY 2
218 #define EFLAG_BAD_HEADER 4
219 #define EFLAG_BAD_PAYLOAD 8
220
221 struct dataseg {
222 u_int d_base;
223 #ifdef CONFIG_QL_ISP_A64
224 u_int d_base_hi;
225 #endif
226 u_int d_count;
227 };
228
229 struct Command_Entry {
230 struct Entry_header hdr;
231 u_int handle;
232 u_char target_lun;
233 u_char target_id;
234 u_short cdb_length;
235 u_short control_flags;
236 u_short rsvd;
237 u_short time_out;
238 u_short segment_cnt;
239 u_char cdb[12];
240 #ifdef CONFIG_QL_ISP_A64
241 u_int rsvd1;
242 u_int rsvd2;
243 #endif
244 struct dataseg dataseg[IOCB_SEGS];
245 };
246
247 /* command entry control flag definitions */
248 #define CFLAG_NODISC 0x01
249 #define CFLAG_HEAD_TAG 0x02
250 #define CFLAG_ORDERED_TAG 0x04
251 #define CFLAG_SIMPLE_TAG 0x08
252 #define CFLAG_TAR_RTN 0x10
253 #define CFLAG_READ 0x20
254 #define CFLAG_WRITE 0x40
255
256 struct Ext_Command_Entry {
257 struct Entry_header hdr;
258 u_int handle;
259 u_char target_lun;
260 u_char target_id;
261 u_short cdb_length;
262 u_short control_flags;
263 u_short rsvd;
264 u_short time_out;
265 u_short segment_cnt;
266 u_char cdb[44];
267 };
268
269 struct Continuation_Entry {
270 struct Entry_header hdr;
271 #ifndef CONFIG_QL_ISP_A64
272 u_int reserved;
273 #endif
274 struct dataseg dataseg[CONTINUATION_SEGS];
275 };
276
277 struct Marker_Entry {
278 struct Entry_header hdr;
279 u_int reserved;
280 u_char target_lun;
281 u_char target_id;
282 u_char modifier;
283 u_char rsvd;
284 u_char rsvds[52];
285 };
286
287 /* marker entry modifier definitions */
288 #define SYNC_DEVICE 0
289 #define SYNC_TARGET 1
290 #define SYNC_ALL 2
291
292 struct Status_Entry {
293 struct Entry_header hdr;
294 u_int handle;
295 u_short scsi_status;
296 u_short completion_status;
297 u_short state_flags;
298 u_short status_flags;
299 u_short time;
300 u_short req_sense_len;
301 u_int residual;
302 u_char rsvd[8];
303 u_char req_sense_data[32];
304 };
305
306 /* status entry completion status definitions */
307 #define CS_COMPLETE 0x0000
308 #define CS_INCOMPLETE 0x0001
309 #define CS_DMA_ERROR 0x0002
310 #define CS_TRANSPORT_ERROR 0x0003
311 #define CS_RESET_OCCURRED 0x0004
312 #define CS_ABORTED 0x0005
313 #define CS_TIMEOUT 0x0006
314 #define CS_DATA_OVERRUN 0x0007
315 #define CS_COMMAND_OVERRUN 0x0008
316 #define CS_STATUS_OVERRUN 0x0009
317 #define CS_BAD_MESSAGE 0x000a
318 #define CS_NO_MESSAGE_OUT 0x000b
319 #define CS_EXT_ID_FAILED 0x000c
320 #define CS_IDE_MSG_FAILED 0x000d
321 #define CS_ABORT_MSG_FAILED 0x000e
322 #define CS_REJECT_MSG_FAILED 0x000f
323 #define CS_NOP_MSG_FAILED 0x0010
324 #define CS_PARITY_ERROR_MSG_FAILED 0x0011
325 #define CS_DEVICE_RESET_MSG_FAILED 0x0012
326 #define CS_ID_MSG_FAILED 0x0013
327 #define CS_UNEXP_BUS_FREE 0x0014
328 #define CS_DATA_UNDERRUN 0x0015
329
330 /* status entry state flag definitions */
331 #define SF_GOT_BUS 0x0100
332 #define SF_GOT_TARGET 0x0200
333 #define SF_SENT_CDB 0x0400
334 #define SF_TRANSFERRED_DATA 0x0800
335 #define SF_GOT_STATUS 0x1000
336 #define SF_GOT_SENSE 0x2000
337
338 /* status entry status flag definitions */
339 #define STF_DISCONNECT 0x0001
340 #define STF_SYNCHRONOUS 0x0002
341 #define STF_PARITY_ERROR 0x0004
342 #define STF_BUS_RESET 0x0008
343 #define STF_DEVICE_RESET 0x0010
344 #define STF_ABORTED 0x0020
345 #define STF_TIMEOUT 0x0040
346 #define STF_NEGOTIATION 0x0080
347
348 /* interface control commands */
349 #define ISP_RESET 0x0001
350 #define ISP_EN_INT 0x0002
351 #define ISP_EN_RISC 0x0004
352
353 /* host control commands */
354 #define HCCR_NOP 0x0000
355 #define HCCR_RESET 0x1000
356 #define HCCR_PAUSE 0x2000
357 #define HCCR_RELEASE 0x3000
358 #define HCCR_SINGLE_STEP 0x4000
359 #define HCCR_SET_HOST_INTR 0x5000
360 #define HCCR_CLEAR_HOST_INTR 0x6000
361 #define HCCR_CLEAR_RISC_INTR 0x7000
362 #define HCCR_BP_ENABLE 0x8000
363 #define HCCR_BIOS_DISABLE 0x9000
364 #define HCCR_TEST_MODE 0xf000
365
366 #define RISC_BUSY 0x0004
367
368 /* mailbox commands */
369 #define MBOX_NO_OP 0x0000
370 #define MBOX_LOAD_RAM 0x0001
371 #define MBOX_EXEC_FIRMWARE 0x0002
372 #define MBOX_DUMP_RAM 0x0003
373 #define MBOX_WRITE_RAM_WORD 0x0004
374 #define MBOX_READ_RAM_WORD 0x0005
375 #define MBOX_MAILBOX_REG_TEST 0x0006
376 #define MBOX_VERIFY_CHECKSUM 0x0007
377 #define MBOX_ABOUT_FIRMWARE 0x0008
378 #define MBOX_CHECK_FIRMWARE 0x000e
379 #define MBOX_INIT_REQ_QUEUE 0x0010
380 #define MBOX_INIT_RES_QUEUE 0x0011
381 #define MBOX_EXECUTE_IOCB 0x0012
382 #define MBOX_WAKE_UP 0x0013
383 #define MBOX_STOP_FIRMWARE 0x0014
384 #define MBOX_ABORT 0x0015
385 #define MBOX_ABORT_DEVICE 0x0016
386 #define MBOX_ABORT_TARGET 0x0017
387 #define MBOX_BUS_RESET 0x0018
388 #define MBOX_STOP_QUEUE 0x0019
389 #define MBOX_START_QUEUE 0x001a
390 #define MBOX_SINGLE_STEP_QUEUE 0x001b
391 #define MBOX_ABORT_QUEUE 0x001c
392 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
393 #define MBOX_GET_FIRMWARE_STATUS 0x001f
394 #define MBOX_GET_INIT_SCSI_ID 0x0020
395 #define MBOX_GET_SELECT_TIMEOUT 0x0021
396 #define MBOX_GET_RETRY_COUNT 0x0022
397 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
398 #define MBOX_GET_CLOCK_RATE 0x0024
399 #define MBOX_GET_ACT_NEG_STATE 0x0025
400 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
401 #define MBOX_GET_PCI_PARAMS 0x0027
402 #define MBOX_GET_TARGET_PARAMS 0x0028
403 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
404 #define MBOX_SET_INIT_SCSI_ID 0x0030
405 #define MBOX_SET_SELECT_TIMEOUT 0x0031
406 #define MBOX_SET_RETRY_COUNT 0x0032
407 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
408 #define MBOX_SET_CLOCK_RATE 0x0034
409 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
410 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
411 #define MBOX_SET_PCI_CONTROL_PARAMS 0x0037
412 #define MBOX_SET_TARGET_PARAMS 0x0038
413 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
414 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
415 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
416 #define MBOX_EXEC_BIOS_IOCB 0x0042
417
418 #ifdef CONFIG_QL_ISP_A64
419 #define MBOX_CMD_INIT_REQUEST_QUEUE_64 0x0052
420 #define MBOX_CMD_INIT_RESPONSE_QUEUE_64 0x0053
421 #endif /* CONFIG_QL_ISP_A64 */
422
423 #include "qlogicisp_asm.c"
424
425 #define PACKB(a, b) (((a)<<4)|(b))
426
427 static const u_char mbox_param[] = {
428 PACKB(1, 1), /* MBOX_NO_OP */
429 PACKB(5, 5), /* MBOX_LOAD_RAM */
430 PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
431 PACKB(5, 5), /* MBOX_DUMP_RAM */
432 PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
433 PACKB(2, 3), /* MBOX_READ_RAM_WORD */
434 PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
435 PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
436 PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
437 PACKB(0, 0), /* 0x0009 */
438 PACKB(0, 0), /* 0x000a */
439 PACKB(0, 0), /* 0x000b */
440 PACKB(0, 0), /* 0x000c */
441 PACKB(0, 0), /* 0x000d */
442 PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
443 PACKB(0, 0), /* 0x000f */
444 PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
445 PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
446 PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
447 PACKB(2, 2), /* MBOX_WAKE_UP */
448 PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
449 PACKB(4, 4), /* MBOX_ABORT */
450 PACKB(2, 2), /* MBOX_ABORT_DEVICE */
451 PACKB(3, 3), /* MBOX_ABORT_TARGET */
452 PACKB(2, 2), /* MBOX_BUS_RESET */
453 PACKB(2, 3), /* MBOX_STOP_QUEUE */
454 PACKB(2, 3), /* MBOX_START_QUEUE */
455 PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
456 PACKB(2, 3), /* MBOX_ABORT_QUEUE */
457 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
458 PACKB(0, 0), /* 0x001e */
459 PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
460 PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
461 PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
462 PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
463 PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
464 PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
465 PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
466 PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
467 PACKB(1, 3), /* MBOX_GET_PCI_PARAMS */
468 PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
469 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
470 PACKB(0, 0), /* 0x002a */
471 PACKB(0, 0), /* 0x002b */
472 PACKB(0, 0), /* 0x002c */
473 PACKB(0, 0), /* 0x002d */
474 PACKB(0, 0), /* 0x002e */
475 PACKB(0, 0), /* 0x002f */
476 PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
477 PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
478 PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
479 PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
480 PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
481 PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
482 PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
483 PACKB(3, 3), /* MBOX_SET_PCI_CONTROL_PARAMS */
484 PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
485 PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
486 PACKB(0, 0), /* 0x003a */
487 PACKB(0, 0), /* 0x003b */
488 PACKB(0, 0), /* 0x003c */
489 PACKB(0, 0), /* 0x003d */
490 PACKB(0, 0), /* 0x003e */
491 PACKB(0, 0), /* 0x003f */
492 PACKB(1, 2), /* MBOX_RETURN_BIOS_BLOCK_ADDR */
493 PACKB(6, 1), /* MBOX_WRITE_FOUR_RAM_WORDS */
494 PACKB(2, 3) /* MBOX_EXEC_BIOS_IOCB */
495 #ifdef CONFIG_QL_ISP_A64
496 ,PACKB(0, 0), /* 0x0043 */
497 PACKB(0, 0), /* 0x0044 */
498 PACKB(0, 0), /* 0x0045 */
499 PACKB(0, 0), /* 0x0046 */
500 PACKB(0, 0), /* 0x0047 */
501 PACKB(0, 0), /* 0x0048 */
502 PACKB(0, 0), /* 0x0049 */
503 PACKB(0, 0), /* 0x004a */
504 PACKB(0, 0), /* 0x004b */
505 PACKB(0, 0), /* 0x004c */
506 PACKB(0, 0), /* 0x004d */
507 PACKB(0, 0), /* 0x004e */
508 PACKB(0, 0), /* 0x004f */
509 PACKB(0, 0), /* 0x0050 */
510 PACKB(0, 0), /* 0x0051 */
511 PACKB(8, 8), /* MBOX_CMD_INIT_REQUEST_QUEUE_64 (0x0052) */
512 PACKB(8, 8) /* MBOX_CMD_INIT_RESPONSE_QUEUE_64 (0x0053) */
513 #endif /* CONFIG_QL_ISP_A64 */
514 };
515
516 #define MAX_MBOX_COMMAND (sizeof(mbox_param)/sizeof(u_short))
517
518 struct host_param {
519 u_short fifo_threshold;
520 u_short host_adapter_enable;
521 u_short initiator_scsi_id;
522 u_short bus_reset_delay;
523 u_short retry_count;
524 u_short retry_delay;
525 u_short async_data_setup_time;
526 u_short req_ack_active_negation;
527 u_short data_line_active_negation;
528 u_short data_dma_burst_enable;
529 u_short command_dma_burst_enable;
530 u_short tag_aging;
531 u_short selection_timeout;
532 u_short max_queue_depth;
533 };
534
535 /*
536 * Device Flags:
537 *
538 * Bit Name
539 * ---------
540 * 7 Disconnect Privilege
541 * 6 Parity Checking
542 * 5 Wide Data Transfers
543 * 4 Synchronous Data Transfers
544 * 3 Tagged Queuing
545 * 2 Automatic Request Sense
546 * 1 Stop Queue on Check Condition
547 * 0 Renegotiate on Error
548 */
549
550 struct dev_param {
551 u_short device_flags;
552 u_short execution_throttle;
553 u_short synchronous_period;
554 u_short synchronous_offset;
555 u_short device_enable;
556 u_short reserved; /* pad */
557 };
558
559 /*
560 * The result queue can be quite a bit smaller since continuation entries
561 * do not show up there:
562 */
563 #define RES_QUEUE_LEN ((QLOGICISP_REQ_QUEUE_LEN + 1) / 8 - 1)
564 #define QUEUE_ENTRY_LEN 64
565 #define QSIZE(entries) (((entries) + 1) * QUEUE_ENTRY_LEN)
566
567 struct isp_queue_entry {
568 char __opaque[QUEUE_ENTRY_LEN];
569 };
570
571 struct isp1020_hostdata {
572 u_long memaddr;
573 u_char revision;
574 struct host_param host_param;
575 struct dev_param dev_param[MAX_TARGETS];
576 struct pci_dev *pci_dev;
577
578 struct isp_queue_entry *res_cpu; /* CPU-side address of response queue. */
579 struct isp_queue_entry *req_cpu; /* CPU-size address of request queue. */
580
581 /* result and request queues (shared with isp1020): */
582 u_int req_in_ptr; /* index of next request slot */
583 u_int res_out_ptr; /* index of next result slot */
584
585 /* this is here so the queues are nicely aligned */
586 long send_marker; /* do we need to send a marker? */
587
588 /* The cmd->handle has a fixed size, and is only 32-bits. We
589 * need to take care to handle 64-bit systems correctly thus what
590 * we actually place in cmd->handle is an index to the following
591 * table. Kudos to Matt Jacob for the technique. -DaveM
592 */
593 Scsi_Cmnd *cmd_slots[QLOGICISP_REQ_QUEUE_LEN + 1];
594
595 dma_addr_t res_dma; /* PCI side view of response queue */
596 dma_addr_t req_dma; /* PCI side view of request queue */
597 };
598
599 /* queue length's _must_ be power of two: */
600 #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
601 #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
602 QLOGICISP_REQ_QUEUE_LEN)
603 #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
604
605 static void isp1020_enable_irqs(struct Scsi_Host *);
606 static void isp1020_disable_irqs(struct Scsi_Host *);
607 static int isp1020_init(struct Scsi_Host *);
608 static int isp1020_reset_hardware(struct Scsi_Host *);
609 static int isp1020_set_defaults(struct Scsi_Host *);
610 static int isp1020_load_parameters(struct Scsi_Host *);
611 static int isp1020_mbox_command(struct Scsi_Host *, u_short []);
612 static int isp1020_return_status(struct Status_Entry *);
613 static void isp1020_intr_handler(int, void *, struct pt_regs *);
614 static void do_isp1020_intr_handler(int, void *, struct pt_regs *);
615
616 #if USE_NVRAM_DEFAULTS
617 static int isp1020_get_defaults(struct Scsi_Host *);
618 static int isp1020_verify_nvram(struct Scsi_Host *);
619 static u_short isp1020_read_nvram_word(struct Scsi_Host *, u_short);
620 #endif
621
622 #if DEBUG_ISP1020
623 static void isp1020_print_scsi_cmd(Scsi_Cmnd *);
624 #endif
625 #if DEBUG_ISP1020_INTR
626 static void isp1020_print_status_entry(struct Status_Entry *);
627 #endif
628
629 /* memaddr should be used to determine if memmapped port i/o is being used
630 * non-null memaddr == mmap'd
631 * JV 7-Jan-2000
632 */
633 static inline u_short isp_inw(struct Scsi_Host *host, long offset)
634 {
635 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
636 if (h->memaddr)
637 return readw(h->memaddr + offset);
638 else
639 return inw(host->io_port + offset);
640 }
641
642 static inline void isp_outw(u_short val, struct Scsi_Host *host, long offset)
643 {
644 struct isp1020_hostdata *h = (struct isp1020_hostdata *)host->hostdata;
645 if (h->memaddr)
646 writew(val, h->memaddr + offset);
647 else
648 outw(val, host->io_port + offset);
649 }
650
651 static inline void isp1020_enable_irqs(struct Scsi_Host *host)
652 {
653 isp_outw(ISP_EN_INT|ISP_EN_RISC, host, PCI_INTF_CTL);
654 }
655
656
657 static inline void isp1020_disable_irqs(struct Scsi_Host *host)
658 {
659 isp_outw(0x0, host, PCI_INTF_CTL);
660 }
661
662
663 int isp1020_detect(Scsi_Host_Template *tmpt)
664 {
665 int hosts = 0;
666 struct Scsi_Host *host;
667 struct isp1020_hostdata *hostdata;
668 struct pci_dev *pdev = NULL;
669
670 ENTER("isp1020_detect");
671
672 tmpt->proc_name = "isp1020";
673
674 if (pci_present() == 0) {
675 printk("qlogicisp : PCI not present\n");
676 return 0;
677 }
678
679 while ((pdev = pci_find_device(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, pdev)))
680 {
681 if (pci_enable_device(pdev))
682 continue;
683
684 host = scsi_register(tmpt, sizeof(struct isp1020_hostdata));
685 hostdata = (struct isp1020_hostdata *) host->hostdata;
686
687 memset(hostdata, 0, sizeof(struct isp1020_hostdata));
688
689 hostdata->pci_dev = pdev;
690
691 if (isp1020_init(host))
692 goto fail_and_unregister;
693
694 if (isp1020_reset_hardware(host)
695 #if USE_NVRAM_DEFAULTS
696 || isp1020_get_defaults(host)
697 #else
698 || isp1020_set_defaults(host)
699 #endif /* USE_NVRAM_DEFAULTS */
700 || isp1020_load_parameters(host)) {
701 iounmap((void *)hostdata->memaddr);
702 release_region(host->io_port, 0xff);
703 goto fail_and_unregister;
704 }
705
706 host->this_id = hostdata->host_param.initiator_scsi_id;
707
708 if (request_irq(host->irq, do_isp1020_intr_handler, SA_INTERRUPT | SA_SHIRQ,
709 "qlogicisp", host))
710 {
711 printk("qlogicisp : interrupt %d already in use\n",
712 host->irq);
713 iounmap((void *)hostdata->memaddr);
714 release_region(host->io_port, 0xff);
715 goto fail_and_unregister;
716 }
717
718 isp_outw(0x0, host, PCI_SEMAPHORE);
719 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
720 isp1020_enable_irqs(host);
721
722 hosts++;
723 continue;
724
725 fail_and_unregister:
726 if (hostdata->res_cpu)
727 pci_free_consistent(hostdata->pci_dev,
728 QSIZE(RES_QUEUE_LEN),
729 hostdata->res_cpu,
730 hostdata->res_dma);
731 if (hostdata->req_cpu)
732 pci_free_consistent(hostdata->pci_dev,
733 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
734 hostdata->req_cpu,
735 hostdata->req_dma);
736 scsi_unregister(host);
737 }
738
739 LEAVE("isp1020_detect");
740
741 return hosts;
742 }
743
744
745 int isp1020_release(struct Scsi_Host *host)
746 {
747 struct isp1020_hostdata *hostdata;
748
749 ENTER("isp1020_release");
750
751 hostdata = (struct isp1020_hostdata *) host->hostdata;
752
753 isp_outw(0x0, host, PCI_INTF_CTL);
754 free_irq(host->irq, host);
755
756 iounmap((void *)hostdata->memaddr);
757
758 release_region(host->io_port, 0xff);
759
760 LEAVE("isp1020_release");
761
762 return 0;
763 }
764
765
766 const char *isp1020_info(struct Scsi_Host *host)
767 {
768 static char buf[80];
769 struct isp1020_hostdata *hostdata;
770
771 ENTER("isp1020_info");
772
773 hostdata = (struct isp1020_hostdata *) host->hostdata;
774 sprintf(buf,
775 "QLogic ISP1020 SCSI on PCI bus %02x device %02x irq %d %s base 0x%lx",
776 hostdata->pci_dev->bus->number, hostdata->pci_dev->devfn, host->irq,
777 (hostdata->memaddr ? "MEM" : "I/O"),
778 (hostdata->memaddr ? hostdata->memaddr : host->io_port));
779
780 LEAVE("isp1020_info");
781
782 return buf;
783 }
784
785
786 /*
787 * The middle SCSI layer ensures that queuecommand never gets invoked
788 * concurrently with itself or the interrupt handler (though the
789 * interrupt handler may call this routine as part of
790 * request-completion handling).
791 */
792 int isp1020_queuecommand(Scsi_Cmnd *Cmnd, void (*done)(Scsi_Cmnd *))
793 {
794 int i, n, num_free;
795 u_int in_ptr, out_ptr;
796 struct dataseg * ds;
797 struct scatterlist *sg;
798 struct Command_Entry *cmd;
799 struct Continuation_Entry *cont;
800 struct Scsi_Host *host;
801 struct isp1020_hostdata *hostdata;
802 dma_addr_t dma_addr;
803
804 ENTER("isp1020_queuecommand");
805
806 host = Cmnd->host;
807 hostdata = (struct isp1020_hostdata *) host->hostdata;
808 Cmnd->scsi_done = done;
809
810 DEBUG(isp1020_print_scsi_cmd(Cmnd));
811
812 out_ptr = isp_inw(host, + MBOX4);
813 in_ptr = hostdata->req_in_ptr;
814
815 DEBUG(printk("qlogicisp : request queue depth %d\n",
816 REQ_QUEUE_DEPTH(in_ptr, out_ptr)));
817
818 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
819 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
820 if (in_ptr == out_ptr) {
821 printk("qlogicisp : request queue overflow\n");
822 return 1;
823 }
824
825 if (hostdata->send_marker) {
826 struct Marker_Entry *marker;
827
828 TRACE("queue marker", in_ptr, 0);
829
830 DEBUG(printk("qlogicisp : adding marker entry\n"));
831 marker = (struct Marker_Entry *) cmd;
832 memset(marker, 0, sizeof(struct Marker_Entry));
833
834 marker->hdr.entry_type = ENTRY_MARKER;
835 marker->hdr.entry_cnt = 1;
836 marker->modifier = SYNC_ALL;
837
838 hostdata->send_marker = 0;
839
840 if (((in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN) == out_ptr) {
841 isp_outw(in_ptr, host, MBOX4);
842 hostdata->req_in_ptr = in_ptr;
843 printk("qlogicisp : request queue overflow\n");
844 return 1;
845 }
846 cmd = (struct Command_Entry *) &hostdata->req_cpu[in_ptr];
847 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
848 }
849
850 TRACE("queue command", in_ptr, Cmnd);
851
852 memset(cmd, 0, sizeof(struct Command_Entry));
853
854 cmd->hdr.entry_type = ENTRY_COMMAND;
855 cmd->hdr.entry_cnt = 1;
856
857 cmd->target_lun = Cmnd->lun;
858 cmd->target_id = Cmnd->target;
859 cmd->cdb_length = cpu_to_le16(Cmnd->cmd_len);
860 cmd->control_flags = cpu_to_le16(CFLAG_READ | CFLAG_WRITE);
861 cmd->time_out = cpu_to_le16(30);
862
863 memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
864
865 if (Cmnd->use_sg) {
866 int sg_count;
867
868 sg = (struct scatterlist *) Cmnd->request_buffer;
869 ds = cmd->dataseg;
870
871 sg_count = pci_map_sg(hostdata->pci_dev, sg, Cmnd->use_sg,
872 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
873
874 cmd->segment_cnt = cpu_to_le16(sg_count);
875
876 /* fill in first four sg entries: */
877 n = sg_count;
878 if (n > IOCB_SEGS)
879 n = IOCB_SEGS;
880 for (i = 0; i < n; i++) {
881 dma_addr = sg_dma_address(sg);
882 ds[i].d_base = cpu_to_le32((u32) dma_addr);
883 #ifdef CONFIG_QL_ISP_A64
884 ds[i].d_base_hi = cpu_to_le32((u32) (dma_addr>>32));
885 #endif /* CONFIG_QL_ISP_A64 */
886 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
887 ++sg;
888 }
889 sg_count -= IOCB_SEGS;
890
891 while (sg_count > 0) {
892 ++cmd->hdr.entry_cnt;
893 cont = (struct Continuation_Entry *)
894 &hostdata->req_cpu[in_ptr];
895 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
896 if (in_ptr == out_ptr) {
897 printk("isp1020: unexpected request queue "
898 "overflow\n");
899 return 1;
900 }
901 TRACE("queue continuation", in_ptr, 0);
902 cont->hdr.entry_type = ENTRY_CONTINUATION;
903 cont->hdr.entry_cnt = 0;
904 cont->hdr.sys_def_1 = 0;
905 cont->hdr.flags = 0;
906 #ifndef CONFIG_QL_ISP_A64
907 cont->reserved = 0;
908 #endif
909 ds = cont->dataseg;
910 n = sg_count;
911 if (n > CONTINUATION_SEGS)
912 n = CONTINUATION_SEGS;
913 for (i = 0; i < n; ++i) {
914 dma_addr = sg_dma_address(sg);
915 ds[i].d_base = cpu_to_le32((u32) dma_addr);
916 #ifdef CONFIG_QL_ISP_A64
917 ds[i].d_base_hi = cpu_to_le32((u32)(dma_addr>>32));
918 #endif /* CONFIG_QL_ISP_A64 */
919 ds[i].d_count = cpu_to_le32(sg_dma_len(sg));
920 ++sg;
921 }
922 sg_count -= n;
923 }
924 } else if (Cmnd->request_bufflen) {
925 /*Cmnd->SCp.ptr = (char *)(unsigned long)*/
926 dma_addr = pci_map_single(hostdata->pci_dev,
927 Cmnd->request_buffer,
928 Cmnd->request_bufflen,
929 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
930 Cmnd->SCp.ptr = (char *)(unsigned long) dma_addr;
931
932 cmd->dataseg[0].d_base =
933 cpu_to_le32((u32) dma_addr);
934 #ifdef CONFIG_QL_ISP_A64
935 cmd->dataseg[0].d_base_hi =
936 cpu_to_le32((u32) (dma_addr>>32));
937 #endif /* CONFIG_QL_ISP_A64 */
938 cmd->dataseg[0].d_count =
939 cpu_to_le32((u32)Cmnd->request_bufflen);
940 cmd->segment_cnt = cpu_to_le16(1);
941 } else {
942 cmd->dataseg[0].d_base = 0;
943 #ifdef CONFIG_QL_ISP_A64
944 cmd->dataseg[0].d_base_hi = 0;
945 #endif /* CONFIG_QL_ISP_A64 */
946 cmd->dataseg[0].d_count = 0;
947 cmd->segment_cnt = cpu_to_le16(1); /* Shouldn't this be 0? */
948 }
949
950 /* Committed, record Scsi_Cmd so we can find it later. */
951 cmd->handle = in_ptr;
952 hostdata->cmd_slots[in_ptr] = Cmnd;
953
954 isp_outw(in_ptr, host, MBOX4);
955 hostdata->req_in_ptr = in_ptr;
956
957 num_free = QLOGICISP_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr);
958 host->can_queue = host->host_busy + num_free;
959 host->sg_tablesize = QLOGICISP_MAX_SG(num_free);
960
961 LEAVE("isp1020_queuecommand");
962
963 return 0;
964 }
965
966
967 #define ASYNC_EVENT_INTERRUPT 0x01
968
969 void do_isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
970 {
971 unsigned long flags;
972
973 spin_lock_irqsave(&io_request_lock, flags);
974 isp1020_intr_handler(irq, dev_id, regs);
975 spin_unlock_irqrestore(&io_request_lock, flags);
976 }
977
978 void isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
979 {
980 Scsi_Cmnd *Cmnd;
981 struct Status_Entry *sts;
982 struct Scsi_Host *host = dev_id;
983 struct isp1020_hostdata *hostdata;
984 u_int in_ptr, out_ptr;
985 u_short status;
986
987 ENTER_INTR("isp1020_intr_handler");
988
989 hostdata = (struct isp1020_hostdata *) host->hostdata;
990
991 DEBUG_INTR(printk("qlogicisp : interrupt on line %d\n", irq));
992
993 if (!(isp_inw(host, PCI_INTF_STS) & 0x04)) {
994 /* spurious interrupts can happen legally */
995 DEBUG_INTR(printk("qlogicisp: got spurious interrupt\n"));
996 return;
997 }
998 in_ptr = isp_inw(host, MBOX5);
999 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1000
1001 if ((isp_inw(host, PCI_SEMAPHORE) & ASYNC_EVENT_INTERRUPT)) {
1002 status = isp_inw(host, MBOX0);
1003
1004 DEBUG_INTR(printk("qlogicisp : mbox completion status: %x\n",
1005 status));
1006
1007 switch (status) {
1008 case ASYNC_SCSI_BUS_RESET:
1009 case EXECUTION_TIMEOUT_RESET:
1010 hostdata->send_marker = 1;
1011 break;
1012 case INVALID_COMMAND:
1013 case HOST_INTERFACE_ERROR:
1014 case COMMAND_ERROR:
1015 case COMMAND_PARAM_ERROR:
1016 printk("qlogicisp : bad mailbox return status\n");
1017 break;
1018 }
1019 isp_outw(0x0, host, PCI_SEMAPHORE);
1020 }
1021 out_ptr = hostdata->res_out_ptr;
1022
1023 DEBUG_INTR(printk("qlogicisp : response queue update\n"));
1024 DEBUG_INTR(printk("qlogicisp : response queue depth %d\n",
1025 QUEUE_DEPTH(in_ptr, out_ptr, RES_QUEUE_LEN)));
1026
1027 while (out_ptr != in_ptr) {
1028 u_int cmd_slot;
1029
1030 sts = (struct Status_Entry *) &hostdata->res_cpu[out_ptr];
1031 out_ptr = (out_ptr + 1) & RES_QUEUE_LEN;
1032
1033 cmd_slot = sts->handle;
1034 Cmnd = hostdata->cmd_slots[cmd_slot];
1035 hostdata->cmd_slots[cmd_slot] = NULL;
1036
1037 TRACE("done", out_ptr, Cmnd);
1038
1039 if (le16_to_cpu(sts->completion_status) == CS_RESET_OCCURRED
1040 || le16_to_cpu(sts->completion_status) == CS_ABORTED
1041 || (le16_to_cpu(sts->status_flags) & STF_BUS_RESET))
1042 hostdata->send_marker = 1;
1043
1044 if (le16_to_cpu(sts->state_flags) & SF_GOT_SENSE)
1045 memcpy(Cmnd->sense_buffer, sts->req_sense_data,
1046 sizeof(Cmnd->sense_buffer));
1047
1048 DEBUG_INTR(isp1020_print_status_entry(sts));
1049
1050 if (sts->hdr.entry_type == ENTRY_STATUS)
1051 Cmnd->result = isp1020_return_status(sts);
1052 else
1053 Cmnd->result = DID_ERROR << 16;
1054
1055 if (Cmnd->use_sg)
1056 pci_unmap_sg(hostdata->pci_dev,
1057 (struct scatterlist *)Cmnd->buffer,
1058 Cmnd->use_sg,
1059 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
1060 else if (Cmnd->request_bufflen)
1061 pci_unmap_single(hostdata->pci_dev,
1062 #ifdef CONFIG_QL_ISP_A64
1063 (dma_addr_t)((long)Cmnd->SCp.ptr),
1064 #else
1065 (u32)((long)Cmnd->SCp.ptr),
1066 #endif
1067 Cmnd->request_bufflen,
1068 scsi_to_pci_dma_dir(Cmnd->sc_data_direction));
1069
1070 isp_outw(out_ptr, host, MBOX5);
1071 (*Cmnd->scsi_done)(Cmnd);
1072 }
1073 hostdata->res_out_ptr = out_ptr;
1074
1075 LEAVE_INTR("isp1020_intr_handler");
1076 }
1077
1078
1079 static int isp1020_return_status(struct Status_Entry *sts)
1080 {
1081 int host_status = DID_ERROR;
1082 #if DEBUG_ISP1020_INTR
1083 static char *reason[] = {
1084 "DID_OK",
1085 "DID_NO_CONNECT",
1086 "DID_BUS_BUSY",
1087 "DID_TIME_OUT",
1088 "DID_BAD_TARGET",
1089 "DID_ABORT",
1090 "DID_PARITY",
1091 "DID_ERROR",
1092 "DID_RESET",
1093 "DID_BAD_INTR"
1094 };
1095 #endif /* DEBUG_ISP1020_INTR */
1096
1097 ENTER("isp1020_return_status");
1098
1099 DEBUG(printk("qlogicisp : completion status = 0x%04x\n",
1100 le16_to_cpu(sts->completion_status)));
1101
1102 switch(le16_to_cpu(sts->completion_status)) {
1103 case CS_COMPLETE:
1104 host_status = DID_OK;
1105 break;
1106 case CS_INCOMPLETE:
1107 if (!(le16_to_cpu(sts->state_flags) & SF_GOT_BUS))
1108 host_status = DID_NO_CONNECT;
1109 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_TARGET))
1110 host_status = DID_BAD_TARGET;
1111 else if (!(le16_to_cpu(sts->state_flags) & SF_SENT_CDB))
1112 host_status = DID_ERROR;
1113 else if (!(le16_to_cpu(sts->state_flags) & SF_TRANSFERRED_DATA))
1114 host_status = DID_ERROR;
1115 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_STATUS))
1116 host_status = DID_ERROR;
1117 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_SENSE))
1118 host_status = DID_ERROR;
1119 break;
1120 case CS_DMA_ERROR:
1121 case CS_TRANSPORT_ERROR:
1122 host_status = DID_ERROR;
1123 break;
1124 case CS_RESET_OCCURRED:
1125 host_status = DID_RESET;
1126 break;
1127 case CS_ABORTED:
1128 host_status = DID_ABORT;
1129 break;
1130 case CS_TIMEOUT:
1131 host_status = DID_TIME_OUT;
1132 break;
1133 case CS_DATA_OVERRUN:
1134 case CS_COMMAND_OVERRUN:
1135 case CS_STATUS_OVERRUN:
1136 case CS_BAD_MESSAGE:
1137 case CS_NO_MESSAGE_OUT:
1138 case CS_EXT_ID_FAILED:
1139 case CS_IDE_MSG_FAILED:
1140 case CS_ABORT_MSG_FAILED:
1141 case CS_NOP_MSG_FAILED:
1142 case CS_PARITY_ERROR_MSG_FAILED:
1143 case CS_DEVICE_RESET_MSG_FAILED:
1144 case CS_ID_MSG_FAILED:
1145 case CS_UNEXP_BUS_FREE:
1146 host_status = DID_ERROR;
1147 break;
1148 case CS_DATA_UNDERRUN:
1149 host_status = DID_OK;
1150 break;
1151 default:
1152 printk("qlogicisp : unknown completion status 0x%04x\n",
1153 le16_to_cpu(sts->completion_status));
1154 host_status = DID_ERROR;
1155 break;
1156 }
1157
1158 DEBUG_INTR(printk("qlogicisp : host status (%s) scsi status %x\n",
1159 reason[host_status], le16_to_cpu(sts->scsi_status)));
1160
1161 LEAVE("isp1020_return_status");
1162
1163 return (le16_to_cpu(sts->scsi_status) & STATUS_MASK) | (host_status << 16);
1164 }
1165
1166
1167 int isp1020_abort(Scsi_Cmnd *Cmnd)
1168 {
1169 u_short param[6];
1170 struct Scsi_Host *host;
1171 struct isp1020_hostdata *hostdata;
1172 int return_status = SCSI_ABORT_SUCCESS;
1173 u_int cmd_cookie;
1174 int i;
1175
1176 ENTER("isp1020_abort");
1177
1178 host = Cmnd->host;
1179 hostdata = (struct isp1020_hostdata *) host->hostdata;
1180
1181 for (i = 0; i < QLOGICISP_REQ_QUEUE_LEN + 1; i++)
1182 if (hostdata->cmd_slots[i] == Cmnd)
1183 break;
1184 cmd_cookie = i;
1185
1186 isp1020_disable_irqs(host);
1187
1188 param[0] = MBOX_ABORT;
1189 param[1] = (((u_short) Cmnd->target) << 8) | Cmnd->lun;
1190 param[2] = cmd_cookie >> 16;
1191 param[3] = cmd_cookie & 0xffff;
1192
1193 isp1020_mbox_command(host, param);
1194
1195 if (param[0] != MBOX_COMMAND_COMPLETE) {
1196 printk("qlogicisp : scsi abort failure: %x\n", param[0]);
1197 return_status = SCSI_ABORT_ERROR;
1198 }
1199
1200 isp1020_enable_irqs(host);
1201
1202 LEAVE("isp1020_abort");
1203
1204 return return_status;
1205 }
1206
1207
1208 int isp1020_reset(Scsi_Cmnd *Cmnd, unsigned int reset_flags)
1209 {
1210 u_short param[6];
1211 struct Scsi_Host *host;
1212 struct isp1020_hostdata *hostdata;
1213 int return_status = SCSI_RESET_SUCCESS;
1214
1215 ENTER("isp1020_reset");
1216
1217 host = Cmnd->host;
1218 hostdata = (struct isp1020_hostdata *) host->hostdata;
1219
1220 param[0] = MBOX_BUS_RESET;
1221 param[1] = hostdata->host_param.bus_reset_delay;
1222
1223 isp1020_disable_irqs(host);
1224
1225 isp1020_mbox_command(host, param);
1226
1227 if (param[0] != MBOX_COMMAND_COMPLETE) {
1228 printk("qlogicisp : scsi bus reset failure: %x\n", param[0]);
1229 return_status = SCSI_RESET_ERROR;
1230 }
1231
1232 isp1020_enable_irqs(host);
1233
1234 LEAVE("isp1020_reset");
1235
1236 return return_status;;
1237 }
1238
1239
1240 int isp1020_biosparam(Disk *disk, kdev_t n, int ip[])
1241 {
1242 int size = disk->capacity;
1243
1244 ENTER("isp1020_biosparam");
1245
1246 ip[0] = 64;
1247 ip[1] = 32;
1248 ip[2] = size >> 11;
1249 if (ip[2] > 1024) {
1250 ip[0] = 255;
1251 ip[1] = 63;
1252 ip[2] = size / (ip[0] * ip[1]);
1253 #if 0
1254 if (ip[2] > 1023)
1255 ip[2] = 1023;
1256 #endif
1257 }
1258
1259 LEAVE("isp1020_biosparam");
1260
1261 return 0;
1262 }
1263
1264
1265 static int isp1020_reset_hardware(struct Scsi_Host *host)
1266 {
1267 u_short param[6];
1268 int loop_count;
1269
1270 ENTER("isp1020_reset_hardware");
1271
1272 isp_outw(ISP_RESET, host, PCI_INTF_CTL);
1273 udelay(100);
1274 isp_outw(HCCR_RESET, host, HOST_HCCR);
1275 udelay(100);
1276 isp_outw(HCCR_RELEASE, host, HOST_HCCR);
1277 isp_outw(HCCR_BIOS_DISABLE, host, HOST_HCCR);
1278
1279 loop_count = DEFAULT_LOOP_COUNT;
1280 while (--loop_count && isp_inw(host, HOST_HCCR) == RISC_BUSY)
1281 barrier();
1282 if (!loop_count)
1283 printk("qlogicisp: reset_hardware loop timeout\n");
1284
1285 isp_outw(0, host, ISP_CFG1);
1286
1287 #if DEBUG_ISP1020
1288 printk("qlogicisp : mbox 0 0x%04x \n", isp_inw(host, MBOX0));
1289 printk("qlogicisp : mbox 1 0x%04x \n", isp_inw(host, MBOX1));
1290 printk("qlogicisp : mbox 2 0x%04x \n", isp_inw(host, MBOX2));
1291 printk("qlogicisp : mbox 3 0x%04x \n", isp_inw(host, MBOX3));
1292 printk("qlogicisp : mbox 4 0x%04x \n", isp_inw(host, MBOX4));
1293 printk("qlogicisp : mbox 5 0x%04x \n", isp_inw(host, MBOX5));
1294 #endif /* DEBUG_ISP1020 */
1295
1296 param[0] = MBOX_NO_OP;
1297 isp1020_mbox_command(host, param);
1298 if (param[0] != MBOX_COMMAND_COMPLETE) {
1299 printk("qlogicisp : NOP test failed\n");
1300 return 1;
1301 }
1302
1303 DEBUG(printk("qlogicisp : loading risc ram\n"));
1304
1305 #if RELOAD_FIRMWARE
1306 for (loop_count = 0; loop_count < risc_code_length01; loop_count++) {
1307 param[0] = MBOX_WRITE_RAM_WORD;
1308 param[1] = risc_code_addr01 + loop_count;
1309 param[2] = risc_code01[loop_count];
1310 isp1020_mbox_command(host, param);
1311 if (param[0] != MBOX_COMMAND_COMPLETE) {
1312 printk("qlogicisp : firmware load failure at %d\n",
1313 loop_count);
1314 return 1;
1315 }
1316 }
1317 #endif /* RELOAD_FIRMWARE */
1318
1319 DEBUG(printk("qlogicisp : verifying checksum\n"));
1320
1321 param[0] = MBOX_VERIFY_CHECKSUM;
1322 param[1] = risc_code_addr01;
1323
1324 isp1020_mbox_command(host, param);
1325
1326 if (param[0] != MBOX_COMMAND_COMPLETE) {
1327 printk("qlogicisp : ram checksum failure\n");
1328 return 1;
1329 }
1330
1331 DEBUG(printk("qlogicisp : executing firmware\n"));
1332
1333 param[0] = MBOX_EXEC_FIRMWARE;
1334 param[1] = risc_code_addr01;
1335
1336 isp1020_mbox_command(host, param);
1337
1338 param[0] = MBOX_ABOUT_FIRMWARE;
1339
1340 isp1020_mbox_command(host, param);
1341
1342 if (param[0] != MBOX_COMMAND_COMPLETE) {
1343 printk("qlogicisp : about firmware failure\n");
1344 return 1;
1345 }
1346
1347 DEBUG(printk("qlogicisp : firmware major revision %d\n", param[1]));
1348 DEBUG(printk("qlogicisp : firmware minor revision %d\n", param[2]));
1349
1350 LEAVE("isp1020_reset_hardware");
1351
1352 return 0;
1353 }
1354
1355
1356 static int isp1020_init(struct Scsi_Host *sh)
1357 {
1358 u_long io_base, mem_base, io_flags, mem_flags;
1359 struct isp1020_hostdata *hostdata;
1360 u_char revision;
1361 u_int irq;
1362 u_short command;
1363 struct pci_dev *pdev;
1364
1365 ENTER("isp1020_init");
1366
1367 hostdata = (struct isp1020_hostdata *) sh->hostdata;
1368 pdev = hostdata->pci_dev;
1369
1370 if (pci_read_config_word(pdev, PCI_COMMAND, &command)
1371 || pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision))
1372 {
1373 printk("qlogicisp : error reading PCI configuration\n");
1374 return 1;
1375 }
1376
1377 io_base = pci_resource_start(pdev, 0);
1378 mem_base = pci_resource_start(pdev, 1);
1379 io_flags = pci_resource_flags(pdev, 0);
1380 mem_flags = pci_resource_flags(pdev, 1);
1381 irq = pdev->irq;
1382
1383 if (pdev->vendor != PCI_VENDOR_ID_QLOGIC) {
1384 printk("qlogicisp : 0x%04x is not QLogic vendor ID\n",
1385 pdev->vendor);
1386 return 1;
1387 }
1388
1389 if (pdev->device != PCI_DEVICE_ID_QLOGIC_ISP1020) {
1390 printk("qlogicisp : 0x%04x does not match ISP1020 device id\n",
1391 pdev->device);
1392 return 1;
1393 }
1394
1395 #ifdef __alpha__
1396 /* Force ALPHA to use bus I/O and not bus MEM.
1397 This is to avoid having to use HAE_MEM registers,
1398 which is broken on some platforms and with SMP. */
1399 command &= ~PCI_COMMAND_MEMORY;
1400 #endif
1401
1402 if (!(command & PCI_COMMAND_MASTER)) {
1403 printk("qlogicisp : bus mastering is disabled\n");
1404 return 1;
1405 }
1406
1407 sh->io_port = io_base;
1408
1409 if (check_region(sh->io_port, 0xff)) {
1410 printk("qlogicisp : i/o region 0x%lx-0x%lx already "
1411 "in use\n",
1412 sh->io_port, sh->io_port + 0xff);
1413 return 1;
1414 }
1415
1416 request_region(sh->io_port, 0xff, "qlogicisp");
1417
1418 if ((command & PCI_COMMAND_MEMORY) &&
1419 ((mem_flags & 1) == 0)) {
1420 mem_base = (u_long) ioremap(mem_base, PAGE_SIZE);
1421 hostdata->memaddr = mem_base;
1422 } else {
1423 if (command & PCI_COMMAND_IO && (io_flags & 3) != 1)
1424 {
1425 printk("qlogicisp : i/o mapping is disabled\n");
1426 release_region(sh->io_port, 0xff);
1427 return 1;
1428 }
1429 hostdata->memaddr = 0; /* zero to signify no i/o mapping */
1430 mem_base = 0;
1431 }
1432
1433 if (revision != ISP1020_REV_ID)
1434 printk("qlogicisp : new isp1020 revision ID (%d)\n", revision);
1435
1436 if (isp_inw(sh, PCI_ID_LOW) != PCI_VENDOR_ID_QLOGIC
1437 || isp_inw(sh, PCI_ID_HIGH) != PCI_DEVICE_ID_QLOGIC_ISP1020)
1438 {
1439 printk("qlogicisp : can't decode %s address space 0x%lx\n",
1440 (io_base ? "I/O" : "MEM"),
1441 (io_base ? io_base : mem_base));
1442 iounmap((void *)hostdata->memaddr);
1443 release_region(sh->io_port, 0xff);
1444 return 1;
1445 }
1446
1447 hostdata->revision = revision;
1448
1449 sh->irq = irq;
1450 sh->max_id = MAX_TARGETS;
1451 sh->max_lun = MAX_LUNS;
1452
1453 hostdata->res_cpu = pci_alloc_consistent(hostdata->pci_dev,
1454 QSIZE(RES_QUEUE_LEN),
1455 &hostdata->res_dma);
1456 if (hostdata->res_cpu == NULL) {
1457 printk("qlogicisp : can't allocate response queue\n");
1458 return 1;
1459 }
1460
1461 hostdata->req_cpu = pci_alloc_consistent(hostdata->pci_dev,
1462 QSIZE(QLOGICISP_REQ_QUEUE_LEN),
1463 &hostdata->req_dma);
1464 if (hostdata->req_cpu == NULL) {
1465 pci_free_consistent(hostdata->pci_dev,
1466 QSIZE(RES_QUEUE_LEN),
1467 hostdata->res_cpu,
1468 hostdata->res_dma);
1469 printk("qlogicisp : can't allocate request queue\n");
1470 return 1;
1471 }
1472
1473 LEAVE("isp1020_init");
1474
1475 return 0;
1476 }
1477
1478
1479 #if USE_NVRAM_DEFAULTS
1480
1481 static int isp1020_get_defaults(struct Scsi_Host *host)
1482 {
1483 int i;
1484 u_short value;
1485 struct isp1020_hostdata *hostdata =
1486 (struct isp1020_hostdata *) host->hostdata;
1487
1488 ENTER("isp1020_get_defaults");
1489
1490 if (!isp1020_verify_nvram(host)) {
1491 printk("qlogicisp : nvram checksum failure\n");
1492 printk("qlogicisp : attempting to use default parameters\n");
1493 return isp1020_set_defaults(host);
1494 }
1495
1496 value = isp1020_read_nvram_word(host, 2);
1497 hostdata->host_param.fifo_threshold = (value >> 8) & 0x03;
1498 hostdata->host_param.host_adapter_enable = (value >> 11) & 0x01;
1499 hostdata->host_param.initiator_scsi_id = (value >> 12) & 0x0f;
1500
1501 value = isp1020_read_nvram_word(host, 3);
1502 hostdata->host_param.bus_reset_delay = value & 0xff;
1503 hostdata->host_param.retry_count = value >> 8;
1504
1505 value = isp1020_read_nvram_word(host, 4);
1506 hostdata->host_param.retry_delay = value & 0xff;
1507 hostdata->host_param.async_data_setup_time = (value >> 8) & 0x0f;
1508 hostdata->host_param.req_ack_active_negation = (value >> 12) & 0x01;
1509 hostdata->host_param.data_line_active_negation = (value >> 13) & 0x01;
1510 hostdata->host_param.data_dma_burst_enable = (value >> 14) & 0x01;
1511 hostdata->host_param.command_dma_burst_enable = (value >> 15);
1512
1513 value = isp1020_read_nvram_word(host, 5);
1514 hostdata->host_param.tag_aging = value & 0xff;
1515
1516 value = isp1020_read_nvram_word(host, 6);
1517 hostdata->host_param.selection_timeout = value & 0xffff;
1518
1519 value = isp1020_read_nvram_word(host, 7);
1520 hostdata->host_param.max_queue_depth = value & 0xffff;
1521
1522 #if DEBUG_ISP1020_SETUP
1523 printk("qlogicisp : fifo threshold=%d\n",
1524 hostdata->host_param.fifo_threshold);
1525 printk("qlogicisp : initiator scsi id=%d\n",
1526 hostdata->host_param.initiator_scsi_id);
1527 printk("qlogicisp : bus reset delay=%d\n",
1528 hostdata->host_param.bus_reset_delay);
1529 printk("qlogicisp : retry count=%d\n",
1530 hostdata->host_param.retry_count);
1531 printk("qlogicisp : retry delay=%d\n",
1532 hostdata->host_param.retry_delay);
1533 printk("qlogicisp : async data setup time=%d\n",
1534 hostdata->host_param.async_data_setup_time);
1535 printk("qlogicisp : req/ack active negation=%d\n",
1536 hostdata->host_param.req_ack_active_negation);
1537 printk("qlogicisp : data line active negation=%d\n",
1538 hostdata->host_param.data_line_active_negation);
1539 printk("qlogicisp : data DMA burst enable=%d\n",
1540 hostdata->host_param.data_dma_burst_enable);
1541 printk("qlogicisp : command DMA burst enable=%d\n",
1542 hostdata->host_param.command_dma_burst_enable);
1543 printk("qlogicisp : tag age limit=%d\n",
1544 hostdata->host_param.tag_aging);
1545 printk("qlogicisp : selection timeout limit=%d\n",
1546 hostdata->host_param.selection_timeout);
1547 printk("qlogicisp : max queue depth=%d\n",
1548 hostdata->host_param.max_queue_depth);
1549 #endif /* DEBUG_ISP1020_SETUP */
1550
1551 for (i = 0; i < MAX_TARGETS; i++) {
1552
1553 value = isp1020_read_nvram_word(host, 14 + i * 3);
1554 hostdata->dev_param[i].device_flags = value & 0xff;
1555 hostdata->dev_param[i].execution_throttle = value >> 8;
1556
1557 value = isp1020_read_nvram_word(host, 15 + i * 3);
1558 hostdata->dev_param[i].synchronous_period = value & 0xff;
1559 hostdata->dev_param[i].synchronous_offset = (value >> 8) & 0x0f;
1560 hostdata->dev_param[i].device_enable = (value >> 12) & 0x01;
1561
1562 #if DEBUG_ISP1020_SETUP
1563 printk("qlogicisp : target 0x%02x\n", i);
1564 printk("qlogicisp : device flags=0x%02x\n",
1565 hostdata->dev_param[i].device_flags);
1566 printk("qlogicisp : execution throttle=%d\n",
1567 hostdata->dev_param[i].execution_throttle);
1568 printk("qlogicisp : synchronous period=%d\n",
1569 hostdata->dev_param[i].synchronous_period);
1570 printk("qlogicisp : synchronous offset=%d\n",
1571 hostdata->dev_param[i].synchronous_offset);
1572 printk("qlogicisp : device enable=%d\n",
1573 hostdata->dev_param[i].device_enable);
1574 #endif /* DEBUG_ISP1020_SETUP */
1575 }
1576
1577 LEAVE("isp1020_get_defaults");
1578
1579 return 0;
1580 }
1581
1582
1583 #define ISP1020_NVRAM_LEN 0x40
1584 #define ISP1020_NVRAM_SIG1 0x5349
1585 #define ISP1020_NVRAM_SIG2 0x2050
1586
1587 static int isp1020_verify_nvram(struct Scsi_Host *host)
1588 {
1589 int i;
1590 u_short value;
1591 u_char checksum = 0;
1592
1593 for (i = 0; i < ISP1020_NVRAM_LEN; i++) {
1594 value = isp1020_read_nvram_word(host, i);
1595
1596 switch (i) {
1597 case 0:
1598 if (value != ISP1020_NVRAM_SIG1) return 0;
1599 break;
1600 case 1:
1601 if (value != ISP1020_NVRAM_SIG2) return 0;
1602 break;
1603 case 2:
1604 if ((value & 0xff) != 0x02) return 0;
1605 break;
1606 }
1607 checksum += value & 0xff;
1608 checksum += value >> 8;
1609 }
1610
1611 return (checksum == 0);
1612 }
1613
1614 #define NVRAM_DELAY() udelay(2) /* 2 microsecond delay */
1615
1616
1617 u_short isp1020_read_nvram_word(struct Scsi_Host *host, u_short byte)
1618 {
1619 int i;
1620 u_short value, output, input;
1621
1622 byte &= 0x3f; byte |= 0x0180;
1623
1624 for (i = 8; i >= 0; i--) {
1625 output = ((byte >> i) & 0x1) ? 0x4 : 0x0;
1626 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1627 isp_outw(output | 0x3, host, PCI_NVRAM); NVRAM_DELAY();
1628 isp_outw(output | 0x2, host, PCI_NVRAM); NVRAM_DELAY();
1629 }
1630
1631 for (i = 0xf, value = 0; i >= 0; i--) {
1632 value <<= 1;
1633 isp_outw(0x3, host, PCI_NVRAM); NVRAM_DELAY();
1634 input = isp_inw(host, PCI_NVRAM); NVRAM_DELAY();
1635 isp_outw(0x2, host, PCI_NVRAM); NVRAM_DELAY();
1636 if (input & 0x8) value |= 1;
1637 }
1638
1639 isp_outw(0x0, host, PCI_NVRAM); NVRAM_DELAY();
1640
1641 return value;
1642 }
1643
1644 #endif /* USE_NVRAM_DEFAULTS */
1645
1646
1647 static int isp1020_set_defaults(struct Scsi_Host *host)
1648 {
1649 struct isp1020_hostdata *hostdata =
1650 (struct isp1020_hostdata *) host->hostdata;
1651 int i;
1652
1653 ENTER("isp1020_set_defaults");
1654
1655 hostdata->host_param.fifo_threshold = 2;
1656 hostdata->host_param.host_adapter_enable = 1;
1657 hostdata->host_param.initiator_scsi_id = 7;
1658 hostdata->host_param.bus_reset_delay = 3;
1659 hostdata->host_param.retry_count = 0;
1660 hostdata->host_param.retry_delay = 1;
1661 hostdata->host_param.async_data_setup_time = 6;
1662 hostdata->host_param.req_ack_active_negation = 1;
1663 hostdata->host_param.data_line_active_negation = 1;
1664 hostdata->host_param.data_dma_burst_enable = 1;
1665 hostdata->host_param.command_dma_burst_enable = 1;
1666 hostdata->host_param.tag_aging = 8;
1667 hostdata->host_param.selection_timeout = 250;
1668 hostdata->host_param.max_queue_depth = 256;
1669
1670 for (i = 0; i < MAX_TARGETS; i++) {
1671 hostdata->dev_param[i].device_flags = 0xfd;
1672 hostdata->dev_param[i].execution_throttle = 16;
1673 hostdata->dev_param[i].synchronous_period = 25;
1674 hostdata->dev_param[i].synchronous_offset = 12;
1675 hostdata->dev_param[i].device_enable = 1;
1676 }
1677
1678 LEAVE("isp1020_set_defaults");
1679
1680 return 0;
1681 }
1682
1683
1684 static int isp1020_load_parameters(struct Scsi_Host *host)
1685 {
1686 int i, k;
1687 #ifdef CONFIG_QL_ISP_A64
1688 u_long queue_addr;
1689 u_short param[8];
1690 #else
1691 u_int queue_addr;
1692 u_short param[6];
1693 #endif
1694 u_short isp_cfg1, hwrev;
1695 unsigned long flags;
1696 struct isp1020_hostdata *hostdata =
1697 (struct isp1020_hostdata *) host->hostdata;
1698
1699 ENTER("isp1020_load_parameters");
1700
1701 save_flags(flags);
1702 cli();
1703
1704 hwrev = isp_inw(host, ISP_CFG0) & ISP_CFG0_HWMSK;
1705 isp_cfg1 = ISP_CFG1_F64 | ISP_CFG1_BENAB;
1706 if (hwrev == ISP_CFG0_1040A) {
1707 /* Busted fifo, says mjacob. */
1708 isp_cfg1 &= ISP_CFG1_BENAB;
1709 }
1710
1711 isp_outw(isp_inw(host, ISP_CFG1) | isp_cfg1, host, ISP_CFG1);
1712 isp_outw(isp_inw(host, CDMA_CONF) | DMA_CONF_BENAB, host, CDMA_CONF);
1713 isp_outw(isp_inw(host, DDMA_CONF) | DMA_CONF_BENAB, host, DDMA_CONF);
1714
1715 param[0] = MBOX_SET_INIT_SCSI_ID;
1716 param[1] = hostdata->host_param.initiator_scsi_id;
1717
1718 isp1020_mbox_command(host, param);
1719
1720 if (param[0] != MBOX_COMMAND_COMPLETE) {
1721 restore_flags(flags);
1722 printk("qlogicisp : set initiator id failure\n");
1723 return 1;
1724 }
1725
1726 param[0] = MBOX_SET_RETRY_COUNT;
1727 param[1] = hostdata->host_param.retry_count;
1728 param[2] = hostdata->host_param.retry_delay;
1729
1730 isp1020_mbox_command(host, param);
1731
1732 if (param[0] != MBOX_COMMAND_COMPLETE) {
1733 restore_flags(flags);
1734 printk("qlogicisp : set retry count failure\n");
1735 return 1;
1736 }
1737
1738 param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME;
1739 param[1] = hostdata->host_param.async_data_setup_time;
1740
1741 isp1020_mbox_command(host, param);
1742
1743 if (param[0] != MBOX_COMMAND_COMPLETE) {
1744 restore_flags(flags);
1745 printk("qlogicisp : async data setup time failure\n");
1746 return 1;
1747 }
1748
1749 param[0] = MBOX_SET_ACTIVE_NEG_STATE;
1750 param[1] = (hostdata->host_param.req_ack_active_negation << 4)
1751 | (hostdata->host_param.data_line_active_negation << 5);
1752
1753 isp1020_mbox_command(host, param);
1754
1755 if (param[0] != MBOX_COMMAND_COMPLETE) {
1756 restore_flags(flags);
1757 printk("qlogicisp : set active negation state failure\n");
1758 return 1;
1759 }
1760
1761 param[0] = MBOX_SET_PCI_CONTROL_PARAMS;
1762 param[1] = hostdata->host_param.data_dma_burst_enable << 1;
1763 param[2] = hostdata->host_param.command_dma_burst_enable << 1;
1764
1765 isp1020_mbox_command(host, param);
1766
1767 if (param[0] != MBOX_COMMAND_COMPLETE) {
1768 restore_flags(flags);
1769 printk("qlogicisp : set pci control parameter failure\n");
1770 return 1;
1771 }
1772
1773 param[0] = MBOX_SET_TAG_AGE_LIMIT;
1774 param[1] = hostdata->host_param.tag_aging;
1775
1776 isp1020_mbox_command(host, param);
1777
1778 if (param[0] != MBOX_COMMAND_COMPLETE) {
1779 restore_flags(flags);
1780 printk("qlogicisp : set tag age limit failure\n");
1781 return 1;
1782 }
1783
1784 param[0] = MBOX_SET_SELECT_TIMEOUT;
1785 param[1] = hostdata->host_param.selection_timeout;
1786
1787 isp1020_mbox_command(host, param);
1788
1789 if (param[0] != MBOX_COMMAND_COMPLETE) {
1790 restore_flags(flags);
1791 printk("qlogicisp : set selection timeout failure\n");
1792 return 1;
1793 }
1794
1795 for (i = 0; i < MAX_TARGETS; i++) {
1796
1797 if (!hostdata->dev_param[i].device_enable)
1798 continue;
1799
1800 param[0] = MBOX_SET_TARGET_PARAMS;
1801 param[1] = i << 8;
1802 param[2] = hostdata->dev_param[i].device_flags << 8;
1803 param[3] = (hostdata->dev_param[i].synchronous_offset << 8)
1804 | hostdata->dev_param[i].synchronous_period;
1805
1806 isp1020_mbox_command(host, param);
1807
1808 if (param[0] != MBOX_COMMAND_COMPLETE) {
1809 restore_flags(flags);
1810 printk("qlogicisp : set target parameter failure\n");
1811 return 1;
1812 }
1813
1814 for (k = 0; k < MAX_LUNS; k++) {
1815
1816 param[0] = MBOX_SET_DEV_QUEUE_PARAMS;
1817 param[1] = (i << 8) | k;
1818 param[2] = hostdata->host_param.max_queue_depth;
1819 param[3] = hostdata->dev_param[i].execution_throttle;
1820
1821 isp1020_mbox_command(host, param);
1822
1823 if (param[0] != MBOX_COMMAND_COMPLETE) {
1824 restore_flags(flags);
1825 printk("qlogicisp : set device queue "
1826 "parameter failure\n");
1827 return 1;
1828 }
1829 }
1830 }
1831
1832 queue_addr = hostdata->res_dma;
1833 #ifdef CONFIG_QL_ISP_A64
1834 param[0] = MBOX_CMD_INIT_RESPONSE_QUEUE_64;
1835 #else
1836 param[0] = MBOX_INIT_RES_QUEUE;
1837 #endif
1838 param[1] = RES_QUEUE_LEN + 1;
1839 param[2] = (u_short) (queue_addr >> 16);
1840 param[3] = (u_short) (queue_addr & 0xffff);
1841 param[4] = 0;
1842 param[5] = 0;
1843 #ifdef CONFIG_QL_ISP_A64
1844 param[6] = (u_short) (queue_addr >> 48);
1845 param[7] = (u_short) (queue_addr >> 32);
1846 #endif
1847
1848 isp1020_mbox_command(host, param);
1849
1850 if (param[0] != MBOX_COMMAND_COMPLETE) {
1851 restore_flags(flags);
1852 printk("qlogicisp : set response queue failure\n");
1853 return 1;
1854 }
1855
1856 queue_addr = hostdata->req_dma;
1857 #ifdef CONFIG_QL_ISP_A64
1858 param[0] = MBOX_CMD_INIT_REQUEST_QUEUE_64;
1859 #else
1860 param[0] = MBOX_INIT_REQ_QUEUE;
1861 #endif
1862 param[1] = QLOGICISP_REQ_QUEUE_LEN + 1;
1863 param[2] = (u_short) (queue_addr >> 16);
1864 param[3] = (u_short) (queue_addr & 0xffff);
1865 param[4] = 0;
1866
1867 #ifdef CONFIG_QL_ISP_A64
1868 param[5] = 0;
1869 param[6] = (u_short) (queue_addr >> 48);
1870 param[7] = (u_short) (queue_addr >> 32);
1871 #endif
1872
1873 isp1020_mbox_command(host, param);
1874
1875 if (param[0] != MBOX_COMMAND_COMPLETE) {
1876 restore_flags(flags);
1877 printk("qlogicisp : set request queue failure\n");
1878 return 1;
1879 }
1880
1881 restore_flags(flags);
1882
1883 LEAVE("isp1020_load_parameters");
1884
1885 return 0;
1886 }
1887
1888
1889 /*
1890 * currently, this is only called during initialization or abort/reset,
1891 * at which times interrupts are disabled, so polling is OK, I guess...
1892 */
1893 static int isp1020_mbox_command(struct Scsi_Host *host, u_short param[])
1894 {
1895 int loop_count;
1896
1897 if (mbox_param[param[0]] == 0)
1898 return 1;
1899
1900 loop_count = DEFAULT_LOOP_COUNT;
1901 while (--loop_count && isp_inw(host, HOST_HCCR) & 0x0080)
1902 barrier();
1903 if (!loop_count)
1904 printk("qlogicisp: mbox_command loop timeout #1\n");
1905
1906 switch(mbox_param[param[0]] >> 4) {
1907 case 8: isp_outw(param[7], host, MBOX7);
1908 case 7: isp_outw(param[6], host, MBOX6);
1909 case 6: isp_outw(param[5], host, MBOX5);
1910 case 5: isp_outw(param[4], host, MBOX4);
1911 case 4: isp_outw(param[3], host, MBOX3);
1912 case 3: isp_outw(param[2], host, MBOX2);
1913 case 2: isp_outw(param[1], host, MBOX1);
1914 case 1: isp_outw(param[0], host, MBOX0);
1915 }
1916
1917 isp_outw(0x0, host, PCI_SEMAPHORE);
1918 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1919 isp_outw(HCCR_SET_HOST_INTR, host, HOST_HCCR);
1920
1921 loop_count = DEFAULT_LOOP_COUNT;
1922 while (--loop_count && !(isp_inw(host, PCI_INTF_STS) & 0x04))
1923 barrier();
1924 if (!loop_count)
1925 printk("qlogicisp: mbox_command loop timeout #2\n");
1926
1927 loop_count = DEFAULT_LOOP_COUNT;
1928 while (--loop_count && isp_inw(host, MBOX0) == 0x04)
1929 barrier();
1930 if (!loop_count)
1931 printk("qlogicisp: mbox_command loop timeout #3\n");
1932
1933 switch(mbox_param[param[0]] & 0xf) {
1934 case 8: param[7] = isp_inw(host, MBOX7);
1935 case 7: param[6] = isp_inw(host, MBOX6);
1936 case 6: param[5] = isp_inw(host, MBOX5);
1937 case 5: param[4] = isp_inw(host, MBOX4);
1938 case 4: param[3] = isp_inw(host, MBOX3);
1939 case 3: param[2] = isp_inw(host, MBOX2);
1940 case 2: param[1] = isp_inw(host, MBOX1);
1941 case 1: param[0] = isp_inw(host, MBOX0);
1942 }
1943
1944 isp_outw(0x0, host, PCI_SEMAPHORE);
1945 isp_outw(HCCR_CLEAR_RISC_INTR, host, HOST_HCCR);
1946
1947 return 0;
1948 }
1949
1950
1951 #if DEBUG_ISP1020_INTR
1952
1953 void isp1020_print_status_entry(struct Status_Entry *status)
1954 {
1955 int i;
1956
1957 printk("qlogicisp : entry count = 0x%02x, type = 0x%02x, flags = 0x%02x\n",
1958 status->hdr.entry_cnt, status->hdr.entry_type, status->hdr.flags);
1959 printk("qlogicisp : scsi status = 0x%04x, completion status = 0x%04x\n",
1960 le16_to_cpu(status->scsi_status), le16_to_cpu(status->completion_status));
1961 printk("qlogicisp : state flags = 0x%04x, status flags = 0x%04x\n",
1962 le16_to_cpu(status->state_flags), le16_to_cpu(status->status_flags));
1963 printk("qlogicisp : time = 0x%04x, request sense length = 0x%04x\n",
1964 le16_to_cpu(status->time), le16_to_cpu(status->req_sense_len));
1965 printk("qlogicisp : residual transfer length = 0x%08x\n",
1966 le32_to_cpu(status->residual));
1967
1968 for (i = 0; i < le16_to_cpu(status->req_sense_len); i++)
1969 printk("qlogicisp : sense data = 0x%02x\n", status->req_sense_data[i]);
1970 }
1971
1972 #endif /* DEBUG_ISP1020_INTR */
1973
1974
1975 #if DEBUG_ISP1020
1976
1977 void isp1020_print_scsi_cmd(Scsi_Cmnd *cmd)
1978 {
1979 int i;
1980
1981 printk("qlogicisp : target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n",
1982 cmd->target, cmd->lun, cmd->cmd_len);
1983 printk("qlogicisp : command = ");
1984 for (i = 0; i < cmd->cmd_len; i++)
1985 printk("0x%02x ", cmd->cmnd[i]);
1986 printk("\n");
1987 }
1988
1989 #endif /* DEBUG_ISP1020 */
1990
1991
1992 static Scsi_Host_Template driver_template = QLOGICISP;
1993
1994 #include "scsi_module.c"
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