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Ok. I didn't make 2.4.0 in 2000. Tough. I tried, but we had some
[davej-history.git] / drivers / scsi / mesh.c
blobf80a7c4972bd873810fb9ed1386fbcf7a148d7a7
1 /*
2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
3 * bus adaptor found on Power Macintosh computers.
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
5 * controller.
6 *
7 * Paul Mackerras, August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/types.h>
14 #include <linux/string.h>
15 #include <linux/malloc.h>
16 #include <linux/blk.h>
17 #include <linux/proc_fs.h>
18 #include <linux/stat.h>
19 #include <linux/tqueue.h>
20 #include <linux/interrupt.h>
21 #include <linux/reboot.h>
22 #include <linux/spinlock.h>
23 #include <asm/dbdma.h>
24 #include <asm/io.h>
25 #include <asm/pgtable.h>
26 #include <asm/prom.h>
27 #include <asm/system.h>
28 #include <asm/irq.h>
29 #include <asm/hydra.h>
30 #include <asm/processor.h>
31 #include <asm/feature.h>
32
33 #include "scsi.h"
34 #include "hosts.h"
35 #include "mesh.h"
36
37 /*
38 * To do:
39 * - handle aborts correctly
40 * - retry arbitration if lost (unless higher levels do this for us)
41 */
42
43 #define MESH_NEW_STYLE_EH
44
45 #if 1
46 #undef KERN_DEBUG
47 #define KERN_DEBUG KERN_WARNING
48 #endif
49
50 #if CONFIG_SCSI_MESH_SYNC_RATE == 0
51 int mesh_sync_period = 100;
52 int mesh_sync_offset = 0;
53 #else
54 int mesh_sync_period = 1000 / CONFIG_SCSI_MESH_SYNC_RATE; /* ns */
55 int mesh_sync_offset = 15;
56 #endif
57
58 int mesh_sync_targets = 0xff; /* targets to set synchronous (bitmap) */
59 int mesh_resel_targets = 0xff; /* targets that we let disconnect (bitmap) */
60 int mesh_debug_targets = 0; /* print debug for these targets */
61 unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
62
63 #define ALLOW_SYNC(tgt) ((mesh_sync_targets >> (tgt)) & 1)
64 #define ALLOW_RESEL(tgt) ((mesh_resel_targets >> (tgt)) & 1)
65 #define ALLOW_DEBUG(tgt) ((mesh_debug_targets >> (tgt)) & 1)
66 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->target))
67
68 #undef MESH_DBG
69 #define N_DBG_LOG 50
70 #define N_DBG_SLOG 20
71 #define NUM_DBG_EVENTS 13
72 #undef DBG_USE_TB /* bombs on 601 */
73
74 struct dbglog {
75 char *fmt;
76 u32 tb;
77 u8 phase;
78 u8 bs0;
79 u8 bs1;
80 u8 tgt;
81 int d;
82 };
83
84 enum mesh_phase {
85 idle,
86 arbitrating,
87 selecting,
88 commanding,
89 dataing,
90 statusing,
91 busfreeing,
92 disconnecting,
93 reselecting
94 };
95
96 enum msg_phase {
97 msg_none,
98 msg_out,
99 msg_out_xxx,
100 msg_out_last,
101 msg_in,
102 msg_in_bad,
103 };
104
105 enum sdtr_phase {
106 do_sdtr,
107 sdtr_sent,
108 sdtr_done
109 };
110
111 struct mesh_target {
112 enum sdtr_phase sdtr_state;
113 int sync_params;
114 int data_goes_out; /* guess as to data direction */
115 Scsi_Cmnd *current_req;
116 u32 saved_ptr;
117 int want_abort;
118 #ifdef MESH_DBG
119 int log_ix;
120 int n_log;
121 struct dbglog log[N_DBG_LOG];
122 #endif
123 };
124
125 struct mesh_state {
126 volatile struct mesh_regs *mesh;
127 int meshintr;
128 volatile struct dbdma_regs *dma;
129 int dmaintr;
130 struct Scsi_Host *host;
131 struct mesh_state *next;
132 Scsi_Cmnd *request_q;
133 Scsi_Cmnd *request_qtail;
134 enum mesh_phase phase; /* what we're currently trying to do */
135 enum msg_phase msgphase;
136 int conn_tgt; /* target we're connected to */
137 Scsi_Cmnd *current_req; /* req we're currently working on */
138 int data_ptr;
139 int dma_started;
140 int dma_count;
141 int stat;
142 int aborting;
143 int expect_reply;
144 int n_msgin;
145 u8 msgin[16];
146 int n_msgout;
147 int last_n_msgout;
148 u8 msgout[16];
149 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
150 int clk_freq;
151 struct mesh_target tgts[8];
152 void *dma_cmd_space;
153 struct device_node *ofnode;
154 #ifndef MESH_NEW_STYLE_EH
155 Scsi_Cmnd *completed_q;
156 Scsi_Cmnd *completed_qtail;
157 struct tq_struct tqueue;
158 #endif
159 #ifdef MESH_DBG
160 int log_ix;
161 int n_log;
162 struct dbglog log[N_DBG_SLOG];
163 #endif
164 };
165
166 #ifdef MESH_DBG
167
168 static void dlog(struct mesh_state *ms, char *fmt, int a);
169 static void dumplog(struct mesh_state *ms, int tgt);
170 static void dumpslog(struct mesh_state *ms);
171
172 #else
173 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
174 {}
175 static inline void dumplog(struct mesh_state *ms, int tgt)
176 {}
177 static inline void dumpslog(struct mesh_state *ms)
178 {}
179
180 #endif /* MESH_DBG */
181 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
182
183 static struct mesh_state *all_meshes;
184
185 static void mesh_init(struct mesh_state *);
186 static int mesh_notify_reboot(struct notifier_block *, unsigned long, void *);
187 static void mesh_dump_regs(struct mesh_state *);
188 static void mesh_start(struct mesh_state *);
189 static void mesh_start_cmd(struct mesh_state *, Scsi_Cmnd *);
190 #ifndef MESH_NEW_STYLE_EH
191 static void finish_cmds(void *);
192 #endif
193 static void add_sdtr_msg(struct mesh_state *);
194 static void set_sdtr(struct mesh_state *, int, int);
195 static void start_phase(struct mesh_state *);
196 static void get_msgin(struct mesh_state *);
197 static int msgin_length(struct mesh_state *);
198 static void cmd_complete(struct mesh_state *);
199 static void phase_mismatch(struct mesh_state *);
200 static void reselected(struct mesh_state *);
201 static void handle_reset(struct mesh_state *);
202 static void handle_error(struct mesh_state *);
203 static void handle_exception(struct mesh_state *);
204 static void mesh_interrupt(int, void *, struct pt_regs *);
205 static void do_mesh_interrupt(int, void *, struct pt_regs *);
206 static void handle_msgin(struct mesh_state *);
207 static void mesh_done(struct mesh_state *, int);
208 static void mesh_completed(struct mesh_state *, Scsi_Cmnd *);
209 static void set_dma_cmds(struct mesh_state *, Scsi_Cmnd *);
210 static void halt_dma(struct mesh_state *);
211 static int data_goes_out(Scsi_Cmnd *);
212 static void do_abort(struct mesh_state *ms);
213
214 static struct notifier_block mesh_notifier = {
215 mesh_notify_reboot,
216 NULL,
217 0
218 };
219
220 int
221 mesh_detect(Scsi_Host_Template *tp)
222 {
223 struct device_node *mesh;
224 int nmeshes, tgt, *cfp, minper;
225 struct mesh_state *ms, **prev_statep;
226 struct Scsi_Host *mesh_host;
227 void *dma_cmd_space;
228
229 if (_machine == _MACH_Pmac) {
230 use_active_neg = (find_devices("mac-io") ? 0 : SEQ_ACTIVE_NEG);
231 } else {
232 /* CHRP mac-io */
233 use_active_neg = SEQ_ACTIVE_NEG;
234 }
235
236 nmeshes = 0;
237 prev_statep = &all_meshes;
238 /*
239 * On powermacs, the MESH node has device_type "mesh".
240 * On chrp machines, its device_type is "scsi" with
241 * "chrp,mesh0" as its `compatible' property.
242 */
243 mesh = find_devices("mesh");
244 if (mesh == 0)
245 mesh = find_compatible_devices("scsi", "chrp,mesh0");
246 for (; mesh != 0; mesh = mesh->next) {
247 if (mesh->n_addrs != 2 || mesh->n_intrs != 2) {
248 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
249 " (got %d,%d)", mesh->n_addrs, mesh->n_intrs);
250 continue;
251 }
252 mesh_host = scsi_register(tp, sizeof(struct mesh_state));
253 if (mesh_host == 0) {
254 printk(KERN_ERR "mesh: couldn't register host");
255 continue;
256 }
257 mesh_host->unique_id = nmeshes;
258 #if !defined(MODULE)
259 note_scsi_host(mesh, mesh_host);
260 #endif
261
262 ms = (struct mesh_state *) mesh_host->hostdata;
263 if (ms == 0)
264 panic("no mesh state");
265 memset(ms, 0, sizeof(*ms));
266 ms->host = mesh_host;
267 ms->ofnode = mesh;
268 ms->mesh = (volatile struct mesh_regs *)
269 ioremap(mesh->addrs[0].address, 0x1000);
270 ms->dma = (volatile struct dbdma_regs *)
271 ioremap(mesh->addrs[1].address, 0x1000);
272 ms->meshintr = mesh->intrs[0].line;
273 ms->dmaintr = mesh->intrs[1].line;
274
275 /* Space for dma command list: +1 for stop command,
276 +1 to allow for aligning. */
277 dma_cmd_space = kmalloc((mesh_host->sg_tablesize + 2) *
278 sizeof(struct dbdma_cmd), GFP_KERNEL);
279 if (dma_cmd_space == 0)
280 panic("mesh: couldn't allocate dma command space");
281 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
282 memset(ms->dma_cmds, 0, (mesh_host->sg_tablesize + 1)
283 * sizeof(struct dbdma_cmd));
284 ms->dma_cmd_space = dma_cmd_space;
285
286 ms->current_req = 0;
287 for (tgt = 0; tgt < 8; ++tgt) {
288 ms->tgts[tgt].sdtr_state = do_sdtr;
289 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
290 ms->tgts[tgt].current_req = 0;
291 }
292 #ifndef MESH_NEW_STYLE_EH
293 ms->tqueue.routine = finish_cmds;
294 ms->tqueue.data = ms;
295 #endif
296 *prev_statep = ms;
297 prev_statep = &ms->next;
298
299 if ((cfp = (int *) get_property(mesh, "clock-frequency",
300 NULL))) {
301 ms->clk_freq = *cfp;
302 } else {
303 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
304 ms->clk_freq = 50000000;
305 }
306 /* The maximum sync rate is clock / 5; increase
307 mesh_sync_period if necessary. */
308 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
309 if (mesh_sync_period < minper)
310 mesh_sync_period = minper;
311
312 feature_set(mesh, FEATURE_MESH_enable);
313 mdelay(200);
314
315 mesh_init(ms);
316
317 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
318 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
319 }
320
321 ++nmeshes;
322 }
323
324 if ((_machine == _MACH_Pmac) && (nmeshes > 0))
325 register_reboot_notifier(&mesh_notifier);
326
327 return nmeshes;
328 }
329
330 int
331 mesh_release(struct Scsi_Host *host)
332 {
333 struct mesh_state *ms = (struct mesh_state *) host->hostdata;
334
335 if (ms == 0)
336 return 0;
337 if (ms->mesh)
338 iounmap((void *) ms->mesh);
339 if (ms->dma)
340 iounmap((void *) ms->dma);
341 kfree(ms->dma_cmd_space);
342 free_irq(ms->meshintr, ms);
343 feature_clear(ms->ofnode, FEATURE_MESH_enable);
344 return 0;
345 }
346
347 int
348 mesh_queue(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *))
349 {
350 unsigned long flags;
351 struct mesh_state *ms;
352
353 cmd->scsi_done = done;
354 cmd->host_scribble = NULL;
355
356 ms = (struct mesh_state *) cmd->host->hostdata;
357
358 save_flags(flags);
359 cli();
360 if (ms->request_q == NULL)
361 ms->request_q = cmd;
362 else
363 ms->request_qtail->host_scribble = (void *) cmd;
364 ms->request_qtail = cmd;
365
366 if (ms->phase == idle)
367 mesh_start(ms);
368
369 restore_flags(flags);
370 return 0;
371 }
372
373 int
374 mesh_abort(Scsi_Cmnd *cmd)
375 {
376 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
377
378 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
379 mesh_dump_regs(ms);
380 dumplog(ms, cmd->target);
381 dumpslog(ms);
382 return SCSI_ABORT_SNOOZE;
383 }
384
385 static void
386 mesh_dump_regs(struct mesh_state *ms)
387 {
388 volatile struct mesh_regs *mr = ms->mesh;
389 volatile struct dbdma_regs *md = ms->dma;
390 int t;
391 struct mesh_target *tp;
392
393 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
394 ms, mr, md);
395 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
396 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
397 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
398 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
399 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
400 mr->sync_params);
401 while(in_8(&mr->fifo_count))
402 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
403 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
404 in_le32(&md->status), in_le32(&md->cmdptr));
405 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
406 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
407 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
408 ms->dma_started, ms->dma_count, ms->n_msgout);
409 for (t = 0; t < 8; ++t) {
410 tp = &ms->tgts[t];
411 if (tp->current_req == NULL)
412 continue;
413 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
414 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
415 }
416 }
417
418 int
419 mesh_reset(Scsi_Cmnd *cmd, unsigned how)
420 {
421 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
422 volatile struct mesh_regs *mr = ms->mesh;
423 volatile struct dbdma_regs *md = ms->dma;
424 unsigned long flags;
425 int ret;
426
427 printk(KERN_DEBUG "mesh_reset %x\n", how);
428 ret = SCSI_RESET_BUS_RESET;
429 save_flags(flags);
430 cli();
431 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
432 out_8(&mr->exception, 0xff); /* clear all exception bits */
433 out_8(&mr->error, 0xff); /* clear all error bits */
434 if (how & SCSI_RESET_SUGGEST_HOST_RESET) {
435 out_8(&mr->sequence, SEQ_RESETMESH);
436 ret |= SCSI_RESET_HOST_RESET;
437 udelay(1);
438 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
439 out_8(&mr->source_id, ms->host->this_id);
440 out_8(&mr->sel_timeout, 25); /* 250ms */
441 out_8(&mr->sync_params, ASYNC_PARAMS);
442 }
443 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
444 udelay(30); /* leave it on for >= 25us */
445 out_8(&mr->bus_status1, 0); /* negate RST */
446 #ifdef DO_ASYNC_RESET
447 if (how & SCSI_RESET_ASYNCHRONOUS) {
448 restore_flags(flags);
449 ret |= SCSI_RESET_PENDING;
450 } else
451 #endif
452 {
453 handle_reset(ms);
454 restore_flags(flags);
455 #ifndef MESH_NEW_STYLE_EH
456 finish_cmds(ms);
457 #endif
458 ret |= SCSI_RESET_SUCCESS;
459 }
460 return ret;
461 }
462
463 /*
464 * If we leave drives set for synchronous transfers (especially
465 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
466 * So, on reboot we reset the SCSI bus.
467 */
468 static int
469 mesh_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
470 {
471 struct mesh_state *ms;
472 volatile struct mesh_regs *mr;
473
474 if (code == SYS_DOWN) {
475 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
476 for (ms = all_meshes; ms != 0; ms = ms->next) {
477 mr = ms->mesh;
478 out_8(&mr->intr_mask, 0);
479 out_8(&mr->interrupt,
480 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
481 out_8(&mr->bus_status1, BS1_RST);
482 udelay(30);
483 out_8(&mr->bus_status1, 0);
484 }
485 }
486 return NOTIFY_DONE;
487 }
488
489 int
490 mesh_command(Scsi_Cmnd *cmd)
491 {
492 printk(KERN_WARNING "whoops... mesh_command called\n");
493 return -1;
494 }
495
496 static void
497 mesh_init(struct mesh_state *ms)
498 {
499 volatile struct mesh_regs *mr = ms->mesh;
500 volatile struct dbdma_regs *md = ms->dma;
501
502 udelay(100);
503
504 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
505 out_8(&mr->exception, 0xff); /* clear all exception bits */
506 out_8(&mr->error, 0xff); /* clear all error bits */
507 out_8(&mr->sequence, SEQ_RESETMESH);
508 udelay(10);
509 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
510 out_8(&mr->source_id, ms->host->this_id);
511 out_8(&mr->sel_timeout, 25); /* 250ms */
512 out_8(&mr->sync_params, ASYNC_PARAMS);
513
514 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
515 udelay(30); /* leave it on for >= 25us */
516 out_8(&mr->bus_status1, 0); /* negate RST */
517
518 out_8(&mr->sequence, SEQ_FLUSHFIFO);
519 udelay(1);
520 out_8(&mr->sync_params, ASYNC_PARAMS);
521 out_8(&mr->sequence, SEQ_ENBRESEL);
522 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
523 }
524
525 /*
526 * Start the next command for a MESH.
527 * Should be called with interrupts disabled.
528 */
529 static void
530 mesh_start(struct mesh_state *ms)
531 {
532 Scsi_Cmnd *cmd, *prev, *next;
533
534 if (ms->phase != idle || ms->current_req != NULL) {
535 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
536 ms->phase, ms);
537 return;
538 }
539
540 while (ms->phase == idle) {
541 prev = NULL;
542 for (cmd = ms->request_q; ; cmd = (Scsi_Cmnd *) cmd->host_scribble) {
543 if (cmd == NULL)
544 return;
545 if (ms->tgts[cmd->target].current_req == NULL)
546 break;
547 prev = cmd;
548 }
549 next = (Scsi_Cmnd *) cmd->host_scribble;
550 if (prev == NULL)
551 ms->request_q = next;
552 else
553 prev->host_scribble = (void *) next;
554 if (next == NULL)
555 ms->request_qtail = prev;
556
557 mesh_start_cmd(ms, cmd);
558 }
559 }
560
561 static void
562 mesh_start_cmd(struct mesh_state *ms, Scsi_Cmnd *cmd)
563 {
564 volatile struct mesh_regs *mr = ms->mesh;
565 int t;
566
567 ms->current_req = cmd;
568 ms->tgts[cmd->target].data_goes_out = data_goes_out(cmd);
569 ms->tgts[cmd->target].current_req = cmd;
570
571 #if 1
572 if (DEBUG_TARGET(cmd)) {
573 int i;
574 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
575 cmd, cmd->serial_number, cmd->target);
576 for (i = 0; i < cmd->cmd_len; ++i)
577 printk(" %x", cmd->cmnd[i]);
578 printk(" use_sg=%d buffer=%p bufflen=%u\n",
579 cmd->use_sg, cmd->request_buffer, cmd->request_bufflen);
580 }
581 #endif
582
583 ms->phase = arbitrating;
584 ms->msgphase = msg_none;
585 ms->data_ptr = 0;
586 ms->dma_started = 0;
587 ms->n_msgout = 0;
588 ms->last_n_msgout = 0;
589 ms->expect_reply = 0;
590 ms->conn_tgt = cmd->target;
591 ms->tgts[cmd->target].saved_ptr = 0;
592 ms->stat = DID_OK;
593 ms->aborting = 0;
594 #ifdef MESH_DBG
595 ms->tgts[cmd->target].n_log = 0;
596 dlog(ms, "start cmd=%x", (int) cmd);
597 #endif
598
599 /* Off we go */
600 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
601 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
602 out_8(&mr->interrupt, INT_CMDDONE);
603 out_8(&mr->sequence, SEQ_ENBRESEL);
604 udelay(1);
605
606 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
607 /*
608 * Some other device has the bus or is arbitrating for it -
609 * probably a target which is about to reselect us.
610 */
611 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
612 MKWORD(mr->interrupt, mr->exception,
613 mr->error, mr->fifo_count));
614 for (t = 100; t > 0; --t) {
615 if ((mr->bus_status1 & (BS1_BSY | BS1_SEL)) == 0)
616 break;
617 if (in_8(&mr->interrupt) != 0) {
618 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
619 MKWORD(mr->interrupt, mr->exception,
620 mr->error, mr->fifo_count));
621 mesh_interrupt(0, (void *)ms, 0);
622 if (ms->phase != arbitrating)
623 return;
624 }
625 udelay(1);
626 }
627 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
628 /* XXX should try again in a little while */
629 ms->stat = DID_BUS_BUSY;
630 ms->phase = idle;
631 mesh_done(ms, 0);
632 return;
633 }
634 }
635
636 /*
637 * Apparently the mesh has a bug where it will assert both its
638 * own bit and the target's bit on the bus during arbitration.
639 */
640 out_8(&mr->dest_id, mr->source_id);
641
642 /*
643 * There appears to be a race with reselection sometimes,
644 * where a target reselects us just as we issue the
645 * arbitrate command. It seems that then the arbitrate
646 * command just hangs waiting for the bus to be free
647 * without giving us a reselection exception.
648 * The only way I have found to get it to respond correctly
649 * is this: disable reselection before issuing the arbitrate
650 * command, then after issuing it, if it looks like a target
651 * is trying to reselect us, reset the mesh and then enable
652 * reselection.
653 */
654 out_8(&mr->sequence, SEQ_DISRESEL);
655 if (in_8(&mr->interrupt) != 0) {
656 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
657 MKWORD(mr->interrupt, mr->exception,
658 mr->error, mr->fifo_count));
659 mesh_interrupt(0, (void *)ms, 0);
660 if (ms->phase != arbitrating)
661 return;
662 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
663 MKWORD(mr->interrupt, mr->exception,
664 mr->error, mr->fifo_count));
665 }
666
667 out_8(&mr->sequence, SEQ_ARBITRATE);
668
669 for (t = 230; t > 0; --t) {
670 if (in_8(&mr->interrupt) != 0)
671 break;
672 udelay(1);
673 }
674 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
675 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
676 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
677 && (mr->bus_status0 & BS0_IO)) {
678 /* looks like a reselection - try resetting the mesh */
679 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
680 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
681 out_8(&mr->sequence, SEQ_RESETMESH);
682 udelay(10);
683 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
684 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
685 out_8(&mr->sequence, SEQ_ENBRESEL);
686 for (t = 10; t > 0 && mr->interrupt == 0; --t)
687 udelay(1);
688 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
689 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
690 #ifndef MESH_MULTIPLE_HOSTS
691 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
692 && (mr->bus_status0 & BS0_IO)) {
693 printk(KERN_ERR "mesh: controller not responding"
694 " to reselection!\n");
695 /*
696 * If this is a target reselecting us, and the
697 * mesh isn't responding, the higher levels of
698 * the scsi code will eventually time out and
699 * reset the bus.
700 */
701 }
702 #endif
703 }
704 }
705
706 #ifndef MESH_NEW_STYLE_EH
707 static void
708 finish_cmds(void *data)
709 {
710 struct mesh_state *ms = data;
711 Scsi_Cmnd *cmd;
712 unsigned long flags;
713
714 for (;;) {
715 spin_lock_irqsave(&io_request_lock, flags);
716 cmd = ms->completed_q;
717 if (cmd == NULL) {
718 spin_unlock_irqrestore(&io_request_lock, flags);
719 break;
720 }
721 ms->completed_q = (Scsi_Cmnd *) cmd->host_scribble;
722 (*cmd->scsi_done)(cmd);
723 spin_unlock_irqrestore(&io_request_lock, flags);
724 }
725 }
726 #endif /* MESH_NEW_STYLE_EH */
727
728 static inline void
729 add_sdtr_msg(struct mesh_state *ms)
730 {
731 int i = ms->n_msgout;
732
733 ms->msgout[i] = EXTENDED_MESSAGE;
734 ms->msgout[i+1] = 3;
735 ms->msgout[i+2] = EXTENDED_SDTR;
736 ms->msgout[i+3] = mesh_sync_period/4;
737 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
738 ms->n_msgout = i + 5;
739 }
740
741 static void
742 set_sdtr(struct mesh_state *ms, int period, int offset)
743 {
744 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
745 volatile struct mesh_regs *mr = ms->mesh;
746 int v, tr;
747
748 tp->sdtr_state = sdtr_done;
749 if (offset == 0) {
750 /* asynchronous */
751 if (SYNC_OFF(tp->sync_params))
752 printk(KERN_INFO "mesh: target %d now asynchronous\n",
753 ms->conn_tgt);
754 tp->sync_params = ASYNC_PARAMS;
755 out_8(&mr->sync_params, ASYNC_PARAMS);
756 return;
757 }
758 /*
759 * We need to compute ceil(clk_freq * period / 500e6) - 2
760 * without incurring overflow.
761 */
762 v = (ms->clk_freq / 5000) * period;
763 if (v <= 250000) {
764 /* special case: sync_period == 5 * clk_period */
765 v = 0;
766 /* units of tr are 100kB/s */
767 tr = (ms->clk_freq + 250000) / 500000;
768 } else {
769 /* sync_period == (v + 2) * 2 * clk_period */
770 v = (v + 99999) / 100000 - 2;
771 if (v > 15)
772 v = 15; /* oops */
773 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
774 }
775 if (offset > 15)
776 offset = 15; /* can't happen */
777 tp->sync_params = SYNC_PARAMS(offset, v);
778 out_8(&mr->sync_params, tp->sync_params);
779 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
780 ms->conn_tgt, tr/10, tr%10);
781 }
782
783 static void
784 start_phase(struct mesh_state *ms)
785 {
786 int i, seq, nb;
787 volatile struct mesh_regs *mr = ms->mesh;
788 volatile struct dbdma_regs *md = ms->dma;
789 Scsi_Cmnd *cmd = ms->current_req;
790 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
791
792 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
793 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
794 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
795 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
796 switch (ms->msgphase) {
797 case msg_none:
798 break;
799
800 case msg_in:
801 out_8(&mr->count_hi, 0);
802 out_8(&mr->count_lo, 1);
803 out_8(&mr->sequence, SEQ_MSGIN + seq);
804 ms->n_msgin = 0;
805 return;
806
807 case msg_out:
808 /*
809 * To make sure ATN drops before we assert ACK for
810 * the last byte of the message, we have to do the
811 * last byte specially.
812 */
813 if (ms->n_msgout <= 0) {
814 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
815 ms->n_msgout);
816 mesh_dump_regs(ms);
817 ms->msgphase = msg_none;
818 break;
819 }
820 if (ALLOW_DEBUG(ms->conn_tgt)) {
821 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
822 ms->n_msgout);
823 for (i = 0; i < ms->n_msgout; ++i)
824 printk(" %x", ms->msgout[i]);
825 printk("\n");
826 }
827 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
828 ms->msgout[1], ms->msgout[2]));
829 out_8(&mr->count_hi, 0);
830 out_8(&mr->sequence, SEQ_FLUSHFIFO);
831 udelay(1);
832 /*
833 * If ATN is not already asserted, we assert it, then
834 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
835 */
836 if ((mr->bus_status0 & BS0_ATN) == 0) {
837 dlog(ms, "bus0 was %.2x explictly asserting ATN", mr->bus_status0);
838 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
839 udelay(1);
840 out_8(&mr->count_lo, 1);
841 out_8(&mr->sequence, SEQ_MSGOUT + seq);
842 out_8(&mr->bus_status0, 0); /* release explicit ATN */
843 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
844 }
845 if (ms->n_msgout == 1) {
846 /*
847 * We can't issue the SEQ_MSGOUT without ATN
848 * until the target has asserted REQ. The logic
849 * in cmd_complete handles both situations:
850 * REQ already asserted or not.
851 */
852 cmd_complete(ms);
853 } else {
854 out_8(&mr->count_lo, ms->n_msgout - 1);
855 out_8(&mr->sequence, SEQ_MSGOUT + seq);
856 for (i = 0; i < ms->n_msgout - 1; ++i)
857 out_8(&mr->fifo, ms->msgout[i]);
858 }
859 return;
860
861 default:
862 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
863 ms->msgphase);
864 }
865
866 switch (ms->phase) {
867 case selecting:
868 out_8(&mr->dest_id, ms->conn_tgt);
869 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
870 break;
871 case commanding:
872 out_8(&mr->sync_params, tp->sync_params);
873 out_8(&mr->count_hi, 0);
874 if (cmd) {
875 out_8(&mr->count_lo, cmd->cmd_len);
876 out_8(&mr->sequence, SEQ_COMMAND + seq);
877 for (i = 0; i < cmd->cmd_len; ++i)
878 out_8(&mr->fifo, cmd->cmnd[i]);
879 } else {
880 out_8(&mr->count_lo, 6);
881 out_8(&mr->sequence, SEQ_COMMAND + seq);
882 for (i = 0; i < 6; ++i)
883 out_8(&mr->fifo, 0);
884 }
885 break;
886 case dataing:
887 /* transfer data, if any */
888 if (!ms->dma_started) {
889 set_dma_cmds(ms, cmd);
890 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
891 out_le32(&md->control, (RUN << 16) | RUN);
892 ms->dma_started = 1;
893 }
894 nb = ms->dma_count;
895 if (nb > 0xfff0)
896 nb = 0xfff0;
897 ms->dma_count -= nb;
898 ms->data_ptr += nb;
899 out_8(&mr->count_lo, nb);
900 out_8(&mr->count_hi, nb >> 8);
901 out_8(&mr->sequence, (tp->data_goes_out?
902 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
903 break;
904 case statusing:
905 out_8(&mr->count_hi, 0);
906 out_8(&mr->count_lo, 1);
907 out_8(&mr->sequence, SEQ_STATUS + seq);
908 break;
909 case busfreeing:
910 case disconnecting:
911 out_8(&mr->sequence, SEQ_ENBRESEL);
912 udelay(1);
913 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
914 MKWORD(mr->interrupt, mr->exception, mr->error,
915 mr->fifo_count));
916 out_8(&mr->sequence, SEQ_BUSFREE);
917 break;
918 default:
919 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
920 ms->phase);
921 dumpslog(ms);
922 }
923
924 }
925
926 static inline void
927 get_msgin(struct mesh_state *ms)
928 {
929 volatile struct mesh_regs *mr = ms->mesh;
930 int i, n;
931
932 n = mr->fifo_count;
933 if (n != 0) {
934 i = ms->n_msgin;
935 ms->n_msgin = i + n;
936 for (; n > 0; --n)
937 ms->msgin[i++] = in_8(&mr->fifo);
938 }
939 }
940
941 static inline int
942 msgin_length(struct mesh_state *ms)
943 {
944 int b, n;
945
946 n = 1;
947 if (ms->n_msgin > 0) {
948 b = ms->msgin[0];
949 if (b == 1) {
950 /* extended message */
951 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
952 } else if (0x20 <= b && b <= 0x2f) {
953 /* 2-byte message */
954 n = 2;
955 }
956 }
957 return n;
958 }
959
960 static void
961 cmd_complete(struct mesh_state *ms)
962 {
963 volatile struct mesh_regs *mr = ms->mesh;
964 Scsi_Cmnd *cmd = ms->current_req;
965 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
966 int seq, n, t;
967
968 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
969 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
970 switch (ms->msgphase) {
971 case msg_out_xxx:
972 /* huh? we expected a phase mismatch */
973 ms->n_msgin = 0;
974 ms->msgphase = msg_in;
975 /* fall through */
976
977 case msg_in:
978 /* should have some message bytes in fifo */
979 get_msgin(ms);
980 n = msgin_length(ms);
981 if (ms->n_msgin < n) {
982 out_8(&mr->count_lo, n - ms->n_msgin);
983 out_8(&mr->sequence, SEQ_MSGIN + seq);
984 } else {
985 ms->msgphase = msg_none;
986 handle_msgin(ms);
987 start_phase(ms);
988 }
989 break;
990
991 case msg_in_bad:
992 out_8(&mr->sequence, SEQ_FLUSHFIFO);
993 udelay(1);
994 out_8(&mr->count_lo, 1);
995 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
996 break;
997
998 case msg_out:
999 /*
1000 * To get the right timing on ATN wrt ACK, we have
1001 * to get the MESH to drop ACK, wait until REQ gets
1002 * asserted, then drop ATN. To do this we first
1003 * issue a SEQ_MSGOUT with ATN and wait for REQ,
1004 * then change the command to a SEQ_MSGOUT w/o ATN.
1005 * If we don't see REQ in a reasonable time, we
1006 * change the command to SEQ_MSGIN with ATN,
1007 * wait for the phase mismatch interrupt, then
1008 * issue the SEQ_MSGOUT without ATN.
1009 */
1010 out_8(&mr->count_lo, 1);
1011 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1012 t = 30; /* wait up to 30us */
1013 while ((mr->bus_status0 & BS0_REQ) == 0 && --t >= 0)
1014 udelay(1);
1015 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1016 MKWORD(mr->error, mr->exception,
1017 mr->fifo_count, mr->count_lo));
1018 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1019 /* whoops, target didn't do what we expected */
1020 ms->last_n_msgout = ms->n_msgout;
1021 ms->n_msgout = 0;
1022 if (in_8(&mr->interrupt) & INT_ERROR) {
1023 printk(KERN_ERR "mesh: error %x in msg_out\n",
1024 in_8(&mr->error));
1025 handle_error(ms);
1026 return;
1027 }
1028 if (in_8(&mr->exception) != EXC_PHASEMM)
1029 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1030 in_8(&mr->exception));
1031 else
1032 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1033 in_8(&mr->bus_status0));
1034 handle_exception(ms);
1035 return;
1036 }
1037 if (mr->bus_status0 & BS0_REQ) {
1038 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1039 udelay(1);
1040 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1041 ms->msgphase = msg_out_last;
1042 } else {
1043 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1044 ms->msgphase = msg_out_xxx;
1045 }
1046 break;
1047
1048 case msg_out_last:
1049 ms->last_n_msgout = ms->n_msgout;
1050 ms->n_msgout = 0;
1051 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1052 start_phase(ms);
1053 break;
1054
1055 case msg_none:
1056 switch (ms->phase) {
1057 case idle:
1058 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1059 dumpslog(ms);
1060 return;
1061 case selecting:
1062 dlog(ms, "Selecting phase at command completion",0);
1063 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1064 (cmd? cmd->lun: 0));
1065 ms->n_msgout = 1;
1066 ms->expect_reply = 0;
1067 if (ms->aborting) {
1068 ms->msgout[0] = ABORT;
1069 ms->n_msgout++;
1070 } else if (tp->sdtr_state == do_sdtr) {
1071 /* add SDTR message */
1072 add_sdtr_msg(ms);
1073 ms->expect_reply = 1;
1074 tp->sdtr_state = sdtr_sent;
1075 }
1076 ms->msgphase = msg_out;
1077 /*
1078 * We need to wait for REQ before dropping ATN.
1079 * We wait for at most 30us, then fall back to
1080 * a scheme where we issue a SEQ_COMMAND with ATN,
1081 * which will give us a phase mismatch interrupt
1082 * when REQ does come, and then we send the message.
1083 */
1084 t = 230; /* wait up to 230us */
1085 while ((mr->bus_status0 & BS0_REQ) == 0) {
1086 if (--t < 0) {
1087 dlog(ms, "impatient for req", ms->n_msgout);
1088 ms->msgphase = msg_none;
1089 break;
1090 }
1091 udelay(1);
1092 }
1093 break;
1094 case dataing:
1095 if (ms->dma_count != 0) {
1096 start_phase(ms);
1097 return;
1098 }
1099 /*
1100 * We can get a phase mismatch here if the target
1101 * changes to the status phase, even though we have
1102 * had a command complete interrupt. Then, if we
1103 * issue the SEQ_STATUS command, we'll get a sequence
1104 * error interrupt. Which isn't so bad except that
1105 * occasionally the mesh actually executes the
1106 * SEQ_STATUS *as well as* giving us the sequence
1107 * error and phase mismatch exception.
1108 */
1109 out_8(&mr->sequence, 0);
1110 out_8(&mr->interrupt,
1111 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1112 halt_dma(ms);
1113 break;
1114 case statusing:
1115 if (cmd) {
1116 cmd->SCp.Status = mr->fifo;
1117 if (DEBUG_TARGET(cmd))
1118 printk(KERN_DEBUG "mesh: status is %x\n",
1119 cmd->SCp.Status);
1120 }
1121 ms->msgphase = msg_in;
1122 break;
1123 case busfreeing:
1124 mesh_done(ms, 1);
1125 return;
1126 case disconnecting:
1127 ms->current_req = 0;
1128 ms->phase = idle;
1129 mesh_start(ms);
1130 return;
1131 default:
1132 break;
1133 }
1134 ++ms->phase;
1135 start_phase(ms);
1136 break;
1137 }
1138 }
1139
1140 static void phase_mismatch(struct mesh_state *ms)
1141 {
1142 volatile struct mesh_regs *mr = ms->mesh;
1143 int phase;
1144
1145 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1146 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1147 phase = mr->bus_status0 & BS0_PHASE;
1148 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1149 /* output the last byte of the message, without ATN */
1150 out_8(&mr->count_lo, 1);
1151 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1152 udelay(1);
1153 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1154 ms->msgphase = msg_out_last;
1155 return;
1156 }
1157
1158 if (ms->msgphase == msg_in) {
1159 get_msgin(ms);
1160 if (ms->n_msgin)
1161 handle_msgin(ms);
1162 }
1163
1164 if (ms->dma_started)
1165 halt_dma(ms);
1166 if (mr->fifo_count) {
1167 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1168 udelay(1);
1169 }
1170
1171 ms->msgphase = msg_none;
1172 switch (phase) {
1173 case BP_DATAIN:
1174 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1175 ms->phase = dataing;
1176 break;
1177 case BP_DATAOUT:
1178 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1179 ms->phase = dataing;
1180 break;
1181 case BP_COMMAND:
1182 ms->phase = commanding;
1183 break;
1184 case BP_STATUS:
1185 ms->phase = statusing;
1186 break;
1187 case BP_MSGIN:
1188 ms->msgphase = msg_in;
1189 ms->n_msgin = 0;
1190 break;
1191 case BP_MSGOUT:
1192 ms->msgphase = msg_out;
1193 if (ms->n_msgout == 0) {
1194 if (ms->aborting) {
1195 do_abort(ms);
1196 } else {
1197 if (ms->last_n_msgout == 0) {
1198 printk(KERN_DEBUG
1199 "mesh: no msg to repeat\n");
1200 ms->msgout[0] = NOP;
1201 ms->last_n_msgout = 1;
1202 }
1203 ms->n_msgout = ms->last_n_msgout;
1204 }
1205 }
1206 break;
1207 default:
1208 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1209 ms->stat = DID_ERROR;
1210 mesh_done(ms, 1);
1211 return;
1212 }
1213
1214 start_phase(ms);
1215 }
1216
1217 static void
1218 reselected(struct mesh_state *ms)
1219 {
1220 volatile struct mesh_regs *mr = ms->mesh;
1221 Scsi_Cmnd *cmd;
1222 struct mesh_target *tp;
1223 int b, t, prev;
1224
1225 switch (ms->phase) {
1226 case idle:
1227 break;
1228 case arbitrating:
1229 if ((cmd = ms->current_req) != NULL) {
1230 /* put the command back on the queue */
1231 cmd->host_scribble = (void *) ms->request_q;
1232 if (ms->request_q == NULL)
1233 ms->request_qtail = cmd;
1234 ms->request_q = cmd;
1235 tp = &ms->tgts[cmd->target];
1236 tp->current_req = NULL;
1237 }
1238 break;
1239 case busfreeing:
1240 ms->phase = reselecting;
1241 mesh_done(ms, 0);
1242 break;
1243 case disconnecting:
1244 break;
1245 default:
1246 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
1247 ms->msgphase, ms->phase, ms->conn_tgt);
1248 dumplog(ms, ms->conn_tgt);
1249 dumpslog(ms);
1250 }
1251
1252 ms->current_req = NULL;
1253 ms->phase = dataing;
1254 ms->msgphase = msg_in;
1255 ms->dma_started = 0;
1256 ms->n_msgout = 0;
1257 ms->last_n_msgout = 0;
1258 prev = ms->conn_tgt;
1259
1260 /*
1261 * We seem to get abortive reselections sometimes.
1262 */
1263 while ((mr->bus_status1 & BS1_BSY) == 0) {
1264 static int mesh_aborted_resels;
1265 mesh_aborted_resels++;
1266 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1267 udelay(1);
1268 out_8(&mr->sequence, SEQ_ENBRESEL);
1269 udelay(5);
1270 dlog(ms, "extra resel err/exc/fc = %.6x",
1271 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
1272 }
1273 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1274 udelay(1);
1275 out_8(&mr->sequence, SEQ_ENBRESEL);
1276 udelay(1);
1277 out_8(&mr->sync_params, ASYNC_PARAMS);
1278
1279 /*
1280 * Find out who reselected us.
1281 */
1282 if (mr->fifo_count == 0) {
1283 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
1284 ms->conn_tgt = ms->host->this_id;
1285 goto bogus;
1286 }
1287 /* get the last byte in the fifo */
1288 do {
1289 b = in_8(&mr->fifo);
1290 dlog(ms, "reseldata %x", b);
1291 } while (in_8(&mr->fifo_count));
1292 for (t = 0; t < 8; ++t)
1293 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
1294 break;
1295 if (b != (1 << t) + (1 << ms->host->this_id)) {
1296 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
1297 ms->conn_tgt = ms->host->this_id;
1298 goto bogus;
1299 }
1300
1301
1302 /*
1303 * Set up to continue with that target's transfer.
1304 */
1305 ms->conn_tgt = t;
1306 tp = &ms->tgts[t];
1307 out_8(&mr->sync_params, tp->sync_params);
1308 if (ALLOW_DEBUG(t)) {
1309 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
1310 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
1311 tp->saved_ptr, tp->data_goes_out, tp->current_req);
1312 }
1313 ms->current_req = tp->current_req;
1314 if (tp->current_req == NULL) {
1315 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
1316 goto bogus;
1317 }
1318 ms->data_ptr = tp->saved_ptr;
1319 dlog(ms, "resel prev tgt=%d", prev);
1320 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
1321 start_phase(ms);
1322 return;
1323
1324 bogus:
1325 dumplog(ms, ms->conn_tgt);
1326 dumpslog(ms);
1327 ms->data_ptr = 0;
1328 ms->aborting = 1;
1329 start_phase(ms);
1330 }
1331
1332 static void do_abort(struct mesh_state *ms)
1333 {
1334 ms->msgout[0] = ABORT;
1335 ms->n_msgout = 1;
1336 ms->aborting = 1;
1337 ms->stat = DID_ABORT;
1338 dlog(ms, "abort", 0);
1339 }
1340
1341 static void
1342 handle_reset(struct mesh_state *ms)
1343 {
1344 int tgt;
1345 struct mesh_target *tp;
1346 Scsi_Cmnd *cmd;
1347 volatile struct mesh_regs *mr = ms->mesh;
1348
1349 for (tgt = 0; tgt < 8; ++tgt) {
1350 tp = &ms->tgts[tgt];
1351 if ((cmd = tp->current_req) != NULL) {
1352 cmd->result = DID_RESET << 16;
1353 tp->current_req = NULL;
1354 mesh_completed(ms, cmd);
1355 }
1356 ms->tgts[tgt].sdtr_state = do_sdtr;
1357 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1358 }
1359 ms->current_req = NULL;
1360 while ((cmd = ms->request_q) != NULL) {
1361 ms->request_q = (Scsi_Cmnd *) cmd->host_scribble;
1362 cmd->result = DID_RESET << 16;
1363 mesh_completed(ms, cmd);
1364 }
1365 ms->phase = idle;
1366 ms->msgphase = msg_none;
1367 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1368 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1369 udelay(1);
1370 out_8(&mr->sync_params, ASYNC_PARAMS);
1371 out_8(&mr->sequence, SEQ_ENBRESEL);
1372 }
1373
1374 static void
1375 do_mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1376 {
1377 unsigned long flags;
1378
1379 spin_lock_irqsave(&io_request_lock, flags);
1380 mesh_interrupt(irq, dev_id, ptregs);
1381 spin_unlock_irqrestore(&io_request_lock, flags);
1382 }
1383
1384 static void handle_error(struct mesh_state *ms)
1385 {
1386 int err, exc, count;
1387 volatile struct mesh_regs *mr = ms->mesh;
1388
1389 err = in_8(&mr->error);
1390 exc = in_8(&mr->exception);
1391 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1392 dlog(ms, "error err/exc/fc/cl=%.8x",
1393 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1394 if (err & ERR_SCSIRESET) {
1395 /* SCSI bus was reset */
1396 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1397 "waiting for end...");
1398 while ((mr->bus_status1 & BS1_RST) != 0)
1399 udelay(1);
1400 printk("done\n");
1401 handle_reset(ms);
1402 /* request_q is empty, no point in mesh_start() */
1403 return;
1404 }
1405 if (err & ERR_UNEXPDISC) {
1406 /* Unexpected disconnect */
1407 if (exc & EXC_RESELECTED) {
1408 reselected(ms);
1409 return;
1410 }
1411 if (!ms->aborting) {
1412 printk(KERN_WARNING "mesh: target %d aborted\n",
1413 ms->conn_tgt);
1414 dumplog(ms, ms->conn_tgt);
1415 dumpslog(ms);
1416 }
1417 out_8(&mr->interrupt, INT_CMDDONE);
1418 ms->stat = DID_ABORT;
1419 mesh_done(ms, 1);
1420 return;
1421 }
1422 if (err & ERR_PARITY) {
1423 if (ms->msgphase == msg_in) {
1424 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1425 ms->conn_tgt);
1426 ms->msgout[0] = MSG_PARITY_ERROR;
1427 ms->n_msgout = 1;
1428 ms->msgphase = msg_in_bad;
1429 cmd_complete(ms);
1430 return;
1431 }
1432 if (ms->stat == DID_OK) {
1433 printk(KERN_ERR "mesh: parity error, target %d\n",
1434 ms->conn_tgt);
1435 ms->stat = DID_PARITY;
1436 }
1437 count = (mr->count_hi << 8) + mr->count_lo;
1438 if (count == 0) {
1439 cmd_complete(ms);
1440 } else {
1441 /* reissue the data transfer command */
1442 out_8(&mr->sequence, mr->sequence);
1443 }
1444 return;
1445 }
1446 if (err & ERR_SEQERR) {
1447 if (exc & EXC_RESELECTED) {
1448 /* This can happen if we issue a command to
1449 get the bus just after the target reselects us. */
1450 static int mesh_resel_seqerr;
1451 mesh_resel_seqerr++;
1452 reselected(ms);
1453 return;
1454 }
1455 if (exc == EXC_PHASEMM) {
1456 static int mesh_phasemm_seqerr;
1457 mesh_phasemm_seqerr++;
1458 phase_mismatch(ms);
1459 return;
1460 }
1461 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1462 err, exc);
1463 } else {
1464 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1465 }
1466 mesh_dump_regs(ms);
1467 dumplog(ms, ms->conn_tgt);
1468 if (ms->phase > selecting && (mr->bus_status1 & BS1_BSY)) {
1469 /* try to do what the target wants */
1470 do_abort(ms);
1471 phase_mismatch(ms);
1472 return;
1473 }
1474 ms->stat = DID_ERROR;
1475 mesh_done(ms, 1);
1476 }
1477
1478 static void handle_exception(struct mesh_state *ms)
1479 {
1480 int exc;
1481 volatile struct mesh_regs *mr = ms->mesh;
1482
1483 exc = in_8(&mr->exception);
1484 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1485 if (exc & EXC_RESELECTED) {
1486 static int mesh_resel_exc;
1487 mesh_resel_exc++;
1488 reselected(ms);
1489 } else if (exc == EXC_ARBLOST) {
1490 printk(KERN_DEBUG "mesh: lost arbitration\n");
1491 ms->stat = DID_BUS_BUSY;
1492 mesh_done(ms, 1);
1493 } else if (exc == EXC_SELTO) {
1494 /* selection timed out */
1495 ms->stat = DID_BAD_TARGET;
1496 mesh_done(ms, 1);
1497 } else if (exc == EXC_PHASEMM) {
1498 /* target wants to do something different:
1499 find out what it wants and do it. */
1500 phase_mismatch(ms);
1501 } else {
1502 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1503 mesh_dump_regs(ms);
1504 dumplog(ms, ms->conn_tgt);
1505 do_abort(ms);
1506 phase_mismatch(ms);
1507 }
1508 }
1509
1510 static void
1511 mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1512 {
1513 struct mesh_state *ms = (struct mesh_state *) dev_id;
1514 volatile struct mesh_regs *mr = ms->mesh;
1515 int intr;
1516
1517 #if 0
1518 if (ALLOW_DEBUG(ms->conn_tgt))
1519 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1520 "phase=%d msgphase=%d\n", mr->bus_status0,
1521 mr->interrupt, mr->exception, mr->error,
1522 ms->phase, ms->msgphase);
1523 #endif
1524 while ((intr = in_8(&mr->interrupt)) != 0) {
1525 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1526 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1527 if (intr & INT_ERROR) {
1528 handle_error(ms);
1529 } else if (intr & INT_EXCEPTION) {
1530 handle_exception(ms);
1531 } else if (intr & INT_CMDDONE) {
1532 out_8(&mr->interrupt, INT_CMDDONE);
1533 cmd_complete(ms);
1534 }
1535 }
1536 }
1537
1538 static void
1539 handle_msgin(struct mesh_state *ms)
1540 {
1541 int i, code;
1542 Scsi_Cmnd *cmd = ms->current_req;
1543 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1544
1545 if (ms->n_msgin == 0)
1546 return;
1547 code = ms->msgin[0];
1548 if (ALLOW_DEBUG(ms->conn_tgt)) {
1549 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1550 for (i = 0; i < ms->n_msgin; ++i)
1551 printk(" %x", ms->msgin[i]);
1552 printk("\n");
1553 }
1554 dlog(ms, "msgin msg=%.8x",
1555 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1556
1557 ms->expect_reply = 0;
1558 ms->n_msgout = 0;
1559 if (ms->n_msgin < msgin_length(ms))
1560 goto reject;
1561 if (cmd)
1562 cmd->SCp.Message = code;
1563 switch (code) {
1564 case COMMAND_COMPLETE:
1565 break;
1566 case EXTENDED_MESSAGE:
1567 switch (ms->msgin[2]) {
1568 case EXTENDED_MODIFY_DATA_POINTER:
1569 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1570 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1571 break;
1572 case EXTENDED_SDTR:
1573 if (tp->sdtr_state != sdtr_sent) {
1574 /* reply with an SDTR */
1575 add_sdtr_msg(ms);
1576 /* limit period to at least his value,
1577 offset to no more than his */
1578 if (ms->msgout[3] < ms->msgin[3])
1579 ms->msgout[3] = ms->msgin[3];
1580 if (ms->msgout[4] > ms->msgin[4])
1581 ms->msgout[4] = ms->msgin[4];
1582 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1583 ms->msgphase = msg_out;
1584 } else {
1585 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1586 }
1587 break;
1588 default:
1589 goto reject;
1590 }
1591 break;
1592 case SAVE_POINTERS:
1593 tp->saved_ptr = ms->data_ptr;
1594 break;
1595 case RESTORE_POINTERS:
1596 ms->data_ptr = tp->saved_ptr;
1597 break;
1598 case DISCONNECT:
1599 ms->phase = disconnecting;
1600 break;
1601 case ABORT:
1602 break;
1603 case MESSAGE_REJECT:
1604 if (tp->sdtr_state == sdtr_sent)
1605 set_sdtr(ms, 0, 0);
1606 break;
1607 case NOP:
1608 break;
1609 default:
1610 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1611 if (cmd == NULL) {
1612 do_abort(ms);
1613 ms->msgphase = msg_out;
1614 } else if (code != cmd->lun + IDENTIFY_BASE) {
1615 printk(KERN_WARNING "mesh: lun mismatch "
1616 "(%d != %d) on reselection from "
1617 "target %d\n", i, cmd->lun,
1618 ms->conn_tgt);
1619 }
1620 break;
1621 }
1622 goto reject;
1623 }
1624 return;
1625
1626 reject:
1627 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1628 ms->conn_tgt);
1629 for (i = 0; i < ms->n_msgin; ++i)
1630 printk(" %x", ms->msgin[i]);
1631 printk("\n");
1632 ms->msgout[0] = MESSAGE_REJECT;
1633 ms->n_msgout = 1;
1634 ms->msgphase = msg_out;
1635 }
1636
1637 static void
1638 mesh_done(struct mesh_state *ms, int start_next)
1639 {
1640 Scsi_Cmnd *cmd;
1641 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1642
1643 cmd = ms->current_req;
1644 ms->current_req = 0;
1645 tp->current_req = 0;
1646 if (cmd) {
1647 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
1648 if (ms->stat == DID_OK)
1649 cmd->result += (cmd->SCp.Message << 8);
1650 if (DEBUG_TARGET(cmd)) {
1651 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
1652 cmd->result, ms->data_ptr, cmd->request_bufflen);
1653 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
1654 && cmd->request_buffer != 0) {
1655 unsigned char *b = cmd->request_buffer;
1656 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
1657 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
1658 }
1659 }
1660 cmd->SCp.this_residual -= ms->data_ptr;
1661 mesh_completed(ms, cmd);
1662 }
1663 if (start_next) {
1664 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
1665 udelay(1);
1666 ms->phase = idle;
1667 mesh_start(ms);
1668 }
1669 }
1670
1671 static void
1672 mesh_completed(struct mesh_state *ms, Scsi_Cmnd *cmd)
1673 {
1674 #ifdef MESH_NEW_STYLE_EH
1675 (*cmd->scsi_done)(cmd);
1676 #else
1677 if (ms->completed_q == NULL)
1678 ms->completed_q = cmd;
1679 else
1680 ms->completed_qtail->host_scribble = (void *) cmd;
1681 ms->completed_qtail = cmd;
1682 cmd->host_scribble = NULL;
1683 queue_task(&ms->tqueue, &tq_immediate);
1684 mark_bh(IMMEDIATE_BH);
1685 #endif /* MESH_NEW_STYLE_EH */
1686 }
1687
1688 /*
1689 * Set up DMA commands for transferring data.
1690 */
1691 static void
1692 set_dma_cmds(struct mesh_state *ms, Scsi_Cmnd *cmd)
1693 {
1694 int i, dma_cmd, total, off, dtot;
1695 struct scatterlist *scl;
1696 struct dbdma_cmd *dcmds;
1697
1698 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1699 OUTPUT_MORE: INPUT_MORE;
1700 dcmds = ms->dma_cmds;
1701 dtot = 0;
1702 if (cmd) {
1703 cmd->SCp.this_residual = cmd->request_bufflen;
1704 if (cmd->use_sg > 0) {
1705 total = 0;
1706 scl = (struct scatterlist *) cmd->buffer;
1707 off = ms->data_ptr;
1708 for (i = 0; i < cmd->use_sg; ++i, ++scl) {
1709 total += scl->length;
1710 if (off >= scl->length) {
1711 off -= scl->length;
1712 continue;
1713 }
1714 if (scl->length > 0xffff)
1715 panic("mesh: scatterlist element >= 64k");
1716 st_le16(&dcmds->req_count, scl->length - off);
1717 st_le16(&dcmds->command, dma_cmd);
1718 st_le32(&dcmds->phy_addr,
1719 virt_to_phys(scl->address) + off);
1720 dcmds->xfer_status = 0;
1721 ++dcmds;
1722 dtot += scl->length - off;
1723 off = 0;
1724 }
1725 } else if (ms->data_ptr < cmd->request_bufflen) {
1726 dtot = cmd->request_bufflen - ms->data_ptr;
1727 if (dtot > 0xffff)
1728 panic("mesh: transfer size >= 64k");
1729 st_le16(&dcmds->req_count, dtot);
1730 st_le32(&dcmds->phy_addr,
1731 virt_to_phys(cmd->request_buffer) + ms->data_ptr);
1732 dcmds->xfer_status = 0;
1733 ++dcmds;
1734 }
1735 }
1736 if (dtot == 0) {
1737 /* Either the target has overrun our buffer,
1738 or the caller didn't provide a buffer. */
1739 static char mesh_extra_buf[64];
1740
1741 dtot = sizeof(mesh_extra_buf);
1742 st_le16(&dcmds->req_count, dtot);
1743 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1744 dcmds->xfer_status = 0;
1745 ++dcmds;
1746 }
1747 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1748 st_le16(&dcmds[-1].command, dma_cmd);
1749 memset(dcmds, 0, sizeof(*dcmds));
1750 st_le16(&dcmds->command, DBDMA_STOP);
1751 ms->dma_count = dtot;
1752 }
1753
1754 static void
1755 halt_dma(struct mesh_state *ms)
1756 {
1757 volatile struct dbdma_regs *md = ms->dma;
1758 volatile struct mesh_regs *mr = ms->mesh;
1759 Scsi_Cmnd *cmd = ms->current_req;
1760 int t, nb;
1761
1762 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1763 /* wait a little while until the fifo drains */
1764 t = 50;
1765 while (t > 0 && mr->fifo_count != 0
1766 && (in_le32(&md->status) & ACTIVE) != 0) {
1767 --t;
1768 udelay(1);
1769 }
1770 }
1771 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1772 nb = (mr->count_hi << 8) + mr->count_lo;
1773 dlog(ms, "halt_dma fc/count=%.6x",
1774 MKWORD(0, mr->fifo_count, 0, nb));
1775 if (ms->tgts[ms->conn_tgt].data_goes_out)
1776 nb += mr->fifo_count;
1777 /* nb is the number of bytes not yet transferred
1778 to/from the target. */
1779 ms->data_ptr -= nb;
1780 dlog(ms, "data_ptr %x", ms->data_ptr);
1781 if (ms->data_ptr < 0) {
1782 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1783 ms->data_ptr, nb, ms);
1784 ms->data_ptr = 0;
1785 #ifdef MESH_DBG
1786 dumplog(ms, ms->conn_tgt);
1787 dumpslog(ms);
1788 #endif /* MESH_DBG */
1789 } else if (cmd && cmd->request_bufflen != 0 &&
1790 ms->data_ptr > cmd->request_bufflen) {
1791 printk(KERN_DEBUG "mesh: target %d overrun, "
1792 "data_ptr=%x total=%x goes_out=%d\n",
1793 ms->conn_tgt, ms->data_ptr, cmd->request_bufflen,
1794 ms->tgts[ms->conn_tgt].data_goes_out);
1795 }
1796 ms->dma_started = 0;
1797 }
1798
1799 /*
1800 * Work out whether we expect data to go out from the host adaptor or into it.
1801 * (If this information is available from somewhere else in the scsi
1802 * code, somebody please let me know :-)
1803 */
1804 static int
1805 data_goes_out(Scsi_Cmnd *cmd)
1806 {
1807 switch (cmd->cmnd[0]) {
1808 case CHANGE_DEFINITION:
1809 case COMPARE:
1810 case COPY:
1811 case COPY_VERIFY:
1812 case FORMAT_UNIT:
1813 case LOG_SELECT:
1814 case MEDIUM_SCAN:
1815 case MODE_SELECT:
1816 case MODE_SELECT_10:
1817 case REASSIGN_BLOCKS:
1818 case RESERVE:
1819 case SEARCH_EQUAL:
1820 case SEARCH_EQUAL_12:
1821 case SEARCH_HIGH:
1822 case SEARCH_HIGH_12:
1823 case SEARCH_LOW:
1824 case SEARCH_LOW_12:
1825 case SEND_DIAGNOSTIC:
1826 case SEND_VOLUME_TAG:
1827 case SET_WINDOW:
1828 case UPDATE_BLOCK:
1829 case WRITE_BUFFER:
1830 case WRITE_6:
1831 case WRITE_10:
1832 case WRITE_12:
1833 case WRITE_LONG:
1834 case WRITE_LONG_2: /* alternate code for WRITE_LONG */
1835 case WRITE_SAME:
1836 case WRITE_VERIFY:
1837 case WRITE_VERIFY_12:
1838 return 1;
1839 default:
1840 return 0;
1841 }
1842 }
1843
1844 #ifdef MESH_DBG
1845 static inline u32 readtb(void)
1846 {
1847 u32 tb;
1848
1849 #ifdef DBG_USE_TB
1850 /* Beware: if you enable this, it will crash on 601s. */
1851 asm ("mftb %0" : "=r" (tb) : );
1852 #else
1853 tb = 0;
1854 #endif
1855 return tb;
1856 }
1857
1858 static void dlog(struct mesh_state *ms, char *fmt, int a)
1859 {
1860 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1861 struct dbglog *tlp, *slp;
1862
1863 tlp = &tp->log[tp->log_ix];
1864 slp = &ms->log[ms->log_ix];
1865 tlp->fmt = fmt;
1866 tlp->tb = readtb();
1867 tlp->phase = (ms->msgphase << 4) + ms->phase;
1868 tlp->bs0 = ms->mesh->bus_status0;
1869 tlp->bs1 = ms->mesh->bus_status1;
1870 tlp->tgt = ms->conn_tgt;
1871 tlp->d = a;
1872 *slp = *tlp;
1873 if (++tp->log_ix >= N_DBG_LOG)
1874 tp->log_ix = 0;
1875 if (tp->n_log < N_DBG_LOG)
1876 ++tp->n_log;
1877 if (++ms->log_ix >= N_DBG_SLOG)
1878 ms->log_ix = 0;
1879 if (ms->n_log < N_DBG_SLOG)
1880 ++ms->n_log;
1881 }
1882
1883 static void dumplog(struct mesh_state *ms, int t)
1884 {
1885 struct mesh_target *tp = &ms->tgts[t];
1886 struct dbglog *lp;
1887 int i;
1888
1889 if (tp->n_log == 0)
1890 return;
1891 i = tp->log_ix - tp->n_log;
1892 if (i < 0)
1893 i += N_DBG_LOG;
1894 tp->n_log = 0;
1895 do {
1896 lp = &tp->log[i];
1897 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
1898 t, lp->bs1, lp->bs0, lp->phase);
1899 #ifdef DBG_USE_TB
1900 printk("tb=%10u ", lp->tb);
1901 #endif
1902 printk(lp->fmt, lp->d);
1903 printk("\n");
1904 if (++i >= N_DBG_LOG)
1905 i = 0;
1906 } while (i != tp->log_ix);
1907 }
1908
1909 static void dumpslog(struct mesh_state *ms)
1910 {
1911 struct dbglog *lp;
1912 int i;
1913
1914 if (ms->n_log == 0)
1915 return;
1916 i = ms->log_ix - ms->n_log;
1917 if (i < 0)
1918 i += N_DBG_SLOG;
1919 ms->n_log = 0;
1920 do {
1921 lp = &ms->log[i];
1922 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
1923 lp->bs1, lp->bs0, lp->phase, lp->tgt);
1924 #ifdef DBG_USE_TB
1925 printk("tb=%10u ", lp->tb);
1926 #endif
1927 printk(lp->fmt, lp->d);
1928 printk("\n");
1929 if (++i >= N_DBG_SLOG)
1930 i = 0;
1931 } while (i != ms->log_ix);
1932 }
1933 #endif /* MESH_DBG */
1934
1935 static Scsi_Host_Template driver_template = SCSI_MESH;
1936
1937 #include "scsi_module.c"
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