drivers/sbus/char/uctrl.c

   1 /* $Id: uctrl.c,v 1.9 2000/11/08 05:04:06 davem Exp $
   2  * uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3
   3  *
   4  * Copyright 1999 Derrick J Brashear (shadow@dementia.org)
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/sched.h>
   9 #include <linux/errno.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/malloc.h>
  13 #include <linux/ioport.h>
  14 #include <linux/init.h>
  15 #include <linux/miscdevice.h>
  16 #include <linux/mm.h>
  17
  18 #include <asm/openprom.h>
  19 #include <asm/oplib.h>
  20 #include <asm/system.h>
  21 #include <asm/irq.h>
  22 #include <asm/io.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/sbus.h>
  25
  26 #define UCTRL_MINOR     174
  27
  28 #define DEBUG 1
  29 #ifdef DEBUG
  30 #define dprintk(x) printk x
  31 #else
  32 #define dprintk(x)
  33 #endif
  34
  35 struct uctrl_regs {
  36         volatile u32 uctrl_intr;
  37         volatile u32 uctrl_data;
  38         volatile u32 uctrl_stat;
  39         volatile u32 uctrl_xxx[5];
  40 };
  41
  42 struct ts102_regs {
  43         volatile u32 card_a_intr;
  44         volatile u32 card_a_stat;
  45         volatile u32 card_a_ctrl;
  46         volatile u32 card_a_xxx;
  47         volatile u32 card_b_intr;
  48         volatile u32 card_b_stat;
  49         volatile u32 card_b_ctrl;
  50         volatile u32 card_b_xxx;
  51         volatile u32 uctrl_intr;
  52         volatile u32 uctrl_data;
  53         volatile u32 uctrl_stat;
  54         volatile u32 uctrl_xxx;
  55         volatile u32 ts102_xxx[4];
  56 };
  57
  58 /* Bits for uctrl_intr register */
  59 #define UCTRL_INTR_TXE_REQ         0x01    /* transmit FIFO empty int req */
  60 #define UCTRL_INTR_TXNF_REQ        0x02    /* transmit FIFO not full int req */
  61 #define UCTRL_INTR_RXNE_REQ        0x04    /* receive FIFO not empty int req */
  62 #define UCTRL_INTR_RXO_REQ         0x08    /* receive FIFO overflow int req */
  63 #define UCTRL_INTR_TXE_MSK         0x10    /* transmit FIFO empty mask */
  64 #define UCTRL_INTR_TXNF_MSK        0x20    /* transmit FIFO not full mask */
  65 #define UCTRL_INTR_RXNE_MSK        0x40    /* receive FIFO not empty mask */
  66 #define UCTRL_INTR_RXO_MSK         0x80    /* receive FIFO overflow mask */
  67
  68 /* Bits for uctrl_stat register */
  69 #define UCTRL_STAT_TXE_STA         0x01    /* transmit FIFO empty status */
  70 #define UCTRL_STAT_TXNF_STA        0x02    /* transmit FIFO not full status */
  71 #define UCTRL_STAT_RXNE_STA        0x04    /* receive FIFO not empty status */
  72 #define UCTRL_STAT_RXO_STA         0x08    /* receive FIFO overflow status */
  73
  74 static const char *uctrl_extstatus[16] = {
  75         "main power available",
  76         "internal battery attached",
  77         "external battery attached",
  78         "external VGA attached",
  79         "external keyboard attached",
  80         "external mouse attached",
  81         "lid down",
  82         "internal battery currently charging",
  83         "external battery currently charging",
  84         "internal battery currently discharging",
  85         "external battery currently discharging",
  86 };
  87
  88 /* Everything required for one transaction with the uctrl */
  89 struct uctrl_txn {
  90         u8 opcode;
  91         u8 inbits;
  92         u8 outbits;
  93         u8 *inbuf;
  94         u8 *outbuf;
  95 };
  96
  97 struct uctrl_status {
  98         u8 current_temp; /* 0x07 */
  99         u8 reset_status; /* 0x0b */
 100         u16 event_status; /* 0x0c */
 101         u16 error_status; /* 0x10 */
 102         u16 external_status; /* 0x11, 0x1b */
 103         u8 internal_charge; /* 0x18 */
 104         u8 external_charge; /* 0x19 */
 105         u16 control_lcd; /* 0x20 */
 106         u8 control_bitport; /* 0x21 */
 107         u8 speaker_volume; /* 0x23 */
 108         u8 control_tft_brightness; /* 0x24 */
 109         u8 control_kbd_repeat_delay; /* 0x28 */
 110         u8 control_kbd_repeat_rate; /* 0x29 */
 111         u8 control_screen_contrast; /* 0x2F */
 112 };
 113
 114 enum uctrl_opcode {
 115   READ_SERIAL_NUMBER=0x1,
 116   READ_ETHERNET_ADDRESS=0x2,
 117   READ_HARDWARE_VERSION=0x3,
 118   READ_MICROCONTROLLER_VERSION=0x4,
 119   READ_MAX_TEMPERATURE=0x5,
 120   READ_MIN_TEMPERATURE=0x6,
 121   READ_CURRENT_TEMPERATURE=0x7,
 122   READ_SYSTEM_VARIANT=0x8,
 123   READ_POWERON_CYCLES=0x9,
 124   READ_POWERON_SECONDS=0xA,
 125   READ_RESET_STATUS=0xB,
 126   READ_EVENT_STATUS=0xC,
 127   READ_REAL_TIME_CLOCK=0xD,
 128   READ_EXTERNAL_VGA_PORT=0xE,
 129   READ_MICROCONTROLLER_ROM_CHECKSUM=0xF,
 130   READ_ERROR_STATUS=0x10,
 131   READ_EXTERNAL_STATUS=0x11,
 132   READ_USER_CONFIGURATION_AREA=0x12,
 133   READ_MICROCONTROLLER_VOLTAGE=0x13,
 134   READ_INTERNAL_BATTERY_VOLTAGE=0x14,
 135   READ_DCIN_VOLTAGE=0x15,
 136   READ_HORIZONTAL_POINTER_VOLTAGE=0x16,
 137   READ_VERTICAL_POINTER_VOLTAGE=0x17,
 138   READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18,
 139   READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19,
 140   READ_REAL_TIME_CLOCK_ALARM=0x1A,
 141   READ_EVENT_STATUS_NO_RESET=0x1B,
 142   READ_INTERNAL_KEYBOARD_LAYOUT=0x1C,
 143   READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D,
 144   READ_EEPROM_STATUS=0x1E,
 145   CONTROL_LCD=0x20,
 146   CONTROL_BITPORT=0x21,
 147   SPEAKER_VOLUME=0x23,
 148   CONTROL_TFT_BRIGHTNESS=0x24,
 149   CONTROL_WATCHDOG=0x25,
 150   CONTROL_FACTORY_EEPROM_AREA=0x26,
 151   CONTROL_KBD_TIME_UNTIL_REPEAT=0x28,
 152   CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29,
 153   CONTROL_TIMEZONE=0x2A,
 154   CONTROL_MARK_SPACE_RATIO=0x2B,
 155   CONTROL_DIAGNOSTIC_MODE=0x2E,
 156   CONTROL_SCREEN_CONTRAST=0x2F,
 157   RING_BELL=0x30,
 158   SET_DIAGNOSTIC_STATUS=0x32,
 159   CLEAR_KEY_COMBINATION_TABLE=0x33,
 160   PERFORM_SOFTWARE_RESET=0x34,
 161   SET_REAL_TIME_CLOCK=0x35,
 162   RECALIBRATE_POINTING_STICK=0x36,
 163   SET_BELL_FREQUENCY=0x37,
 164   SET_INTERNAL_BATTERY_CHARGE_RATE=0x39,
 165   SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A,
 166   SET_REAL_TIME_CLOCK_ALARM=0x3B,
 167   READ_EEPROM=0x40,
 168   WRITE_EEPROM=0x41,
 169   WRITE_TO_STATUS_DISPLAY=0x42,
 170   DEFINE_SPECIAL_CHARACTER=0x43,
 171   DEFINE_KEY_COMBINATION_ENTRY=0x50,
 172   DEFINE_STRING_TABLE_ENTRY=0x51,
 173   DEFINE_STATUS_SCREEN_DISPLAY=0x52,
 174   PERFORM_EMU_COMMANDS=0x64,
 175   READ_EMU_REGISTER=0x65,
 176   WRITE_EMU_REGISTER=0x66,
 177   READ_EMU_RAM=0x67,
 178   WRITE_EMU_RAM=0x68,
 179   READ_BQ_REGISTER=0x69,
 180   WRITE_BQ_REGISTER=0x6A,
 181   SET_USER_PASSWORD=0x70,
 182   VERIFY_USER_PASSWORD=0x71,
 183   GET_SYSTEM_PASSWORD_KEY=0x72,
 184   VERIFY_SYSTEM_PASSWORD=0x73,
 185   POWER_OFF=0x82,
 186   POWER_RESTART=0x83,
 187 };
 188
 189 struct uctrl_driver {
 190         struct uctrl_regs *regs;
 191         int irq;
 192         int pending;
 193         struct uctrl_status status;
 194 };
 195
 196 static struct uctrl_driver drv;
 197
 198 void uctrl_get_event_status(void);
 199 void uctrl_get_external_status(void);
 200
 201 static loff_t
 202 uctrl_llseek(struct file *file, loff_t offset, int type)
 203 {
 204         return -ESPIPE;
 205 }
 206
 207 static int
 208 uctrl_ioctl(struct inode *inode, struct file *file,
 209               unsigned int cmd, unsigned long arg)
 210 {
 211         switch (cmd) {
 212                 default:
 213                         return -EINVAL;
 214         }
 215         return 0;
 216 }
 217
 218 static int
 219 uctrl_open(struct inode *inode, struct file *file)
 220 {
 221         uctrl_get_event_status();
 222         uctrl_get_external_status();
 223         return 0;
 224 }
 225
 226 void uctrl_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 227 {
 228         struct uctrl_driver *driver = (struct uctrl_driver *)dev_id;
 229         printk("in uctrl_interrupt\n");
 230 }
 231
 232 static struct file_operations uctrl_fops = {
 233         owner:          THIS_MODULE,
 234         llseek:         uctrl_llseek,
 235         ioctl:          uctrl_ioctl,
 236         open:           uctrl_open,
 237 };
 238
 239 static struct miscdevice uctrl_dev = {
 240         UCTRL_MINOR,
 241         "uctrl",
 242         &uctrl_fops
 243 };
 244
 245 /* Wait for space to write, then write to it */
 246 #define WRITEUCTLDATA(value) \
 247 { \
 248   unsigned int i; \
 249   for (i = 0; i < 10000; i++) { \
 250     if (UCTRL_STAT_TXNF_STA & driver->regs->uctrl_stat) \
 251       break; \
 252   } \
 253   dprintk(("write data 0x%02x\n", value)); \
 254   driver->regs->uctrl_data = value; \
 255 }
 256
 257 /* Wait for something to read, read it, then clear the bit */
 258 #define READUCTLDATA(value) \
 259 { \
 260   unsigned int i; \
 261   value = 0; \
 262   for (i = 0; i < 10000; i++) { \
 263     if ((UCTRL_STAT_RXNE_STA & driver->regs->uctrl_stat) == 0) \
 264       break; \
 265     udelay(1); \
 266   } \
 267   value = driver->regs->uctrl_data; \
 268   dprintk(("read data 0x%02x\n", value)); \
 269   driver->regs->uctrl_stat = UCTRL_STAT_RXNE_STA; \
 270 }
 271
 272 void uctrl_set_video(int status)
 273 {
 274         struct uctrl_driver *driver = &drv;
 275
 276 }
 277
 278 static void uctrl_do_txn(struct uctrl_txn *txn)
 279 {
 280         struct uctrl_driver *driver = &drv;
 281         int stat, incnt, outcnt, bytecnt, intr;
 282         u32 byte;
 283
 284         stat = driver->regs->uctrl_stat;
 285         intr = driver->regs->uctrl_intr;
 286         driver->regs->uctrl_stat = stat;
 287
 288         dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr));
 289
 290         incnt = txn->inbits;
 291         outcnt = txn->outbits;
 292         byte = (txn->opcode << 8);
 293         WRITEUCTLDATA(byte);
 294
 295         bytecnt = 0;
 296         while (incnt > 0) {
 297                 byte = (txn->inbuf[bytecnt] << 8);
 298                 WRITEUCTLDATA(byte);
 299                 incnt--;
 300                 bytecnt++;
 301         }
 302
 303         /* Get the ack */
 304         READUCTLDATA(byte);
 305         dprintk(("ack was %x\n", (byte >> 8)));
 306
 307         bytecnt = 0;
 308         while (outcnt > 0) {
 309                 READUCTLDATA(byte);
 310                 txn->outbuf[bytecnt] = (byte >> 8);
 311                 dprintk(("set byte to %02x\n", byte));
 312                 outcnt--;
 313                 bytecnt++;
 314         }
 315 }
 316
 317 void uctrl_get_event_status()
 318 {
 319         struct uctrl_driver *driver = &drv;
 320         struct uctrl_txn txn;
 321         u8 outbits[2];
 322
 323         txn.opcode = READ_EVENT_STATUS;
 324         txn.inbits = 0;
 325         txn.outbits = 2;
 326         txn.inbuf = 0;
 327         txn.outbuf = outbits;
 328
 329         uctrl_do_txn(&txn);
 330
 331         dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
 332         driver->status.event_status =
 333                 ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff);
 334         dprintk(("ev is %x\n", driver->status.event_status));
 335 }
 336
 337 void uctrl_get_external_status()
 338 {
 339         struct uctrl_driver *driver = &drv;
 340         struct uctrl_txn txn;
 341         u8 outbits[2];
 342         int i, v;
 343
 344         txn.opcode = READ_EXTERNAL_STATUS;
 345         txn.inbits = 0;
 346         txn.outbits = 2;
 347         txn.inbuf = 0;
 348         txn.outbuf = outbits;
 349
 350         uctrl_do_txn(&txn);
 351
 352         dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff)));
 353         driver->status.external_status =
 354                 ((outbits[0] * 256) + (outbits[1]));
 355         dprintk(("ex is %x\n", driver->status.external_status));
 356         v = driver->status.external_status;
 357         for (i = 0; v != 0; i++, v >>= 1) {
 358                 if (v & 1) {
 359                         dprintk(("%s%s", " ", uctrl_extstatus[i]));
 360                 }
 361         }
 362         dprintk(("\n"));
 363
 364 }
 365
 366 static int __init ts102_uctrl_init(void)
 367 {
 368         struct uctrl_driver *driver = &drv;
 369         int len, i;
 370         struct linux_prom_irqs tmp_irq[2];
 371         unsigned int vaddr[2] = { 0, 0 };
 372         int tmpnode, uctrlnode = prom_getchild(prom_root_node);
 373
 374         tmpnode = prom_searchsiblings(uctrlnode, "obio");
 375
 376         if (tmpnode)
 377           uctrlnode = prom_getchild(tmpnode);
 378
 379         uctrlnode = prom_searchsiblings(uctrlnode, "uctrl");
 380
 381         if (!uctrlnode)
 382                 return -ENODEV;
 383
 384         /* the prom mapped it for us */
 385         len = prom_getproperty(uctrlnode, "address", (void *) vaddr,
 386                                sizeof(vaddr));
 387         driver->regs = (struct uctrl_regs *)vaddr[0];
 388
 389         len = prom_getproperty(uctrlnode, "intr", (char *) tmp_irq,
 390                                sizeof(tmp_irq));
 391
 392         /* Flush device */
 393         READUCTLDATA(len);
 394
 395         if(!driver->irq)
 396                 driver->irq = tmp_irq[0].pri;
 397
 398         request_irq(driver->irq, uctrl_interrupt, 0,
 399                     "uctrl", driver);
 400
 401         enable_irq(driver->irq);
 402
 403         if (misc_register(&uctrl_dev)) {
 404                 printk("%s: unable to get misc minor %d\n",
 405                        __FUNCTION__, uctrl_dev.minor);
 406                 disable_irq(driver->irq);
 407                 free_irq(driver->irq, driver);
 408                 return -ENODEV;
 409         }
 410
 411         driver->regs->uctrl_intr = UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK;
 412         printk("uctrl: 0x%x (irq %s)\n", driver->regs, __irq_itoa(driver->irq));
 413         uctrl_get_event_status();
 414         uctrl_get_external_status();
 415         return 0;
 416 }
 417
 418 static void __exit ts102_uctrl_cleanup(void)
 419 {
 420         struct uctrl_driver *driver = &drv;
 421
 422         misc_deregister(&uctrl_dev);
 423         if (driver->irq) {
 424                 disable_irq(driver->irq);
 425                 free_irq(driver->irq, driver);
 426         }
 427         if (driver->regs)
 428                 driver->regs = 0;
 429 }
 430
 431 module_init(ts102_uctrl_init);
 432 module_exit(ts102_uctrl_cleanup);