1 /* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*-
2 * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Rickard E. (Rik) Faith <faith@valinux.com>
32 #define __NO_VERSION__
34 #include "gamma_drv.h"
36 #include <linux/interrupt.h> /* For task queue support */
39 /* WARNING!!! MAGIC NUMBER!!! The number of regions already added to the
40 kernel must be specified here. Currently, the number is 2. This must
41 match the order the X server uses for instantiating register regions ,
42 or must be passed in a new ioctl. */
43 #define GAMMA_REG(reg) \
47 : ((reg < 0x10000) ? 1 : ((reg < 0x11000) ? 2 : 3))))
49 #define GAMMA_OFF(reg) \
58 #define GAMMA_BASE(reg) ((unsigned long)dev->maplist[GAMMA_REG(reg)]->handle)
59 #define GAMMA_ADDR(reg) (GAMMA_BASE(reg) + GAMMA_OFF(reg))
60 #define GAMMA_DEREF(reg) *(__volatile__ int *)GAMMA_ADDR(reg)
61 #define GAMMA_READ(reg) GAMMA_DEREF(reg)
62 #define GAMMA_WRITE(reg,val) do { GAMMA_DEREF(reg) = val; } while (0)
64 #define GAMMA_BROADCASTMASK 0x9378
65 #define GAMMA_COMMANDINTENABLE 0x0c48
66 #define GAMMA_DMAADDRESS 0x0028
67 #define GAMMA_DMACOUNT 0x0030
68 #define GAMMA_FILTERMODE 0x8c00
69 #define GAMMA_GCOMMANDINTFLAGS 0x0c50
70 #define GAMMA_GCOMMANDMODE 0x0c40
71 #define GAMMA_GCOMMANDSTATUS 0x0c60
72 #define GAMMA_GDELAYTIMER 0x0c38
73 #define GAMMA_GDMACONTROL 0x0060
74 #define GAMMA_GINTENABLE 0x0808
75 #define GAMMA_GINTFLAGS 0x0810
76 #define GAMMA_INFIFOSPACE 0x0018
77 #define GAMMA_OUTFIFOWORDS 0x0020
78 #define GAMMA_OUTPUTFIFO 0x2000
79 #define GAMMA_SYNC 0x8c40
80 #define GAMMA_SYNC_TAG 0x0188
82 static inline void gamma_dma_dispatch(drm_device_t
*dev
, unsigned long address
,
85 GAMMA_WRITE(GAMMA_DMAADDRESS
, virt_to_phys((void *)address
));
86 while (GAMMA_READ(GAMMA_GCOMMANDSTATUS
) != 4)
88 GAMMA_WRITE(GAMMA_DMACOUNT
, length
/ 4);
91 static inline void gamma_dma_quiescent_single(drm_device_t
*dev
)
93 while (GAMMA_READ(GAMMA_DMACOUNT
))
95 while (GAMMA_READ(GAMMA_INFIFOSPACE
) < 3)
98 GAMMA_WRITE(GAMMA_FILTERMODE
, 1 << 10);
99 GAMMA_WRITE(GAMMA_SYNC
, 0);
102 while (!GAMMA_READ(GAMMA_OUTFIFOWORDS
))
104 } while (GAMMA_READ(GAMMA_OUTPUTFIFO
) != GAMMA_SYNC_TAG
);
107 static inline void gamma_dma_quiescent_dual(drm_device_t
*dev
)
109 while (GAMMA_READ(GAMMA_DMACOUNT
))
111 while (GAMMA_READ(GAMMA_INFIFOSPACE
) < 3)
114 GAMMA_WRITE(GAMMA_BROADCASTMASK
, 3);
116 GAMMA_WRITE(GAMMA_FILTERMODE
, 1 << 10);
117 GAMMA_WRITE(GAMMA_SYNC
, 0);
119 /* Read from first MX */
121 while (!GAMMA_READ(GAMMA_OUTFIFOWORDS
))
123 } while (GAMMA_READ(GAMMA_OUTPUTFIFO
) != GAMMA_SYNC_TAG
);
125 /* Read from second MX */
127 while (!GAMMA_READ(GAMMA_OUTFIFOWORDS
+ 0x10000))
129 } while (GAMMA_READ(GAMMA_OUTPUTFIFO
+ 0x10000) != GAMMA_SYNC_TAG
);
132 static inline void gamma_dma_ready(drm_device_t
*dev
)
134 while (GAMMA_READ(GAMMA_DMACOUNT
))
138 static inline int gamma_dma_is_ready(drm_device_t
*dev
)
140 return !GAMMA_READ(GAMMA_DMACOUNT
);
143 static void gamma_dma_service(int irq
, void *device
, struct pt_regs
*regs
)
145 drm_device_t
*dev
= (drm_device_t
*)device
;
146 drm_device_dma_t
*dma
= dev
->dma
;
148 atomic_inc(&dev
->total_irq
);
149 GAMMA_WRITE(GAMMA_GDELAYTIMER
, 0xc350/2); /* 0x05S */
150 GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS
, 8);
151 GAMMA_WRITE(GAMMA_GINTFLAGS
, 0x2001);
152 if (gamma_dma_is_ready(dev
)) {
153 /* Free previous buffer */
154 if (test_and_set_bit(0, &dev
->dma_flag
)) {
155 atomic_inc(&dma
->total_missed_free
);
158 if (dma
->this_buffer
) {
159 drm_free_buffer(dev
, dma
->this_buffer
);
160 dma
->this_buffer
= NULL
;
162 clear_bit(0, &dev
->dma_flag
);
164 /* Dispatch new buffer */
165 queue_task(&dev
->tq
, &tq_immediate
);
166 mark_bh(IMMEDIATE_BH
);
170 /* Only called by gamma_dma_schedule. */
171 static int gamma_do_dma(drm_device_t
*dev
, int locked
)
173 unsigned long address
;
174 unsigned long length
;
177 drm_device_dma_t
*dma
= dev
->dma
;
178 #if DRM_DMA_HISTOGRAM
179 cycles_t dma_start
, dma_stop
;
182 if (test_and_set_bit(0, &dev
->dma_flag
)) {
183 atomic_inc(&dma
->total_missed_dma
);
187 #if DRM_DMA_HISTOGRAM
188 dma_start
= get_cycles();
191 if (!dma
->next_buffer
) {
192 DRM_ERROR("No next_buffer\n");
193 clear_bit(0, &dev
->dma_flag
);
197 buf
= dma
->next_buffer
;
198 address
= (unsigned long)buf
->address
;
201 DRM_DEBUG("context %d, buffer %d (%ld bytes)\n",
202 buf
->context
, buf
->idx
, length
);
204 if (buf
->list
== DRM_LIST_RECLAIM
) {
205 drm_clear_next_buffer(dev
);
206 drm_free_buffer(dev
, buf
);
207 clear_bit(0, &dev
->dma_flag
);
212 DRM_ERROR("0 length buffer\n");
213 drm_clear_next_buffer(dev
);
214 drm_free_buffer(dev
, buf
);
215 clear_bit(0, &dev
->dma_flag
);
219 if (!gamma_dma_is_ready(dev
)) {
220 clear_bit(0, &dev
->dma_flag
);
224 if (buf
->while_locked
) {
225 if (!_DRM_LOCK_IS_HELD(dev
->lock
.hw_lock
->lock
)) {
226 DRM_ERROR("Dispatching buffer %d from pid %d"
227 " \"while locked\", but no lock held\n",
231 if (!locked
&& !drm_lock_take(&dev
->lock
.hw_lock
->lock
,
232 DRM_KERNEL_CONTEXT
)) {
233 atomic_inc(&dma
->total_missed_lock
);
234 clear_bit(0, &dev
->dma_flag
);
239 if (dev
->last_context
!= buf
->context
240 && !(dev
->queuelist
[buf
->context
]->flags
241 & _DRM_CONTEXT_PRESERVED
)) {
242 /* PRE: dev->last_context != buf->context */
243 if (drm_context_switch(dev
, dev
->last_context
, buf
->context
)) {
244 drm_clear_next_buffer(dev
);
245 drm_free_buffer(dev
, buf
);
250 /* POST: we will wait for the context
251 switch and will dispatch on a later call
252 when dev->last_context == buf->context.
253 NOTE WE HOLD THE LOCK THROUGHOUT THIS
257 drm_clear_next_buffer(dev
);
260 buf
->list
= DRM_LIST_PEND
;
261 #if DRM_DMA_HISTOGRAM
262 buf
->time_dispatched
= get_cycles();
265 gamma_dma_dispatch(dev
, address
, length
);
266 drm_free_buffer(dev
, dma
->this_buffer
);
267 dma
->this_buffer
= buf
;
269 atomic_add(length
, &dma
->total_bytes
);
270 atomic_inc(&dma
->total_dmas
);
272 if (!buf
->while_locked
&& !dev
->context_flag
&& !locked
) {
273 if (drm_lock_free(dev
, &dev
->lock
.hw_lock
->lock
,
274 DRM_KERNEL_CONTEXT
)) {
280 clear_bit(0, &dev
->dma_flag
);
282 #if DRM_DMA_HISTOGRAM
283 dma_stop
= get_cycles();
284 atomic_inc(&dev
->histo
.dma
[drm_histogram_slot(dma_stop
- dma_start
)]);
290 static void gamma_dma_schedule_timer_wrapper(unsigned long dev
)
292 gamma_dma_schedule((drm_device_t
*)dev
, 0);
295 static void gamma_dma_schedule_tq_wrapper(void *dev
)
297 gamma_dma_schedule(dev
, 0);
300 int gamma_dma_schedule(drm_device_t
*dev
, int locked
)
309 drm_device_dma_t
*dma
= dev
->dma
;
310 #if DRM_DMA_HISTOGRAM
311 cycles_t schedule_start
;
314 if (test_and_set_bit(0, &dev
->interrupt_flag
)) {
316 atomic_inc(&dma
->total_missed_sched
);
319 missed
= atomic_read(&dma
->total_missed_sched
);
321 #if DRM_DMA_HISTOGRAM
322 schedule_start
= get_cycles();
326 if (dev
->context_flag
) {
327 clear_bit(0, &dev
->interrupt_flag
);
330 if (dma
->next_buffer
) {
331 /* Unsent buffer that was previously
332 selected, but that couldn't be sent
333 because the lock could not be obtained
334 or the DMA engine wasn't ready. Try
336 atomic_inc(&dma
->total_tried
);
337 if (!(retcode
= gamma_do_dma(dev
, locked
))) {
338 atomic_inc(&dma
->total_hit
);
343 next
= drm_select_queue(dev
,
344 gamma_dma_schedule_timer_wrapper
);
346 q
= dev
->queuelist
[next
];
347 buf
= drm_waitlist_get(&q
->waitlist
);
348 dma
->next_buffer
= buf
;
350 if (buf
&& buf
->list
== DRM_LIST_RECLAIM
) {
351 drm_clear_next_buffer(dev
);
352 drm_free_buffer(dev
, buf
);
355 } while (next
>= 0 && !dma
->next_buffer
);
356 if (dma
->next_buffer
) {
357 if (!(retcode
= gamma_do_dma(dev
, locked
))) {
364 if (missed
!= atomic_read(&dma
->total_missed_sched
)) {
365 atomic_inc(&dma
->total_lost
);
366 if (gamma_dma_is_ready(dev
)) goto again
;
368 if (processed
&& gamma_dma_is_ready(dev
)) {
369 atomic_inc(&dma
->total_lost
);
375 clear_bit(0, &dev
->interrupt_flag
);
377 #if DRM_DMA_HISTOGRAM
378 atomic_inc(&dev
->histo
.schedule
[drm_histogram_slot(get_cycles()
384 static int gamma_dma_priority(drm_device_t
*dev
, drm_dma_t
*d
)
386 unsigned long address
;
387 unsigned long length
;
393 drm_buf_t
*last_buf
= NULL
;
394 drm_device_dma_t
*dma
= dev
->dma
;
395 DECLARE_WAITQUEUE(entry
, current
);
397 /* Turn off interrupt handling */
398 while (test_and_set_bit(0, &dev
->interrupt_flag
)) {
400 if (signal_pending(current
)) return -EINTR
;
402 if (!(d
->flags
& _DRM_DMA_WHILE_LOCKED
)) {
403 while (!drm_lock_take(&dev
->lock
.hw_lock
->lock
,
404 DRM_KERNEL_CONTEXT
)) {
406 if (signal_pending(current
)) {
407 clear_bit(0, &dev
->interrupt_flag
);
413 atomic_inc(&dma
->total_prio
);
415 for (i
= 0; i
< d
->send_count
; i
++) {
416 idx
= d
->send_indices
[i
];
417 if (idx
< 0 || idx
>= dma
->buf_count
) {
418 DRM_ERROR("Index %d (of %d max)\n",
419 d
->send_indices
[i
], dma
->buf_count
- 1);
422 buf
= dma
->buflist
[ idx
];
423 if (buf
->pid
!= current
->pid
) {
424 DRM_ERROR("Process %d using buffer owned by %d\n",
425 current
->pid
, buf
->pid
);
429 if (buf
->list
!= DRM_LIST_NONE
) {
430 DRM_ERROR("Process %d using %d's buffer on list %d\n",
431 current
->pid
, buf
->pid
, buf
->list
);
435 /* This isn't a race condition on
436 buf->list, since our concern is the
437 buffer reclaim during the time the
438 process closes the /dev/drm? handle, so
439 it can't also be doing DMA. */
440 buf
->list
= DRM_LIST_PRIO
;
441 buf
->used
= d
->send_sizes
[i
];
442 buf
->context
= d
->context
;
443 buf
->while_locked
= d
->flags
& _DRM_DMA_WHILE_LOCKED
;
444 address
= (unsigned long)buf
->address
;
447 DRM_ERROR("0 length buffer\n");
450 DRM_ERROR("Sending pending buffer:"
451 " buffer %d, offset %d\n",
452 d
->send_indices
[i
], i
);
457 DRM_ERROR("Sending waiting buffer:"
458 " buffer %d, offset %d\n",
459 d
->send_indices
[i
], i
);
465 if (dev
->last_context
!= buf
->context
466 && !(dev
->queuelist
[buf
->context
]->flags
467 & _DRM_CONTEXT_PRESERVED
)) {
468 add_wait_queue(&dev
->context_wait
, &entry
);
469 current
->state
= TASK_INTERRUPTIBLE
;
470 /* PRE: dev->last_context != buf->context */
471 drm_context_switch(dev
, dev
->last_context
,
473 /* POST: we will wait for the context
474 switch and will dispatch on a later call
475 when dev->last_context == buf->context.
476 NOTE WE HOLD THE LOCK THROUGHOUT THIS
479 current
->state
= TASK_RUNNING
;
480 remove_wait_queue(&dev
->context_wait
, &entry
);
481 if (signal_pending(current
)) {
485 if (dev
->last_context
!= buf
->context
) {
486 DRM_ERROR("Context mismatch: %d %d\n",
492 #if DRM_DMA_HISTOGRAM
493 buf
->time_queued
= get_cycles();
494 buf
->time_dispatched
= buf
->time_queued
;
496 gamma_dma_dispatch(dev
, address
, length
);
497 atomic_add(length
, &dma
->total_bytes
);
498 atomic_inc(&dma
->total_dmas
);
501 drm_free_buffer(dev
, last_buf
);
509 gamma_dma_ready(dev
);
510 drm_free_buffer(dev
, last_buf
);
513 if (must_free
&& !dev
->context_flag
) {
514 if (drm_lock_free(dev
, &dev
->lock
.hw_lock
->lock
,
515 DRM_KERNEL_CONTEXT
)) {
519 clear_bit(0, &dev
->interrupt_flag
);
523 static int gamma_dma_send_buffers(drm_device_t
*dev
, drm_dma_t
*d
)
525 DECLARE_WAITQUEUE(entry
, current
);
526 drm_buf_t
*last_buf
= NULL
;
528 drm_device_dma_t
*dma
= dev
->dma
;
530 if (d
->flags
& _DRM_DMA_BLOCK
) {
531 last_buf
= dma
->buflist
[d
->send_indices
[d
->send_count
-1]];
532 add_wait_queue(&last_buf
->dma_wait
, &entry
);
535 if ((retcode
= drm_dma_enqueue(dev
, d
))) {
536 if (d
->flags
& _DRM_DMA_BLOCK
)
537 remove_wait_queue(&last_buf
->dma_wait
, &entry
);
541 gamma_dma_schedule(dev
, 0);
543 if (d
->flags
& _DRM_DMA_BLOCK
) {
544 DRM_DEBUG("%d waiting\n", current
->pid
);
546 current
->state
= TASK_INTERRUPTIBLE
;
547 if (!last_buf
->waiting
&& !last_buf
->pending
)
548 break; /* finished */
550 if (signal_pending(current
)) {
551 retcode
= -EINTR
; /* Can't restart */
555 current
->state
= TASK_RUNNING
;
556 DRM_DEBUG("%d running\n", current
->pid
);
557 remove_wait_queue(&last_buf
->dma_wait
, &entry
);
559 || (last_buf
->list
==DRM_LIST_PEND
&& !last_buf
->pending
)) {
560 if (!waitqueue_active(&last_buf
->dma_wait
)) {
561 drm_free_buffer(dev
, last_buf
);
565 DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n",
569 DRM_WAITCOUNT(dev
, d
->context
),
579 int gamma_dma(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
582 drm_file_t
*priv
= filp
->private_data
;
583 drm_device_t
*dev
= priv
->dev
;
584 drm_device_dma_t
*dma
= dev
->dma
;
588 if (copy_from_user(&d
, (drm_dma_t
*)arg
, sizeof(d
)))
590 DRM_DEBUG("%d %d: %d send, %d req\n",
591 current
->pid
, d
.context
, d
.send_count
, d
.request_count
);
593 if (d
.context
== DRM_KERNEL_CONTEXT
|| d
.context
>= dev
->queue_slots
) {
594 DRM_ERROR("Process %d using context %d\n",
595 current
->pid
, d
.context
);
598 if (d
.send_count
< 0 || d
.send_count
> dma
->buf_count
) {
599 DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n",
600 current
->pid
, d
.send_count
, dma
->buf_count
);
603 if (d
.request_count
< 0 || d
.request_count
> dma
->buf_count
) {
604 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
605 current
->pid
, d
.request_count
, dma
->buf_count
);
610 if (d
.flags
& _DRM_DMA_PRIORITY
)
611 retcode
= gamma_dma_priority(dev
, &d
);
613 retcode
= gamma_dma_send_buffers(dev
, &d
);
618 if (!retcode
&& d
.request_count
) {
619 retcode
= drm_dma_get_buffers(dev
, &d
);
622 DRM_DEBUG("%d returning, granted = %d\n",
623 current
->pid
, d
.granted_count
);
624 if (copy_to_user((drm_dma_t
*)arg
, &d
, sizeof(d
)))
630 int gamma_irq_install(drm_device_t
*dev
, int irq
)
634 if (!irq
) return -EINVAL
;
636 down(&dev
->struct_sem
);
638 up(&dev
->struct_sem
);
642 up(&dev
->struct_sem
);
644 DRM_DEBUG("%d\n", irq
);
646 dev
->context_flag
= 0;
647 dev
->interrupt_flag
= 0;
650 dev
->dma
->next_buffer
= NULL
;
651 dev
->dma
->next_queue
= NULL
;
652 dev
->dma
->this_buffer
= NULL
;
654 INIT_LIST_HEAD(&dev
->tq
.list
);
656 dev
->tq
.routine
= gamma_dma_schedule_tq_wrapper
;
660 /* Before installing handler */
661 GAMMA_WRITE(GAMMA_GCOMMANDMODE
, 0);
662 GAMMA_WRITE(GAMMA_GDMACONTROL
, 0);
664 /* Install handler */
665 if ((retcode
= request_irq(dev
->irq
,
670 down(&dev
->struct_sem
);
672 up(&dev
->struct_sem
);
676 /* After installing handler */
677 GAMMA_WRITE(GAMMA_GINTENABLE
, 0x2001);
678 GAMMA_WRITE(GAMMA_COMMANDINTENABLE
, 0x0008);
679 GAMMA_WRITE(GAMMA_GDELAYTIMER
, 0x39090);
684 int gamma_irq_uninstall(drm_device_t
*dev
)
688 down(&dev
->struct_sem
);
691 up(&dev
->struct_sem
);
693 if (!irq
) return -EINVAL
;
695 DRM_DEBUG("%d\n", irq
);
697 GAMMA_WRITE(GAMMA_GDELAYTIMER
, 0);
698 GAMMA_WRITE(GAMMA_COMMANDINTENABLE
, 0);
699 GAMMA_WRITE(GAMMA_GINTENABLE
, 0);
706 int gamma_control(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
709 drm_file_t
*priv
= filp
->private_data
;
710 drm_device_t
*dev
= priv
->dev
;
714 if (copy_from_user(&ctl
, (drm_control_t
*)arg
, sizeof(ctl
)))
718 case DRM_INST_HANDLER
:
719 if ((retcode
= gamma_irq_install(dev
, ctl
.irq
)))
722 case DRM_UNINST_HANDLER
:
723 if ((retcode
= gamma_irq_uninstall(dev
)))
732 int gamma_lock(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
735 drm_file_t
*priv
= filp
->private_data
;
736 drm_device_t
*dev
= priv
->dev
;
737 DECLARE_WAITQUEUE(entry
, current
);
741 #if DRM_DMA_HISTOGRAM
744 dev
->lck_start
= start
= get_cycles();
747 if (copy_from_user(&lock
, (drm_lock_t
*)arg
, sizeof(lock
)))
750 if (lock
.context
== DRM_KERNEL_CONTEXT
) {
751 DRM_ERROR("Process %d using kernel context %d\n",
752 current
->pid
, lock
.context
);
756 DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
757 lock
.context
, current
->pid
, dev
->lock
.hw_lock
->lock
,
760 if (lock
.context
< 0 || lock
.context
>= dev
->queue_count
)
762 q
= dev
->queuelist
[lock
.context
];
764 ret
= drm_flush_block_and_flush(dev
, lock
.context
, lock
.flags
);
767 if (_DRM_LOCKING_CONTEXT(dev
->lock
.hw_lock
->lock
)
769 long j
= jiffies
- dev
->lock
.lock_time
;
771 if (j
> 0 && j
<= DRM_LOCK_SLICE
) {
772 /* Can't take lock if we just had it and
773 there is contention. */
774 current
->state
= TASK_INTERRUPTIBLE
;
778 add_wait_queue(&dev
->lock
.lock_queue
, &entry
);
780 current
->state
= TASK_INTERRUPTIBLE
;
781 if (!dev
->lock
.hw_lock
) {
782 /* Device has been unregistered */
786 if (drm_lock_take(&dev
->lock
.hw_lock
->lock
,
788 dev
->lock
.pid
= current
->pid
;
789 dev
->lock
.lock_time
= jiffies
;
790 atomic_inc(&dev
->total_locks
);
791 atomic_inc(&q
->total_locks
);
792 break; /* Got lock */
796 atomic_inc(&dev
->total_sleeps
);
798 if (signal_pending(current
)) {
803 current
->state
= TASK_RUNNING
;
804 remove_wait_queue(&dev
->lock
.lock_queue
, &entry
);
807 drm_flush_unblock(dev
, lock
.context
, lock
.flags
); /* cleanup phase */
810 sigemptyset(&dev
->sigmask
);
811 sigaddset(&dev
->sigmask
, SIGSTOP
);
812 sigaddset(&dev
->sigmask
, SIGTSTP
);
813 sigaddset(&dev
->sigmask
, SIGTTIN
);
814 sigaddset(&dev
->sigmask
, SIGTTOU
);
815 dev
->sigdata
.context
= lock
.context
;
816 dev
->sigdata
.lock
= dev
->lock
.hw_lock
;
817 block_all_signals(drm_notifier
, &dev
->sigdata
, &dev
->sigmask
);
819 if (lock
.flags
& _DRM_LOCK_READY
)
820 gamma_dma_ready(dev
);
821 if (lock
.flags
& _DRM_LOCK_QUIESCENT
) {
822 if (gamma_found() == 1) {
823 gamma_dma_quiescent_single(dev
);
825 gamma_dma_quiescent_dual(dev
);
829 DRM_DEBUG("%d %s\n", lock
.context
, ret
? "interrupted" : "has lock");
831 #if DRM_DMA_HISTOGRAM
832 atomic_inc(&dev
->histo
.lacq
[drm_histogram_slot(get_cycles() - start
)]);