2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/errno.h>
33 #include <linux/atm.h>
34 #include <linux/atmdev.h>
35 #include <linux/sonet.h>
36 #include <linux/skbuff.h>
37 #include <linux/time.h>
38 #include <linux/delay.h>
39 #include <linux/uio.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
43 #include <asm/system.h>
45 #include <asm/atomic.h>
46 #include <asm/uaccess.h>
47 #include <asm/string.h>
48 #include <asm/byteorder.h>
52 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
53 #define description_string "Madge ATM Horizon [Ultra] driver"
54 #define version_string "1.2.1"
56 static inline void __init
show_version (void) {
57 printk ("%s version %s\n", description_string
, version_string
);
64 Driver and documentation by:
66 Chris Aston Madge Networks
67 Giuliano Procida Madge Networks
68 Simon Benham Madge Networks
69 Simon Johnson Madge Networks
70 Various Others Madge Networks
72 Some inspiration taken from other drivers by:
75 Kari Mettinen University of Helsinki
76 Werner Almesberger EPFL LRC
80 I Hardware, detection, initialisation and shutdown.
84 This driver should handle all variants of the PCI Madge ATM adapters
85 with the Horizon chipset. These are all PCI cards supporting PIO, BM
86 DMA and a form of MMIO (registers only, not internal RAM).
88 The driver is only known to work with SONET and UTP Horizon Ultra
89 cards at 155Mb/s. However, code is in place to deal with both the
90 original Horizon and 25Mb/s operation.
92 There are two revisions of the Horizon ASIC: the original and the
93 Ultra. Details of hardware bugs are in section III.
95 The ASIC version can be distinguished by chip markings but is NOT
96 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100 Horizon => Collage 25 PCI Adapter (UTP and STP)
101 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
102 Ambassador x => Collage 155 PCI Server (completely different)
104 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
105 have a Madge B154 plus glue logic serializer. I have also found a
106 really ancient version of this with slightly different glue. It
107 comes with the revision 0 (140-025-01) ASIC.
109 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
110 output (UTP) or an HP HFBR 5205 output (SONET). It has either
111 Madge's SAMBA framer or a SUNI-lite device (early versions). It
112 comes with the revision 1 (140-027-01) ASIC.
116 All Horizon-based cards present with the same PCI Vendor and Device
117 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
118 to enable bus-mastering (with appropriate latency).
120 ATM_LAYER_STATUS in the control register distinguishes between the
121 two possible physical layers (25 and 155). It is not clear whether
122 the 155 cards can also operate at 25Mbps. We rely on the fact that a
123 card operates at 155 if and only if it has the newer Horizon Ultra
126 For 155 cards the two possible framers are probed for and then set
131 The card is reset and then put into a known state. The physical
132 layer is configured for normal operation at the appropriate speed;
133 in the case of the 155 cards, the framer is initialised with
134 line-based timing; the internal RAM is zeroed and the allocation of
135 buffers for RX and TX is made; the Burnt In Address is read and
136 copied to the ATM ESI; various policy settings for RX (VPI bits,
137 unknown VCs, oam cells) are made. Ideally all policy items should be
138 configurable at module load (if not actually on-demand), however,
139 only the vpi vs vci bit allocation can be specified at insmod.
143 This is in response to module_cleaup. No VCs are in use and the card
144 should be idle; it is reset.
146 II Driver software (as it should be)
148 0. Traffic Parameters
150 The traffic classes (not an enumeration) are currently: ATM_NONE (no
151 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
152 (compatible with everything). Together with (perhaps only some of)
153 the following items they make up the traffic specification.
156 unsigned char traffic_class; traffic class (ATM_UBR, ...)
157 int max_pcr; maximum PCR in cells per second
158 int pcr; desired PCR in cells per second
159 int min_pcr; minimum PCR in cells per second
160 int max_cdv; maximum CDV in microseconds
161 int max_sdu; maximum SDU in bytes
164 Note that these denote bandwidth available not bandwidth used; the
165 possibilities according to ATMF are:
167 Real Time (cdv and max CDT given)
169 CBR(pcr) pcr bandwidth always available
170 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
174 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178 mbs is max burst size (bucket)
179 pcr and scr have associated cdvt values
180 mcr is like scr but has no cdtv
181 cdtv may differ at each hop
183 Some of the above items are qos items (as opposed to traffic
184 parameters). We have nothing to do with qos. All except ABR can have
185 their traffic parameters converted to GCRA parameters. The GCRA may
186 be implemented as a (real-number) leaky bucket. The GCRA can be used
187 in complicated ways by switches and in simpler ways by end-stations.
188 It can be used both to filter incoming cells and shape out-going
191 ATM Linux actually supports:
193 ATM_NONE() (no traffic in this direction)
194 ATM_UBR(max_frame_size)
195 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199 A traffic specification consists of the AAL type and separate
200 traffic specifications for either direction. In ATM Linux it is:
203 struct atm_trafprm txtp;
204 struct atm_trafprm rxtp;
210 ATM_NO_AAL AAL not specified
211 ATM_AAL0 "raw" ATM cells
214 ATM_AAL34 AAL3/4 (data)
216 ATM_SAAL signaling AAL
218 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
219 it does not implement AAL 3/4 SAR and it has a different notion of
220 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
221 supported by this driver.
223 The Horizon has limited support for ABR (including UBR), VBR and
224 CBR. Each TX channel has a bucket (containing up to 31 cell units)
225 and two timers (PCR and SCR) associated with it that can be used to
226 govern cell emissions and host notification (in the case of ABR this
227 is presumably so that RM cells may be emitted at appropriate times).
228 The timers may either be disabled or may be set to any of 240 values
229 (determined by the clock crystal, a fixed (?) per-device divider, a
230 configurable divider and a configurable timer preload value).
232 At the moment only UBR and CBR are supported by the driver. VBR will
233 be supported as soon as ATM for Linux supports it. ABR support is
234 very unlikely as RM cell handling is completely up to the driver.
236 1. TX (TX channel setup and TX transfer)
238 The TX half of the driver owns the TX Horizon registers. The TX
239 component in the IRQ handler is the BM completion handler. This can
240 only be entered when tx_busy is true (enforced by hardware). The
241 other TX component can only be entered when tx_busy is false
242 (enforced by driver). So TX is single-threaded.
244 Apart from a minor optimisation to not re-select the last channel,
245 the TX send component works as follows:
247 Atomic test and set tx_busy until we succeed; we should implement
248 some sort of timeout so that tx_busy will never be stuck at true.
250 If no TX channel is set up for this VC we wait for an idle one (if
251 necessary) and set it up.
253 At this point we have a TX channel ready for use. We wait for enough
254 buffers to become available then start a TX transmit (set the TX
255 descriptor, schedule transfer, exit).
257 The IRQ component handles TX completion (stats, free buffer, tx_busy
258 unset, exit). We also re-schedule further transfers for the same
261 TX setup in more detail:
263 TX open is a nop, the relevant information is held in the hrz_vcc
264 (vcc->dev_data) structure and is "cached" on the card.
266 TX close gets the TX lock and clears the channel from the "cache".
268 2. RX (Data Available and RX transfer)
270 The RX half of the driver owns the RX registers. There are two RX
271 components in the IRQ handler: the data available handler deals with
272 fresh data that has arrived on the card, the BM completion handler
273 is very similar to the TX completion handler. The data available
274 handler grabs the rx_lock and it is only released once the data has
275 been discarded or completely transferred to the host. The BM
276 completion handler only runs when the lock is held; the data
277 available handler is locked out over the same period.
279 Data available on the card triggers an interrupt. If the data is not
280 suitable for our existing RX channels or we cannot allocate a buffer
281 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
282 transfers may be scheduled for the same frame.
284 RX setup in more detail:
291 0. Byte vs Word addressing of adapter RAM.
293 A design feature; see the .h file (especially the memory map).
295 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297 The host must not start a transmit direction transfer at a
298 non-four-byte boundary in host memory. Instead the host should
299 perform a byte, or a two byte, or one byte followed by two byte
300 transfer in order to start the rest of the transfer on a four byte
303 Simultaneous transmit and receive direction bus master transfers are
306 The simplest solution to these two is to always do PIO (never DMA)
307 in the TX direction on the original Horizon. More complicated
308 solutions are likely to hurt my brain.
310 2. Loss of buffer on close VC
312 When a VC is being closed, the buffer associated with it is not
313 returned to the pool. The host must store the reference to this
314 buffer and when opening a new VC then give it to that new VC.
316 The host intervention currently consists of stacking such a buffer
317 pointer at VC close and checking the stack at VC open.
319 3. Failure to close a VC
321 If a VC is currently receiving a frame then closing the VC may fail
322 and the frame continues to be received.
324 The solution is to make sure any received frames are flushed when
325 ready. This is currently done just before the solution to 2.
327 4. PCI bus (original Horizon only, fixed in Ultra)
329 Reading from the data port prior to initialisation will hang the PCI
330 bus. Just don't do that then! We don't.
334 . Timer code may be broken.
336 . Allow users to specify buffer allocation split for TX and RX.
338 . Deal once and for all with buggy VC close.
340 . Handle interrupted and/or non-blocking operations.
342 . Change some macros to functions and move from .h to .c.
344 . Try to limit the number of TX frames each VC may have queued, in
345 order to reduce the chances of TX buffer exhaustion.
347 . Implement VBR (bucket and timers not understood) and ABR (need to
348 do RM cells manually); also no Linux support for either.
350 . Implement QoS changes on open VCs (involves extracting parts of VC open
351 and close into separate functions and using them to make changes).
355 /********** globals **********/
357 static hrz_dev
* hrz_devs
= NULL
;
358 static struct timer_list housekeeping
;
360 static unsigned short debug
= 0;
361 static unsigned short vpi_bits
= 0;
362 static unsigned short max_tx_size
= 9000;
363 static unsigned short max_rx_size
= 9000;
364 static unsigned char pci_lat
= 0;
366 /********** access functions **********/
368 /* Read / Write Horizon registers */
369 static inline void wr_regl (const hrz_dev
* dev
, unsigned char reg
, u32 data
) {
370 outl (cpu_to_le32 (data
), dev
->iobase
+ reg
);
373 static inline u32
rd_regl (const hrz_dev
* dev
, unsigned char reg
) {
374 return le32_to_cpu (inl (dev
->iobase
+ reg
));
377 static inline void wr_regw (const hrz_dev
* dev
, unsigned char reg
, u16 data
) {
378 outw (cpu_to_le16 (data
), dev
->iobase
+ reg
);
381 static inline u16
rd_regw (const hrz_dev
* dev
, unsigned char reg
) {
382 return le16_to_cpu (inw (dev
->iobase
+ reg
));
385 static inline void wrs_regb (const hrz_dev
* dev
, unsigned char reg
, void * addr
, u32 len
) {
386 outsb (dev
->iobase
+ reg
, addr
, len
);
389 static inline void rds_regb (const hrz_dev
* dev
, unsigned char reg
, void * addr
, u32 len
) {
390 insb (dev
->iobase
+ reg
, addr
, len
);
393 /* Read / Write to a given address in Horizon buffer memory.
394 Interrupts must be disabled between the address register and data
395 port accesses as these must form an atomic operation. */
396 static inline void wr_mem (const hrz_dev
* dev
, HDW
* addr
, u32 data
) {
397 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
398 wr_regl (dev
, MEM_WR_ADDR_REG_OFF
, (addr
- (HDW
*) 0) * sizeof(HDW
));
399 wr_regl (dev
, MEMORY_PORT_OFF
, data
);
402 static inline u32
rd_mem (const hrz_dev
* dev
, HDW
* addr
) {
403 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
404 wr_regl (dev
, MEM_RD_ADDR_REG_OFF
, (addr
- (HDW
*) 0) * sizeof(HDW
));
405 return rd_regl (dev
, MEMORY_PORT_OFF
);
408 static inline void wr_framer (const hrz_dev
* dev
, u32 addr
, u32 data
) {
409 wr_regl (dev
, MEM_WR_ADDR_REG_OFF
, (u32
) addr
| 0x80000000);
410 wr_regl (dev
, MEMORY_PORT_OFF
, data
);
413 static inline u32
rd_framer (const hrz_dev
* dev
, u32 addr
) {
414 wr_regl (dev
, MEM_RD_ADDR_REG_OFF
, (u32
) addr
| 0x80000000);
415 return rd_regl (dev
, MEMORY_PORT_OFF
);
418 /********** specialised access functions **********/
422 static inline void FLUSH_RX_CHANNEL (hrz_dev
* dev
, u16 channel
) {
423 wr_regw (dev
, RX_CHANNEL_PORT_OFF
, FLUSH_CHANNEL
| channel
);
427 static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev
* dev
) {
428 while (rd_regw (dev
, RX_CHANNEL_PORT_OFF
) & FLUSH_CHANNEL
)
433 static inline void SELECT_RX_CHANNEL (hrz_dev
* dev
, u16 channel
) {
434 wr_regw (dev
, RX_CHANNEL_PORT_OFF
, channel
);
438 static inline void WAIT_UPDATE_COMPLETE (hrz_dev
* dev
) {
439 while (rd_regw (dev
, RX_CHANNEL_PORT_OFF
) & RX_CHANNEL_UPDATE_IN_PROGRESS
)
446 static inline void SELECT_TX_CHANNEL (hrz_dev
* dev
, u16 tx_channel
) {
447 wr_regl (dev
, TX_CHANNEL_PORT_OFF
, tx_channel
);
451 /* Update or query one configuration parameter of a particular channel. */
453 static inline void update_tx_channel_config (hrz_dev
* dev
, short chan
, u8 mode
, u16 value
) {
454 wr_regw (dev
, TX_CHANNEL_CONFIG_COMMAND_OFF
,
455 chan
* TX_CHANNEL_CONFIG_MULT
| mode
);
456 wr_regw (dev
, TX_CHANNEL_CONFIG_DATA_OFF
, value
);
460 static inline u16
query_tx_channel_config (hrz_dev
* dev
, short chan
, u8 mode
) {
461 wr_regw (dev
, TX_CHANNEL_CONFIG_COMMAND_OFF
,
462 chan
* TX_CHANNEL_CONFIG_MULT
| mode
);
463 return rd_regw (dev
, TX_CHANNEL_CONFIG_DATA_OFF
);
466 /********** dump functions **********/
468 static inline void dump_skb (char * prefix
, unsigned int vc
, struct sk_buff
* skb
) {
471 unsigned char * data
= skb
->data
;
472 PRINTDB (DBG_DATA
, "%s(%u) ", prefix
, vc
);
473 for (i
=0; i
<skb
->len
&& i
< 256;i
++)
474 PRINTDM (DBG_DATA
, "%02x ", data
[i
]);
475 PRINTDE (DBG_DATA
,"");
484 static inline void dump_regs (hrz_dev
* dev
) {
486 PRINTD (DBG_REGS
, "CONTROL 0: %#x", rd_regl (dev
, CONTROL_0_REG
));
487 PRINTD (DBG_REGS
, "RX CONFIG: %#x", rd_regw (dev
, RX_CONFIG_OFF
));
488 PRINTD (DBG_REGS
, "TX CONFIG: %#x", rd_regw (dev
, TX_CONFIG_OFF
));
489 PRINTD (DBG_REGS
, "TX STATUS: %#x", rd_regw (dev
, TX_STATUS_OFF
));
490 PRINTD (DBG_REGS
, "IRQ ENBLE: %#x", rd_regl (dev
, INT_ENABLE_REG_OFF
));
491 PRINTD (DBG_REGS
, "IRQ SORCE: %#x", rd_regl (dev
, INT_SOURCE_REG_OFF
));
498 static inline void dump_framer (hrz_dev
* dev
) {
501 PRINTDB (DBG_REGS
, "framer registers:");
502 for (i
= 0; i
< 0x10; ++i
)
503 PRINTDM (DBG_REGS
, " %02x", rd_framer (dev
, i
));
504 PRINTDE (DBG_REGS
,"");
511 /********** VPI/VCI <-> (RX) channel conversions **********/
513 /* RX channels are 10 bit integers, these fns are quite paranoid */
515 static inline int channel_to_vpivci (const u16 channel
, short * vpi
, int * vci
) {
516 unsigned short vci_bits
= 10 - vpi_bits
;
517 if ((channel
& RX_CHANNEL_MASK
) == channel
) {
518 *vci
= channel
& ((~0)<<vci_bits
);
519 *vpi
= channel
>> vci_bits
;
520 return channel
? 0 : -EINVAL
;
525 static inline int vpivci_to_channel (u16
* channel
, const short vpi
, const int vci
) {
526 unsigned short vci_bits
= 10 - vpi_bits
;
527 if (0 <= vpi
&& vpi
< 1<<vpi_bits
&& 0 <= vci
&& vci
< 1<<vci_bits
) {
528 *channel
= vpi
<<vci_bits
| vci
;
529 return *channel
? 0 : -EINVAL
;
534 /********** decode RX queue entries **********/
536 static inline u16
rx_q_entry_to_length (u32 x
) {
537 return x
& RX_Q_ENTRY_LENGTH_MASK
;
540 static inline u16
rx_q_entry_to_rx_channel (u32 x
) {
541 return (x
>>RX_Q_ENTRY_CHANNEL_SHIFT
) & RX_CHANNEL_MASK
;
544 /* Cell Transmit Rate Values
546 * the cell transmit rate (cells per sec) can be set to a variety of
547 * different values by specifying two parameters: a timer preload from
548 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
549 * an exponent from 0 to 14; the special value 15 disables the timer).
551 * cellrate = baserate / (preload * 2^divider)
553 * The maximum cell rate that can be specified is therefore just the
554 * base rate. Halving the preload is equivalent to adding 1 to the
555 * divider and so values 1 to 8 of the preload are redundant except
556 * in the case of a maximal divider (14).
558 * Given a desired cell rate, an algorithm to determine the preload
561 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
562 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
563 * if x <= 16 then set p = x, d = 0 (high rates), done
564 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
565 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
566 * we find the range (n will be between 1 and 14), set d = n
567 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
569 * The algorithm used below is a minor variant of the above.
571 * The base rate is derived from the oscillator frequency (Hz) using a
574 * baserate = freq / 32 in the case of some Unknown Card
575 * baserate = freq / 8 in the case of the Horizon 25
576 * baserate = freq / 8 in the case of the Horizon Ultra 155
578 * The Horizon cards have oscillators and base rates as follows:
580 * Card Oscillator Base Rate
581 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
582 * Horizon 25 32 MHz 4 MHz
583 * Horizon Ultra 155 40 MHz 5 MHz
585 * The following defines give the base rates in Hz. These were
586 * previously a factor of 100 larger, no doubt someone was using
590 #define BR_UKN 1031250l
591 #define BR_HRZ 4000000l
592 #define BR_ULT 5000000l
598 // p ranges from 1 to a power of 2
601 static int make_rate (const hrz_dev
* dev
, u32 c
, rounding r
,
602 u16
* bits
, unsigned int * actual
) {
604 // note: rounding the rate down means rounding 'p' up
606 const unsigned long br
= test_bit (ultra
, (hrz_flags
*) &dev
->flags
) ?
612 // local fn to build the timer bits
615 if (div
> CR_MAXD
|| (!pre
) || pre
> 1<<CR_MAXPEXP
) {
616 PRINTD (DBG_QOS
, "set_cr internal failure: d=%u p=%u",
621 *bits
= (div
<<CLOCK_SELECT_SHIFT
) | (pre
-1);
623 *actual
= (br
+ (pre
<<div
) - 1) / (pre
<<div
);
624 PRINTD (DBG_QOS
, "actual rate: %u", *actual
);
630 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
631 // the tests below. We could think harder about exact possibilities
634 unsigned long br_man
= br
;
635 unsigned int br_exp
= 0;
637 PRINTD (DBG_QOS
|DBG_FLOW
, "make_rate b=%lu, c=%u, %s", br
, c
,
638 (r
== round_up
) ? "up" : (r
== round_down
) ? "down" : "nearest");
642 PRINTD (DBG_QOS
|DBG_ERR
, "zero rate is not allowed!");
646 while (br_exp
< CR_MAXPEXP
+ CR_MIND
&& (br_man
% 2 == 0)) {
647 br_man
= br_man
>> 1;
650 // (br >>br_exp) <<br_exp == br and
651 // br_exp <= CR_MAXPEXP+CR_MIND
653 if (br_man
<= (c
<< (CR_MAXPEXP
+CR_MIND
-br_exp
))) {
654 // Equivalent to: B <= (c << (MAXPEXP+MIND))
655 // take care of rounding
658 pre
= (br
+(c
<<div
)-1)/(c
<<div
);
659 // but p must be non-zero
664 pre
= (br
+(c
<<div
)/2)/(c
<<div
);
665 // but p must be non-zero
671 // but p must be non-zero
676 PRINTD (DBG_QOS
, "A: p=%u, d=%u", pre
, div
);
680 // at this point we have
681 // d == MIND and (c << (MAXPEXP+MIND)) < B
682 while (div
< CR_MAXD
) {
684 if (br_man
<= (c
<< (CR_MAXPEXP
+div
-br_exp
))) {
685 // Equivalent to: B <= (c << (MAXPEXP+d))
686 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
687 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
688 // MAXP/2 < B/c2^d <= MAXP
689 // take care of rounding
692 pre
= (br
+(c
<<div
)-1)/(c
<<div
);
695 pre
= (br
+(c
<<div
)/2)/(c
<<div
);
701 PRINTD (DBG_QOS
, "B: p=%u, d=%u", pre
, div
);
705 // at this point we have
706 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
707 // but we cannot go any higher
708 // take care of rounding
718 pre
= 1 << CR_MAXPEXP
;
719 PRINTD (DBG_QOS
, "C: p=%u, d=%u", pre
, div
);
723 static int make_rate_with_tolerance (const hrz_dev
* dev
, u32 c
, rounding r
, unsigned int tol
,
724 u16
* bit_pattern
, unsigned int * actual
) {
725 unsigned int my_actual
;
727 PRINTD (DBG_QOS
|DBG_FLOW
, "make_rate_with_tolerance c=%u, %s, tol=%u",
728 c
, (r
== round_up
) ? "up" : (r
== round_down
) ? "down" : "nearest", tol
);
731 // actual rate is not returned
734 if (make_rate (dev
, c
, round_nearest
, bit_pattern
, actual
))
735 // should never happen as round_nearest always succeeds
738 if (c
- tol
<= *actual
&& *actual
<= c
+ tol
)
742 // intolerant, try rounding instead
743 return make_rate (dev
, c
, r
, bit_pattern
, actual
);
746 /********** Listen on a VC **********/
748 static int hrz_open_rx (hrz_dev
* dev
, u16 channel
) {
749 // is there any guarantee that we don't get two simulataneous
750 // identical calls of this function from different processes? yes
753 u32 channel_type
; // u16?
755 u16 buf_ptr
= RX_CHANNEL_IDLE
;
757 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[channel
];
759 PRINTD (DBG_FLOW
, "hrz_open_rx %x", channel
);
761 spin_lock_irqsave (&dev
->mem_lock
, flags
);
762 channel_type
= rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
763 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
765 // very serious error, should never occur
766 if (channel_type
!= RX_CHANNEL_DISABLED
) {
767 PRINTD (DBG_ERR
|DBG_VCC
, "RX channel for VC already open");
768 return -EBUSY
; // clean up?
771 // Give back spare buffer
772 if (dev
->noof_spare_buffers
) {
773 buf_ptr
= dev
->spare_buffers
[--dev
->noof_spare_buffers
];
774 PRINTD (DBG_VCC
, "using a spare buffer: %u", buf_ptr
);
775 // should never occur
776 if (buf_ptr
== RX_CHANNEL_DISABLED
|| buf_ptr
== RX_CHANNEL_IDLE
) {
777 // but easy to recover from
778 PRINTD (DBG_ERR
|DBG_VCC
, "bad spare buffer pointer, using IDLE");
779 buf_ptr
= RX_CHANNEL_IDLE
;
782 PRINTD (DBG_VCC
, "using IDLE buffer pointer");
785 // Channel is currently disabled so change its status to idle
787 // do we really need to save the flags again?
788 spin_lock_irqsave (&dev
->mem_lock
, flags
);
790 wr_mem (dev
, &rx_desc
->wr_buf_type
,
791 buf_ptr
| CHANNEL_TYPE_AAL5
| FIRST_CELL_OF_AAL5_FRAME
);
792 if (buf_ptr
!= RX_CHANNEL_IDLE
)
793 wr_mem (dev
, &rx_desc
->rd_buf_type
, buf_ptr
);
795 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
797 // rxer->rate = make_rate (qos->peak_cells);
799 PRINTD (DBG_FLOW
, "hrz_open_rx ok");
805 /********** change vc rate for a given vc **********/
807 static void hrz_change_vc_qos (ATM_RXER
* rxer
, MAAL_QOS
* qos
) {
808 rxer
->rate
= make_rate (qos
->peak_cells
);
812 /********** free an skb (as per ATM device driver documentation) **********/
814 static inline void hrz_kfree_skb (struct sk_buff
* skb
) {
815 if (ATM_SKB(skb
)->vcc
->pop
) {
816 ATM_SKB(skb
)->vcc
->pop (ATM_SKB(skb
)->vcc
, skb
);
818 dev_kfree_skb_any (skb
);
822 /********** cancel listen on a VC **********/
824 static void hrz_close_rx (hrz_dev
* dev
, u16 vc
) {
831 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[vc
];
835 spin_lock_irqsave (&dev
->mem_lock
, flags
);
836 value
= rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
837 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
839 if (value
== RX_CHANNEL_DISABLED
) {
840 // I suppose this could happen once we deal with _NONE traffic properly
841 PRINTD (DBG_VCC
, "closing VC: RX channel %u already disabled", vc
);
844 if (value
== RX_CHANNEL_IDLE
)
847 spin_lock_irqsave (&dev
->mem_lock
, flags
);
850 wr_mem (dev
, &rx_desc
->wr_buf_type
, RX_CHANNEL_DISABLED
);
852 if ((rd_mem (dev
, &rx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
) == RX_CHANNEL_DISABLED
)
859 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
863 WAIT_FLUSH_RX_COMPLETE(dev
);
865 // XXX Is this all really necessary? We can rely on the rx_data_av
866 // handler to discard frames that remain queued for delivery. If the
867 // worry is that immediately reopening the channel (perhaps by a
868 // different process) may cause some data to be mis-delivered then
869 // there may still be a simpler solution (such as busy-waiting on
870 // rx_busy once the channel is disabled or before a new one is
871 // opened - does this leave any holes?). Arguably setting up and
872 // tearing down the TX and RX halves of each virtual circuit could
873 // most safely be done within ?x_busy protected regions.
875 // OK, current changes are that Simon's marker is disabled and we DO
876 // look for NULL rxer elsewhere. The code here seems flush frames
877 // and then remember the last dead cell belonging to the channel
878 // just disabled - the cell gets relinked at the next vc_open.
879 // However, when all VCs are closed or only a few opened there are a
880 // handful of buffers that are unusable.
882 // Does anyone feel like documenting spare_buffers properly?
883 // Does anyone feel like fixing this in a nicer way?
885 // Flush any data which is left in the channel
887 // Change the rx channel port to something different to the RX
888 // channel we are trying to close to force Horizon to flush the rx
889 // channel read and write pointers.
891 u16 other
= vc
^(RX_CHANS
/2);
893 SELECT_RX_CHANNEL (dev
, other
);
894 WAIT_UPDATE_COMPLETE (dev
);
896 r1
= rd_mem (dev
, &rx_desc
->rd_buf_type
);
898 // Select this RX channel. Flush doesn't seem to work unless we
899 // select an RX channel before hand
901 SELECT_RX_CHANNEL (dev
, vc
);
902 WAIT_UPDATE_COMPLETE (dev
);
904 // Attempt to flush a frame on this RX channel
906 FLUSH_RX_CHANNEL (dev
, vc
);
907 WAIT_FLUSH_RX_COMPLETE (dev
);
909 // Force Horizon to flush rx channel read and write pointers as before
911 SELECT_RX_CHANNEL (dev
, other
);
912 WAIT_UPDATE_COMPLETE (dev
);
914 r2
= rd_mem (dev
, &rx_desc
->rd_buf_type
);
916 PRINTD (DBG_VCC
|DBG_RX
, "r1 = %u, r2 = %u", r1
, r2
);
919 dev
->spare_buffers
[dev
->noof_spare_buffers
++] = (u16
)r1
;
926 rx_q_entry
* wr_ptr
= &memmap
->rx_q_entries
[rd_regw (dev
, RX_QUEUE_WR_PTR_OFF
)];
927 rx_q_entry
* rd_ptr
= dev
->rx_q_entry
;
929 PRINTD (DBG_VCC
|DBG_RX
, "rd_ptr = %u, wr_ptr = %u", rd_ptr
, wr_ptr
);
931 while (rd_ptr
!= wr_ptr
) {
932 u32 x
= rd_mem (dev
, (HDW
*) rd_ptr
);
934 if (vc
== rx_q_entry_to_rx_channel (x
)) {
935 x
|= SIMONS_DODGEY_MARKER
;
937 PRINTD (DBG_RX
|DBG_VCC
|DBG_WARN
, "marking a frame as dodgey");
939 wr_mem (dev
, (HDW
*) rd_ptr
, x
);
942 if (rd_ptr
== dev
->rx_q_wrap
)
943 rd_ptr
= dev
->rx_q_reset
;
950 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
955 /********** schedule RX transfers **********/
957 // Note on tail recursion: a GCC developer said that it is not likely
958 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
959 // are sure it does as you may otherwise overflow the kernel stack.
961 // giving this fn a return value would help GCC, alledgedly
963 static void rx_schedule (hrz_dev
* dev
, int irq
) {
964 unsigned int rx_bytes
;
967 #ifndef TAILRECURSIONWORKS
969 while (pio_instead
) {
971 // bytes waiting for RX transfer
972 rx_bytes
= dev
->rx_bytes
;
976 while (rd_regl (dev
, MASTER_RX_COUNT_REG_OFF
)) {
977 PRINTD (DBG_RX
|DBG_WARN
, "RX error: other PCI Bus Master RX still in progress!");
978 if (++spin_count
> 10) {
979 PRINTD (DBG_RX
|DBG_ERR
, "spun out waiting PCI Bus Master RX completion");
980 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
981 clear_bit (rx_busy
, &dev
->flags
);
982 hrz_kfree_skb (dev
->rx_skb
);
988 // this code follows the TX code but (at the moment) there is only
989 // one region - the skb itself. I don't know if this will change,
990 // but it doesn't hurt to have the code here, disabled.
993 // start next transfer within same region
994 if (rx_bytes
<= MAX_PIO_COUNT
) {
995 PRINTD (DBG_RX
|DBG_BUS
, "(pio)");
998 if (rx_bytes
<= MAX_TRANSFER_COUNT
) {
999 PRINTD (DBG_RX
|DBG_BUS
, "(simple or last multi)");
1002 PRINTD (DBG_RX
|DBG_BUS
, "(continuing multi)");
1003 dev
->rx_bytes
= rx_bytes
- MAX_TRANSFER_COUNT
;
1004 rx_bytes
= MAX_TRANSFER_COUNT
;
1007 // rx_bytes == 0 -- we're between regions
1008 // regions remaining to transfer
1010 unsigned int rx_regions
= dev
->rx_regions
;
1012 unsigned int rx_regions
= 0;
1017 // start a new region
1018 dev
->rx_addr
= dev
->rx_iovec
->iov_base
;
1019 rx_bytes
= dev
->rx_iovec
->iov_len
;
1021 dev
->rx_regions
= rx_regions
- 1;
1023 if (rx_bytes
<= MAX_PIO_COUNT
) {
1024 PRINTD (DBG_RX
|DBG_BUS
, "(pio)");
1027 if (rx_bytes
<= MAX_TRANSFER_COUNT
) {
1028 PRINTD (DBG_RX
|DBG_BUS
, "(full region)");
1031 PRINTD (DBG_RX
|DBG_BUS
, "(start multi region)");
1032 dev
->rx_bytes
= rx_bytes
- MAX_TRANSFER_COUNT
;
1033 rx_bytes
= MAX_TRANSFER_COUNT
;
1038 // that's all folks - end of frame
1039 struct sk_buff
* skb
= dev
->rx_skb
;
1040 // dev->rx_iovec = 0;
1042 FLUSH_RX_CHANNEL (dev
, dev
->rx_channel
);
1044 dump_skb ("<<<", dev
->rx_channel
, skb
);
1046 PRINTD (DBG_RX
|DBG_SKB
, "push %p %u", skb
->data
, skb
->len
);
1049 struct atm_vcc
* vcc
= ATM_SKB(skb
)->vcc
;
1051 atomic_inc(&vcc
->stats
->rx
);
1053 // end of our responsability
1054 vcc
->push (vcc
, skb
);
1059 // note: writing RX_COUNT clears any interrupt condition
1063 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1064 rds_regb (dev
, DATA_PORT_OFF
, dev
->rx_addr
, rx_bytes
);
1066 wr_regl (dev
, MASTER_RX_ADDR_REG_OFF
, virt_to_bus (dev
->rx_addr
));
1067 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, rx_bytes
);
1069 dev
->rx_addr
+= rx_bytes
;
1072 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1073 // allow another RX thread to start
1075 clear_bit (rx_busy
, &dev
->flags
);
1076 PRINTD (DBG_RX
, "cleared rx_busy for dev %p", dev
);
1079 #ifdef TAILRECURSIONWORKS
1080 // and we all bless optimised tail calls
1082 return rx_schedule (dev
, 0);
1092 /********** handle RX bus master complete events **********/
1094 static inline void rx_bus_master_complete_handler (hrz_dev
* dev
) {
1095 if (test_bit (rx_busy
, &dev
->flags
)) {
1096 rx_schedule (dev
, 1);
1098 PRINTD (DBG_RX
|DBG_ERR
, "unexpected RX bus master completion");
1099 // clear interrupt condition on adapter
1100 wr_regl (dev
, MASTER_RX_COUNT_REG_OFF
, 0);
1105 /********** (queue to) become the next TX thread **********/
1107 static inline int tx_hold (hrz_dev
* dev
) {
1108 while (test_and_set_bit (tx_busy
, &dev
->flags
)) {
1109 PRINTD (DBG_TX
, "sleeping at tx lock %p %u", dev
, dev
->flags
);
1110 interruptible_sleep_on (&dev
->tx_queue
);
1111 PRINTD (DBG_TX
, "woken at tx lock %p %u", dev
, dev
->flags
);
1112 if (signal_pending (current
))
1115 PRINTD (DBG_TX
, "set tx_busy for dev %p", dev
);
1119 /********** allow another TX thread to start **********/
1121 static inline void tx_release (hrz_dev
* dev
) {
1122 clear_bit (tx_busy
, &dev
->flags
);
1123 PRINTD (DBG_TX
, "cleared tx_busy for dev %p", dev
);
1124 wake_up_interruptible (&dev
->tx_queue
);
1127 /********** schedule TX transfers **********/
1129 static void tx_schedule (hrz_dev
* const dev
, int irq
) {
1130 unsigned int tx_bytes
;
1132 int append_desc
= 0;
1134 int pio_instead
= 0;
1135 #ifndef TAILRECURSIONWORKS
1137 while (pio_instead
) {
1139 // bytes in current region waiting for TX transfer
1140 tx_bytes
= dev
->tx_bytes
;
1144 while (rd_regl (dev
, MASTER_TX_COUNT_REG_OFF
)) {
1145 PRINTD (DBG_TX
|DBG_WARN
, "TX error: other PCI Bus Master TX still in progress!");
1146 if (++spin_count
> 10) {
1147 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting PCI Bus Master TX completion");
1148 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1150 hrz_kfree_skb (dev
->tx_skb
);
1157 // start next transfer within same region
1158 if (!test_bit (ultra
, &dev
->flags
) || tx_bytes
<= MAX_PIO_COUNT
) {
1159 PRINTD (DBG_TX
|DBG_BUS
, "(pio)");
1162 if (tx_bytes
<= MAX_TRANSFER_COUNT
) {
1163 PRINTD (DBG_TX
|DBG_BUS
, "(simple or last multi)");
1164 if (!dev
->tx_iovec
) {
1165 // end of last region
1170 PRINTD (DBG_TX
|DBG_BUS
, "(continuing multi)");
1171 dev
->tx_bytes
= tx_bytes
- MAX_TRANSFER_COUNT
;
1172 tx_bytes
= MAX_TRANSFER_COUNT
;
1175 // tx_bytes == 0 -- we're between regions
1176 // regions remaining to transfer
1177 unsigned int tx_regions
= dev
->tx_regions
;
1180 // start a new region
1181 dev
->tx_addr
= dev
->tx_iovec
->iov_base
;
1182 tx_bytes
= dev
->tx_iovec
->iov_len
;
1184 dev
->tx_regions
= tx_regions
- 1;
1186 if (!test_bit (ultra
, &dev
->flags
) || tx_bytes
<= MAX_PIO_COUNT
) {
1187 PRINTD (DBG_TX
|DBG_BUS
, "(pio)");
1190 if (tx_bytes
<= MAX_TRANSFER_COUNT
) {
1191 PRINTD (DBG_TX
|DBG_BUS
, "(full region)");
1194 PRINTD (DBG_TX
|DBG_BUS
, "(start multi region)");
1195 dev
->tx_bytes
= tx_bytes
- MAX_TRANSFER_COUNT
;
1196 tx_bytes
= MAX_TRANSFER_COUNT
;
1200 // that's all folks - end of frame
1201 struct sk_buff
* skb
= dev
->tx_skb
;
1205 atomic_inc(&ATM_SKB(skb
)->vcc
->stats
->tx
);
1208 hrz_kfree_skb (skb
);
1212 // note: writing TX_COUNT clears any interrupt condition
1216 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1217 wrs_regb (dev
, DATA_PORT_OFF
, dev
->tx_addr
, tx_bytes
);
1219 wr_regl (dev
, TX_DESCRIPTOR_PORT_OFF
, cpu_to_be32 (dev
->tx_skb
->len
));
1221 wr_regl (dev
, MASTER_TX_ADDR_REG_OFF
, virt_to_bus (dev
->tx_addr
));
1223 wr_regl (dev
, TX_DESCRIPTOR_REG_OFF
, cpu_to_be32 (dev
->tx_skb
->len
));
1224 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
,
1226 ? tx_bytes
| MASTER_TX_AUTO_APPEND_DESC
1229 dev
->tx_addr
+= tx_bytes
;
1232 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1237 #ifdef TAILRECURSIONWORKS
1238 // and we all bless optimised tail calls
1240 return tx_schedule (dev
, 0);
1250 /********** handle TX bus master complete events **********/
1252 static inline void tx_bus_master_complete_handler (hrz_dev
* dev
) {
1253 if (test_bit (tx_busy
, &dev
->flags
)) {
1254 tx_schedule (dev
, 1);
1256 PRINTD (DBG_TX
|DBG_ERR
, "unexpected TX bus master completion");
1257 // clear interrupt condition on adapter
1258 wr_regl (dev
, MASTER_TX_COUNT_REG_OFF
, 0);
1263 /********** move RX Q pointer to next item in circular buffer **********/
1265 // called only from IRQ sub-handler
1266 static inline u32
rx_queue_entry_next (hrz_dev
* dev
) {
1268 spin_lock (&dev
->mem_lock
);
1269 rx_queue_entry
= rd_mem (dev
, &dev
->rx_q_entry
->entry
);
1270 if (dev
->rx_q_entry
== dev
->rx_q_wrap
)
1271 dev
->rx_q_entry
= dev
->rx_q_reset
;
1274 wr_regw (dev
, RX_QUEUE_RD_PTR_OFF
, dev
->rx_q_entry
- dev
->rx_q_reset
);
1275 spin_unlock (&dev
->mem_lock
);
1276 return rx_queue_entry
;
1279 /********** handle RX disabled by device **********/
1281 static inline void rx_disabled_handler (hrz_dev
* dev
) {
1282 wr_regw (dev
, RX_CONFIG_OFF
, rd_regw (dev
, RX_CONFIG_OFF
) | RX_ENABLE
);
1284 PRINTK (KERN_WARNING
, "RX was disabled!");
1287 /********** handle RX data received by device **********/
1289 // called from IRQ handler
1290 static inline void rx_data_av_handler (hrz_dev
* dev
) {
1292 u32 rx_queue_entry_flags
;
1296 PRINTD (DBG_FLOW
, "hrz_data_av_handler");
1298 // try to grab rx lock (not possible during RX bus mastering)
1299 if (test_and_set_bit (rx_busy
, &dev
->flags
)) {
1300 PRINTD (DBG_RX
, "locked out of rx lock");
1303 PRINTD (DBG_RX
, "set rx_busy for dev %p", dev
);
1304 // lock is cleared if we fail now, o/w after bus master completion
1306 YELLOW_LED_OFF(dev
);
1308 rx_queue_entry
= rx_queue_entry_next (dev
);
1310 rx_len
= rx_q_entry_to_length (rx_queue_entry
);
1311 rx_channel
= rx_q_entry_to_rx_channel (rx_queue_entry
);
1313 WAIT_FLUSH_RX_COMPLETE (dev
);
1315 SELECT_RX_CHANNEL (dev
, rx_channel
);
1317 PRINTD (DBG_RX
, "rx_queue_entry is: %#x", rx_queue_entry
);
1318 rx_queue_entry_flags
= rx_queue_entry
& (RX_CRC_32_OK
|RX_COMPLETE_FRAME
|SIMONS_DODGEY_MARKER
);
1321 // (at least) bus-mastering breaks if we try to handle a
1322 // zero-length frame, besides AAL5 does not support them
1323 PRINTK (KERN_ERR
, "zero-length frame!");
1324 rx_queue_entry_flags
&= ~RX_COMPLETE_FRAME
;
1327 if (rx_queue_entry_flags
& SIMONS_DODGEY_MARKER
) {
1328 PRINTD (DBG_RX
|DBG_ERR
, "Simon's marker detected!");
1330 if (rx_queue_entry_flags
== (RX_CRC_32_OK
| RX_COMPLETE_FRAME
)) {
1331 struct atm_vcc
* atm_vcc
;
1333 PRINTD (DBG_RX
, "got a frame on rx_channel %x len %u", rx_channel
, rx_len
);
1335 atm_vcc
= dev
->rxer
[rx_channel
];
1336 // if no vcc is assigned to this channel, we should drop the frame
1337 // (is this what SIMONS etc. was trying to achieve?)
1341 if (atm_vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
1343 if (rx_len
<= atm_vcc
->qos
.rxtp
.max_sdu
) {
1345 struct sk_buff
* skb
= atm_alloc_charge (atm_vcc
, rx_len
, GFP_ATOMIC
);
1347 // remember this so we can push it later
1349 // remember this so we can flush it later
1350 dev
->rx_channel
= rx_channel
;
1352 // prepare socket buffer
1353 skb_put (skb
, rx_len
);
1354 ATM_SKB(skb
)->vcc
= atm_vcc
;
1357 // dev->rx_regions = 0;
1358 // dev->rx_iovec = 0;
1359 dev
->rx_bytes
= rx_len
;
1360 dev
->rx_addr
= skb
->data
;
1361 PRINTD (DBG_RX
, "RX start simple transfer (addr %p, len %d)",
1365 rx_schedule (dev
, 0);
1369 PRINTD (DBG_SKB
|DBG_WARN
, "failed to get skb");
1373 PRINTK (KERN_INFO
, "frame received on TX-only VC %x", rx_channel
);
1374 // do we count this?
1378 PRINTK (KERN_WARNING
, "dropped over-size frame");
1379 // do we count this?
1383 PRINTD (DBG_WARN
|DBG_VCC
|DBG_RX
, "no VCC for this frame (VC closed)");
1384 // do we count this?
1388 // Wait update complete ? SPONG
1394 FLUSH_RX_CHANNEL (dev
,rx_channel
);
1395 clear_bit (rx_busy
, &dev
->flags
);
1400 /********** interrupt handler **********/
1402 static void interrupt_handler (int irq
, void * dev_id
, struct pt_regs
* pt_regs
) {
1403 hrz_dev
* dev
= hrz_devs
;
1405 unsigned int irq_ok
;
1408 PRINTD (DBG_FLOW
, "interrupt_handler: %p", dev_id
);
1411 PRINTD (DBG_IRQ
|DBG_ERR
, "irq with NULL dev_id: %d", irq
);
1414 // Did one of our cards generate the interrupt?
1421 PRINTD (DBG_IRQ
, "irq not for me: %d", irq
);
1424 if (irq
!= dev
->irq
) {
1425 PRINTD (DBG_IRQ
|DBG_ERR
, "irq mismatch: %d", irq
);
1429 // definitely for us
1431 while ((int_source
= rd_regl (dev
, INT_SOURCE_REG_OFF
)
1432 & INTERESTING_INTERRUPTS
)) {
1433 // In the interests of fairness, the (inline) handlers below are
1434 // called in sequence and without immediate return to the head of
1435 // the while loop. This is only of issue for slow hosts (or when
1436 // debugging messages are on). Really slow hosts may find a fast
1437 // sender keeps them permanently in the IRQ handler. :(
1439 // (only an issue for slow hosts) RX completion goes before
1440 // rx_data_av as the former implies rx_busy and so the latter
1441 // would just abort. If it reschedules another transfer
1442 // (continuing the same frame) then it will not clear rx_busy.
1444 // (only an issue for slow hosts) TX completion goes before RX
1445 // data available as it is a much shorter routine - there is the
1446 // chance that any further transfers it schedules will be complete
1447 // by the time of the return to the head of the while loop
1449 if (int_source
& RX_BUS_MASTER_COMPLETE
) {
1451 PRINTD (DBG_IRQ
|DBG_BUS
|DBG_RX
, "rx_bus_master_complete asserted");
1452 rx_bus_master_complete_handler (dev
);
1454 if (int_source
& TX_BUS_MASTER_COMPLETE
) {
1456 PRINTD (DBG_IRQ
|DBG_BUS
|DBG_TX
, "tx_bus_master_complete asserted");
1457 tx_bus_master_complete_handler (dev
);
1459 if (int_source
& RX_DATA_AV
) {
1461 PRINTD (DBG_IRQ
|DBG_RX
, "rx_data_av asserted");
1462 rx_data_av_handler (dev
);
1466 PRINTD (DBG_IRQ
, "work done: %u", irq_ok
);
1468 PRINTD (DBG_IRQ
|DBG_WARN
, "spurious interrupt source: %#x", int_source
);
1471 PRINTD (DBG_IRQ
|DBG_FLOW
, "interrupt_handler done: %p", dev_id
);
1474 /********** housekeeping **********/
1476 static void set_timer (struct timer_list
* timer
, unsigned int delay
) {
1477 timer
->expires
= jiffies
+ delay
;
1482 static void do_housekeeping (unsigned long arg
) {
1483 // just stats at the moment
1484 hrz_dev
* dev
= hrz_devs
;
1486 // data is set to zero at module unload
1487 if (housekeeping
.data
) {
1489 // collect device-specific (not driver/atm-linux) stats here
1490 dev
->tx_cell_count
+= rd_regw (dev
, TX_CELL_COUNT_OFF
);
1491 dev
->rx_cell_count
+= rd_regw (dev
, RX_CELL_COUNT_OFF
);
1492 dev
->hec_error_count
+= rd_regw (dev
, HEC_ERROR_COUNT_OFF
);
1493 dev
->unassigned_cell_count
+= rd_regw (dev
, UNASSIGNED_CELL_COUNT_OFF
);
1496 set_timer (&housekeeping
, HZ
/10);
1501 /********** find an idle channel for TX and set it up **********/
1503 // called with tx_busy set
1504 static inline short setup_idle_tx_channel (hrz_dev
* dev
, hrz_vcc
* vcc
) {
1505 unsigned short idle_channels
;
1506 short tx_channel
= -1;
1507 unsigned int spin_count
;
1508 PRINTD (DBG_FLOW
|DBG_TX
, "setup_idle_tx_channel %p", dev
);
1510 // better would be to fail immediately, the caller can then decide whether
1511 // to wait or drop (depending on whether this is UBR etc.)
1513 while (!(idle_channels
= rd_regw (dev
, TX_STATUS_OFF
) & IDLE_CHANNELS_MASK
)) {
1514 PRINTD (DBG_TX
|DBG_WARN
, "waiting for idle TX channel");
1516 if (++spin_count
> 100) {
1517 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting for idle TX channel");
1522 // got an idle channel
1524 // tx_idle ensures we look for idle channels in RR order
1525 int chan
= dev
->tx_idle
;
1528 while (keep_going
) {
1529 if (idle_channels
& (1<<chan
)) {
1534 if (chan
== TX_CHANS
)
1538 dev
->tx_idle
= chan
;
1541 // set up the channel we found
1543 // Initialise the cell header in the transmit channel descriptor
1544 // a.k.a. prepare the channel and remember that we have done so.
1546 tx_ch_desc
* tx_desc
= &memmap
->tx_descs
[tx_channel
];
1549 u16 channel
= vcc
->channel
;
1551 unsigned long flags
;
1552 spin_lock_irqsave (&dev
->mem_lock
, flags
);
1554 // Update the transmit channel record.
1555 dev
->tx_channel_record
[tx_channel
] = channel
;
1558 update_tx_channel_config (dev
, tx_channel
, RATE_TYPE_ACCESS
,
1561 // Update the PCR counter preload value etc.
1562 update_tx_channel_config (dev
, tx_channel
, PCR_TIMER_ACCESS
,
1566 if (vcc
->tx_xbr_bits
== VBR_RATE_TYPE
) {
1568 update_tx_channel_config (dev
, tx_channel
, SCR_TIMER_ACCESS
,
1572 update_tx_channel_config (dev
, tx_channel
, BUCKET_CAPACITY_ACCESS
,
1573 vcc
->tx_bucket_bits
);
1576 update_tx_channel_config (dev
, tx_channel
, BUCKET_FULLNESS_ACCESS
,
1577 vcc
->tx_bucket_bits
);
1581 // Initialise the read and write buffer pointers
1582 rd_ptr
= rd_mem (dev
, &tx_desc
->rd_buf_type
) & BUFFER_PTR_MASK
;
1583 wr_ptr
= rd_mem (dev
, &tx_desc
->wr_buf_type
) & BUFFER_PTR_MASK
;
1585 // idle TX channels should have identical pointers
1586 if (rd_ptr
!= wr_ptr
) {
1587 PRINTD (DBG_TX
|DBG_ERR
, "TX buffer pointers are broken!");
1588 // spin_unlock... return -E...
1589 // I wonder if gcc would get rid of one of the pointer aliases
1591 PRINTD (DBG_TX
, "TX buffer pointers are: rd %x, wr %x.",
1596 PRINTD (DBG_QOS
|DBG_TX
, "tx_channel: aal0");
1597 rd_ptr
|= CHANNEL_TYPE_RAW_CELLS
;
1598 wr_ptr
|= CHANNEL_TYPE_RAW_CELLS
;
1601 PRINTD (DBG_QOS
|DBG_TX
, "tx_channel: aal34");
1602 rd_ptr
|= CHANNEL_TYPE_AAL3_4
;
1603 wr_ptr
|= CHANNEL_TYPE_AAL3_4
;
1606 rd_ptr
|= CHANNEL_TYPE_AAL5
;
1607 wr_ptr
|= CHANNEL_TYPE_AAL5
;
1608 // Initialise the CRC
1609 wr_mem (dev
, &tx_desc
->partial_crc
, INITIAL_CRC
);
1613 wr_mem (dev
, &tx_desc
->rd_buf_type
, rd_ptr
);
1614 wr_mem (dev
, &tx_desc
->wr_buf_type
, wr_ptr
);
1616 // Write the Cell Header
1617 // Payload Type, CLP and GFC would go here if non-zero
1618 wr_mem (dev
, &tx_desc
->cell_header
, channel
);
1620 spin_unlock_irqrestore (&dev
->mem_lock
, flags
);
1626 /********** send a frame **********/
1628 static int hrz_send (struct atm_vcc
* atm_vcc
, struct sk_buff
* skb
) {
1629 unsigned int spin_count
;
1631 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
1632 hrz_vcc
* vcc
= HRZ_VCC(atm_vcc
);
1633 u16 channel
= vcc
->channel
;
1635 u32 buffers_required
;
1637 /* signed for error return */
1640 PRINTD (DBG_FLOW
|DBG_TX
, "hrz_send vc %x data %p len %u",
1641 channel
, skb
->data
, skb
->len
);
1643 dump_skb (">>>", channel
, skb
);
1645 if (atm_vcc
->qos
.txtp
.traffic_class
== ATM_NONE
) {
1646 PRINTK (KERN_ERR
, "attempt to send on RX-only VC %x", channel
);
1647 hrz_kfree_skb (skb
);
1651 // don't understand this
1652 ATM_SKB(skb
)->vcc
= atm_vcc
;
1654 if (skb
->len
> atm_vcc
->qos
.txtp
.max_sdu
) {
1655 PRINTK (KERN_ERR
, "sk_buff length greater than agreed max_sdu, dropping...");
1656 hrz_kfree_skb (skb
);
1661 PRINTD (DBG_ERR
|DBG_TX
, "attempt to transmit on zero (rx_)channel");
1662 hrz_kfree_skb (skb
);
1668 // where would be a better place for this? housekeeping?
1670 pci_read_config_word (dev
->pci_dev
, PCI_STATUS
, &status
);
1671 if (status
& PCI_STATUS_REC_MASTER_ABORT
) {
1672 PRINTD (DBG_BUS
|DBG_ERR
, "Clearing PCI Master Abort (and cleaning up)");
1673 status
&= ~PCI_STATUS_REC_MASTER_ABORT
;
1674 pci_write_config_word (dev
->pci_dev
, PCI_STATUS
, status
);
1675 if (test_bit (tx_busy
, &dev
->flags
)) {
1676 hrz_kfree_skb (dev
->tx_skb
);
1683 #ifdef DEBUG_HORIZON
1685 if (channel
== 1023) {
1687 unsigned short d
= 0;
1688 char * s
= skb
->data
;
1690 for (i
= 0; i
< 4; ++i
) {
1691 d
= (d
<<4) | ((*s
<= '9') ? (*s
- '0') : (*s
- 'a' + 10));
1694 PRINTK (KERN_INFO
, "debug bitmap is now %hx", debug
= d
);
1699 // wait until TX is free and grab lock
1700 if (tx_hold (dev
)) {
1701 hrz_kfree_skb (skb
);
1702 return -ERESTARTSYS
;
1705 // Wait for enough space to be available in transmit buffer memory.
1707 // should be number of cells needed + 2 (according to hardware docs)
1708 // = ((framelen+8)+47) / 48 + 2
1709 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1710 buffers_required
= (skb
->len
+(ATM_AAL5_TRAILER
-1)) / ATM_CELL_PAYLOAD
+ 3;
1712 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1714 while ((free_buffers
= rd_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
)) < buffers_required
) {
1715 PRINTD (DBG_TX
, "waiting for free TX buffers, got %d of %d",
1716 free_buffers
, buffers_required
);
1717 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1719 // what happens if we kill (current_pid, SIGKILL) ?
1721 if (++spin_count
> 1000) {
1722 PRINTD (DBG_TX
|DBG_ERR
, "spun out waiting for tx buffers, got %d of %d",
1723 free_buffers
, buffers_required
);
1725 hrz_kfree_skb (skb
);
1726 return -ERESTARTSYS
;
1730 // Select a channel to transmit the frame on.
1731 if (channel
== dev
->last_vc
) {
1732 PRINTD (DBG_TX
, "last vc hack: hit");
1733 tx_channel
= dev
->tx_last
;
1735 PRINTD (DBG_TX
, "last vc hack: miss");
1736 // Are we currently transmitting this VC on one of the channels?
1737 for (tx_channel
= 0; tx_channel
< TX_CHANS
; ++tx_channel
)
1738 if (dev
->tx_channel_record
[tx_channel
] == channel
) {
1739 PRINTD (DBG_TX
, "vc already on channel: hit");
1742 if (tx_channel
== TX_CHANS
) {
1743 PRINTD (DBG_TX
, "vc already on channel: miss");
1744 // Find and set up an idle channel.
1745 tx_channel
= setup_idle_tx_channel (dev
, vcc
);
1746 if (tx_channel
< 0) {
1747 PRINTD (DBG_TX
|DBG_ERR
, "failed to get channel");
1753 PRINTD (DBG_TX
, "got channel");
1754 SELECT_TX_CHANNEL(dev
, tx_channel
);
1756 dev
->last_vc
= channel
;
1757 dev
->tx_last
= tx_channel
;
1760 PRINTD (DBG_TX
, "using channel %u", tx_channel
);
1762 YELLOW_LED_OFF(dev
);
1764 // TX start transfer
1767 unsigned int tx_len
= skb
->len
;
1768 unsigned int tx_iovcnt
= ATM_SKB(skb
)->iovcnt
;
1769 // remember this so we can free it later
1773 // scatter gather transfer
1774 dev
->tx_regions
= tx_iovcnt
;
1775 dev
->tx_iovec
= (struct iovec
*) skb
->data
;
1777 PRINTD (DBG_TX
|DBG_BUS
, "TX start scatter-gather transfer (iovec %p, len %d)",
1781 dev
->tx_regions
= 0;
1783 dev
->tx_bytes
= tx_len
;
1784 dev
->tx_addr
= skb
->data
;
1785 PRINTD (DBG_TX
|DBG_BUS
, "TX start simple transfer (addr %p, len %d)",
1789 // and do the business
1790 tx_schedule (dev
, 0);
1797 /********** reset a card **********/
1799 static void __init
hrz_reset (const hrz_dev
* dev
) {
1800 u32 control_0_reg
= rd_regl (dev
, CONTROL_0_REG
);
1802 // why not set RESET_HORIZON to one and wait for the card to
1803 // reassert that bit as zero? Like so:
1804 control_0_reg
= control_0_reg
& RESET_HORIZON
;
1805 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
);
1806 while (control_0_reg
& RESET_HORIZON
)
1807 control_0_reg
= rd_regl (dev
, CONTROL_0_REG
);
1809 // old reset code retained:
1810 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
|
1811 RESET_ATM
| RESET_RX
| RESET_TX
| RESET_HOST
);
1812 // just guessing here
1815 wr_regl (dev
, CONTROL_0_REG
, control_0_reg
);
1818 /********** read the burnt in address **********/
1820 static u16 __init
read_bia (const hrz_dev
* dev
, u16 addr
) {
1822 u32 ctrl
= rd_regl (dev
, CONTROL_0_REG
);
1824 void WRITE_IT_WAIT (void) {
1825 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
1829 void CLOCK_IT (void) {
1830 // DI must be valid around rising SK edge
1831 ctrl
&= ~SEEPROM_SK
;
1837 const unsigned int addr_bits
= 6;
1838 const unsigned int data_bits
= 16;
1844 ctrl
&= ~(SEEPROM_CS
| SEEPROM_SK
| SEEPROM_DI
);
1847 // wake Serial EEPROM and send 110 (READ) command
1848 ctrl
|= (SEEPROM_CS
| SEEPROM_DI
);
1854 ctrl
&= ~SEEPROM_DI
;
1857 for (i
=0; i
<addr_bits
; i
++) {
1858 if (addr
& (1 << (addr_bits
-1)))
1861 ctrl
&= ~SEEPROM_DI
;
1868 // we could check that we have DO = 0 here
1869 ctrl
&= ~SEEPROM_DI
;
1872 for (i
=0;i
<data_bits
;i
++) {
1877 if (rd_regl (dev
, CONTROL_0_REG
) & SEEPROM_DO
)
1878 res
|= (1 << (data_bits
-1));
1881 ctrl
&= ~(SEEPROM_SK
| SEEPROM_CS
);
1887 /********** initialise a card **********/
1889 static int __init
hrz_init (hrz_dev
* dev
) {
1903 ctrl
= rd_regl (dev
, CONTROL_0_REG
);
1904 PRINTD (DBG_INFO
, "ctrl0reg is %#x", ctrl
);
1905 onefivefive
= ctrl
& ATM_LAYER_STATUS
;
1908 printk (DEV_LABEL
": Horizon Ultra (at 155.52 MBps)");
1910 printk (DEV_LABEL
": Horizon (at 25 MBps)");
1913 // Reset the card to get everything in a known state
1918 // Clear all the buffer memory
1920 printk (" clearing memory");
1922 for (mem
= (HDW
*) memmap
; mem
< (HDW
*) (memmap
+ 1); ++mem
)
1923 wr_mem (dev
, mem
, 0);
1925 printk (" tx channels");
1927 // All transmit eight channels are set up as AAL5 ABR channels with
1928 // a 16us cell spacing. Why?
1930 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1931 // buffer at 110h etc.
1933 for (chan
= 0; chan
< TX_CHANS
; ++chan
) {
1934 tx_ch_desc
* tx_desc
= &memmap
->tx_descs
[chan
];
1935 cell_buf
* buf
= &memmap
->inittxbufs
[chan
];
1937 // initialise the read and write buffer pointers
1938 wr_mem (dev
, &tx_desc
->rd_buf_type
, BUF_PTR(buf
));
1939 wr_mem (dev
, &tx_desc
->wr_buf_type
, BUF_PTR(buf
));
1941 // set the status of the initial buffers to empty
1942 wr_mem (dev
, &buf
->next
, BUFF_STATUS_EMPTY
);
1945 // Use space bufn3 at the moment for tx buffers
1947 printk (" tx buffers");
1949 tx_desc
= memmap
->bufn3
;
1951 wr_mem (dev
, &memmap
->txfreebufstart
.next
, BUF_PTR(tx_desc
) | BUFF_STATUS_EMPTY
);
1953 for (buff_count
= 0; buff_count
< BUFN3_SIZE
-1; buff_count
++) {
1954 wr_mem (dev
, &tx_desc
->next
, BUF_PTR(tx_desc
+1) | BUFF_STATUS_EMPTY
);
1958 wr_mem (dev
, &tx_desc
->next
, BUF_PTR(&memmap
->txfreebufend
) | BUFF_STATUS_EMPTY
);
1960 // Initialise the transmit free buffer count
1961 wr_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
, BUFN3_SIZE
);
1963 printk (" rx channels");
1965 // Initialise all of the receive channels to be AAL5 disabled with
1966 // an interrupt threshold of 0
1968 for (chan
= 0; chan
< RX_CHANS
; ++chan
) {
1969 rx_ch_desc
* rx_desc
= &memmap
->rx_descs
[chan
];
1971 wr_mem (dev
, &rx_desc
->wr_buf_type
, CHANNEL_TYPE_AAL5
| RX_CHANNEL_DISABLED
);
1974 printk (" rx buffers");
1976 // Use space bufn4 at the moment for rx buffers
1978 rx_desc
= memmap
->bufn4
;
1980 wr_mem (dev
, &memmap
->rxfreebufstart
.next
, BUF_PTR(rx_desc
) | BUFF_STATUS_EMPTY
);
1982 for (buff_count
= 0; buff_count
< BUFN4_SIZE
-1; buff_count
++) {
1983 wr_mem (dev
, &rx_desc
->next
, BUF_PTR(rx_desc
+1) | BUFF_STATUS_EMPTY
);
1988 wr_mem (dev
, &rx_desc
->next
, BUF_PTR(&memmap
->rxfreebufend
) | BUFF_STATUS_EMPTY
);
1990 // Initialise the receive free buffer count
1991 wr_regw (dev
, RX_FREE_BUFFER_COUNT_OFF
, BUFN4_SIZE
);
1993 // Initialize Horizons registers
1996 wr_regw (dev
, TX_CONFIG_OFF
,
1997 ABR_ROUND_ROBIN
| TX_NORMAL_OPERATION
| DRVR_DRVRBAR_ENABLE
);
1999 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
2000 wr_regw (dev
, RX_CONFIG_OFF
,
2001 DISCARD_UNUSED_VPI_VCI_BITS_SET
| NON_USER_CELLS_IN_ONE_CHANNEL
| vpi_bits
);
2004 wr_regw (dev
, RX_LINE_CONFIG_OFF
,
2005 LOCK_DETECT_ENABLE
| FREQUENCY_DETECT_ENABLE
| GXTALOUT_SELECT_DIV4
);
2007 // Set the max AAL5 cell count to be just enough to contain the
2008 // largest AAL5 frame that the user wants to receive
2009 wr_regw (dev
, MAX_AAL5_CELL_COUNT_OFF
,
2010 (max_rx_size
+ ATM_AAL5_TRAILER
+ ATM_CELL_PAYLOAD
- 1) / ATM_CELL_PAYLOAD
);
2013 wr_regw (dev
, RX_CONFIG_OFF
, rd_regw (dev
, RX_CONFIG_OFF
) | RX_ENABLE
);
2015 printk (" control");
2017 // Drive the OE of the LEDs then turn the green LED on
2018 ctrl
|= GREEN_LED_OE
| YELLOW_LED_OE
| GREEN_LED
| YELLOW_LED
;
2019 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
2021 // Test for a 155-capable card
2024 // Select 155 mode... make this a choice (or: how do we detect
2025 // external line speed and switch?)
2026 ctrl
|= ATM_LAYER_SELECT
;
2027 wr_regl (dev
, CONTROL_0_REG
, ctrl
);
2029 // test SUNI-lite vs SAMBA
2031 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2032 // they will always be zero for the SAMBA. Ha! Bloody hardware
2033 // engineers. It'll never work.
2035 if (rd_framer (dev
, 0) & 0x00f0) {
2039 // Reset, just in case
2040 wr_framer (dev
, 0x00, 0x0080);
2041 wr_framer (dev
, 0x00, 0x0000);
2043 // Configure transmit FIFO
2044 wr_framer (dev
, 0x63, rd_framer (dev
, 0x63) | 0x0002);
2046 // Set line timed mode
2047 wr_framer (dev
, 0x05, rd_framer (dev
, 0x05) | 0x0001);
2052 // Reset, just in case
2053 wr_framer (dev
, 0, rd_framer (dev
, 0) | 0x0001);
2054 wr_framer (dev
, 0, rd_framer (dev
, 0) &~ 0x0001);
2056 // Turn off diagnostic loopback and enable line-timed mode
2057 wr_framer (dev
, 0, 0x0002);
2059 // Turn on transmit outputs
2060 wr_framer (dev
, 2, 0x0B80);
2064 ctrl
&= ~ATM_LAYER_SELECT
;
2080 u8
* esi
= dev
->atm_dev
->esi
;
2082 // in the card I have, EEPROM
2083 // addresses 0, 1, 2 contain 0
2084 // addresess 5, 6 etc. contain ffff
2085 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2086 // the read_bia routine gets the BIA in Ethernet bit order
2088 for (i
=0; i
< ESI_LEN
; ++i
) {
2090 b
= read_bia (dev
, i
/2 + 2);
2094 printk ("%02x", esi
[i
]);
2098 // Enable RX_Q and ?X_COMPLETE interrupts only
2099 wr_regl (dev
, INT_ENABLE_REG_OFF
, INTERESTING_INTERRUPTS
);
2107 /********** check max_sdu **********/
2109 static int check_max_sdu (hrz_aal aal
, struct atm_trafprm
* tp
, unsigned int max_frame_size
) {
2110 PRINTD (DBG_FLOW
|DBG_QOS
, "check_max_sdu");
2114 if (!(tp
->max_sdu
)) {
2115 PRINTD (DBG_QOS
, "defaulting max_sdu");
2116 tp
->max_sdu
= ATM_AAL0_SDU
;
2117 } else if (tp
->max_sdu
!= ATM_AAL0_SDU
) {
2118 PRINTD (DBG_QOS
|DBG_ERR
, "rejecting max_sdu");
2123 if (tp
->max_sdu
== 0 || tp
->max_sdu
> ATM_MAX_AAL34_PDU
) {
2124 PRINTD (DBG_QOS
, "%sing max_sdu", tp
->max_sdu
? "capp" : "default");
2125 tp
->max_sdu
= ATM_MAX_AAL34_PDU
;
2129 if (tp
->max_sdu
== 0 || tp
->max_sdu
> max_frame_size
) {
2130 PRINTD (DBG_QOS
, "%sing max_sdu", tp
->max_sdu
? "capp" : "default");
2131 tp
->max_sdu
= max_frame_size
;
2138 /********** check pcr **********/
2140 // something like this should be part of ATM Linux
2141 static int atm_pcr_check (struct atm_trafprm
* tp
, unsigned int pcr
) {
2142 // we are assuming non-UBR, and non-special values of pcr
2143 if (tp
->min_pcr
== ATM_MAX_PCR
)
2144 PRINTD (DBG_QOS
, "luser gave min_pcr = ATM_MAX_PCR");
2145 else if (tp
->min_pcr
< 0)
2146 PRINTD (DBG_QOS
, "luser gave negative min_pcr");
2147 else if (tp
->min_pcr
&& tp
->min_pcr
> pcr
)
2148 PRINTD (DBG_QOS
, "pcr less than min_pcr");
2150 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2151 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2152 // [this would get rid of next two conditionals]
2153 if ((0) && tp
->max_pcr
== ATM_MAX_PCR
)
2154 PRINTD (DBG_QOS
, "luser gave max_pcr = ATM_MAX_PCR");
2155 else if ((tp
->max_pcr
!= ATM_MAX_PCR
) && tp
->max_pcr
< 0)
2156 PRINTD (DBG_QOS
, "luser gave negative max_pcr");
2157 else if (tp
->max_pcr
&& tp
->max_pcr
!= ATM_MAX_PCR
&& tp
->max_pcr
< pcr
)
2158 PRINTD (DBG_QOS
, "pcr greater than max_pcr");
2160 // each limit unspecified or not violated
2161 PRINTD (DBG_QOS
, "xBR(pcr) OK");
2164 PRINTD (DBG_QOS
, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2165 pcr
, tp
->min_pcr
, tp
->pcr
, tp
->max_pcr
);
2169 /********** open VC **********/
2171 static int hrz_open (struct atm_vcc
* atm_vcc
, short vpi
, int vci
) {
2175 struct atm_qos
* qos
;
2176 struct atm_trafprm
* txtp
;
2177 struct atm_trafprm
* rxtp
;
2179 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2181 hrz_vcc
* vccp
; // allocated late
2182 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_open %x %x", vpi
, vci
);
2184 #ifdef ATM_VPI_UNSPEC
2185 // UNSPEC is deprecated, remove this code eventually
2186 if (vpi
== ATM_VPI_UNSPEC
|| vci
== ATM_VCI_UNSPEC
) {
2187 PRINTK (KERN_WARNING
, "rejecting open with unspecified VPI/VCI (deprecated)");
2192 // deal with possibly wildcarded VCs
2193 error
= atm_find_ci (atm_vcc
, &vpi
, &vci
);
2195 PRINTD (DBG_WARN
|DBG_VCC
, "atm_find_ci failed!");
2198 PRINTD (DBG_VCC
, "atm_find_ci gives %x %x", vpi
, vci
);
2200 error
= vpivci_to_channel (&channel
, vpi
, vci
);
2202 PRINTD (DBG_WARN
|DBG_VCC
, "VPI/VCI out of range: %hd/%d", vpi
, vci
);
2206 vcc
.channel
= channel
;
2207 // max speed for the moment
2210 qos
= &atm_vcc
->qos
;
2212 // check AAL and remember it
2215 // we would if it were 48 bytes and not 52!
2216 PRINTD (DBG_QOS
|DBG_VCC
, "AAL0");
2220 // we would if I knew how do the SAR!
2221 PRINTD (DBG_QOS
|DBG_VCC
, "AAL3/4");
2225 PRINTD (DBG_QOS
|DBG_VCC
, "AAL5");
2229 PRINTD (DBG_QOS
|DBG_VCC
, "Bad AAL!");
2234 // TX traffic parameters
2236 // there are two, interrelated problems here: 1. the reservation of
2237 // PCR is not a binary choice, we are given bounds and/or a
2238 // desirable value; 2. the device is only capable of certain values,
2239 // most of which are not integers. It is almost certainly acceptable
2240 // to be off by a maximum of 1 to 10 cps.
2242 // Pragmatic choice: always store an integral PCR as that which has
2243 // been allocated, even if we allocate a little (or a lot) less,
2244 // after rounding. The actual allocation depends on what we can
2245 // manage with our rate selection algorithm. The rate selection
2246 // algorithm is given an integral PCR and a tolerance and told
2247 // whether it should round the value up or down if the tolerance is
2248 // exceeded; it returns: a) the actual rate selected (rounded up to
2249 // the nearest integer), b) a bit pattern to feed to the timer
2250 // register, and c) a failure value if no applicable rate exists.
2252 // Part of the job is done by atm_pcr_goal which gives us a PCR
2253 // specification which says: EITHER grab the maximum available PCR
2254 // (and perhaps a lower bound which we musn't pass), OR grab this
2255 // amount, rounding down if you have to (and perhaps a lower bound
2256 // which we musn't pass) OR grab this amount, rounding up if you
2257 // have to (and perhaps an upper bound which we musn't pass). If any
2258 // bounds ARE passed we fail. Note that rounding is only rounding to
2259 // match device limitations, we do not round down to satisfy
2260 // bandwidth availability even if this would not violate any given
2263 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2264 // (say) so this is not even a binary fixpoint cell rate (but this
2265 // device can do it). To avoid this sort of hassle we use a
2266 // tolerance parameter (currently fixed at 10 cps).
2268 PRINTD (DBG_QOS
, "TX:");
2272 // set up defaults for no traffic
2274 // who knows what would actually happen if you try and send on this?
2275 vcc
.tx_xbr_bits
= IDLE_RATE_TYPE
;
2276 vcc
.tx_pcr_bits
= CLOCK_DISABLE
;
2278 vcc
.tx_scr_bits
= CLOCK_DISABLE
;
2279 vcc
.tx_bucket_bits
= 0;
2282 if (txtp
->traffic_class
!= ATM_NONE
) {
2283 error
= check_max_sdu (vcc
.aal
, txtp
, max_tx_size
);
2285 PRINTD (DBG_QOS
, "TX max_sdu check failed");
2289 switch (txtp
->traffic_class
) {
2291 // we take "the PCR" as a rate-cap
2294 make_rate (dev
, 1<<30, round_nearest
, &vcc
.tx_pcr_bits
, 0);
2295 vcc
.tx_xbr_bits
= ABR_RATE_TYPE
;
2300 // reserve min, allow up to max
2301 vcc
.tx_rate
= 0; // ?
2302 make_rate (dev
, 1<<30, round_nearest
, &vcc
.tx_pcr_bits
, 0);
2303 vcc
.tx_xbr_bits
= ABR_RATE_TYPE
;
2308 int pcr
= atm_pcr_goal (txtp
);
2311 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2312 // should really have: once someone gets unlimited bandwidth
2313 // that no more non-UBR channels can be opened until the
2314 // unlimited one closes?? For the moment, round_down means
2315 // greedy people actually get something and not nothing
2317 // slight race (no locking) here so we may get -EAGAIN
2318 // later; the greedy bastards would deserve it :)
2319 PRINTD (DBG_QOS
, "snatching all remaining TX bandwidth");
2320 pcr
= dev
->tx_avail
;
2321 } else if (pcr
< 0) {
2327 error
= make_rate_with_tolerance (dev
, pcr
, r
, 10,
2328 &vcc
.tx_pcr_bits
, &vcc
.tx_rate
);
2330 PRINTD (DBG_QOS
, "could not make rate from TX PCR");
2333 // not really clear what further checking is needed
2334 error
= atm_pcr_check (txtp
, vcc
.tx_rate
);
2336 PRINTD (DBG_QOS
, "TX PCR failed consistency check");
2339 vcc
.tx_xbr_bits
= CBR_RATE_TYPE
;
2344 int pcr
= atm_pcr_goal (txtp
);
2345 // int scr = atm_scr_goal (txtp);
2346 int scr
= pcr
/2; // just for fun
2347 unsigned int mbs
= 60; // just for fun
2350 unsigned int bucket
;
2354 } else if (pcr
< 0) {
2360 error
= make_rate_with_tolerance (dev
, pcr
, pr
, 10,
2361 &vcc
.tx_pcr_bits
, 0);
2363 // see comments for PCR with CBR above
2365 // slight race (no locking) here so we may get -EAGAIN
2366 // later; the greedy bastards would deserve it :)
2367 PRINTD (DBG_QOS
, "snatching all remaining TX bandwidth");
2368 scr
= dev
->tx_avail
;
2369 } else if (scr
< 0) {
2375 error
= make_rate_with_tolerance (dev
, scr
, sr
, 10,
2376 &vcc
.tx_scr_bits
, &vcc
.tx_rate
);
2378 PRINTD (DBG_QOS
, "could not make rate from TX SCR");
2381 // not really clear what further checking is needed
2382 // error = atm_scr_check (txtp, vcc.tx_rate);
2384 PRINTD (DBG_QOS
, "TX SCR failed consistency check");
2387 // bucket calculations (from a piece of paper...) cell bucket
2388 // capacity must be largest integer smaller than m(p-s)/p + 1
2389 // where m = max burst size, p = pcr, s = scr
2390 bucket
= mbs
*(pcr
-scr
)/pcr
;
2391 if (bucket
*pcr
!= mbs
*(pcr
-scr
))
2393 if (bucket
> BUCKET_MAX_SIZE
) {
2394 PRINTD (DBG_QOS
, "shrinking bucket from %u to %u",
2395 bucket
, BUCKET_MAX_SIZE
);
2396 bucket
= BUCKET_MAX_SIZE
;
2398 vcc
.tx_xbr_bits
= VBR_RATE_TYPE
;
2399 vcc
.tx_bucket_bits
= bucket
;
2404 PRINTD (DBG_QOS
, "unsupported TX traffic class");
2411 // RX traffic parameters
2413 PRINTD (DBG_QOS
, "RX:");
2417 // set up defaults for no traffic
2420 if (rxtp
->traffic_class
!= ATM_NONE
) {
2421 error
= check_max_sdu (vcc
.aal
, rxtp
, max_rx_size
);
2423 PRINTD (DBG_QOS
, "RX max_sdu check failed");
2426 switch (rxtp
->traffic_class
) {
2434 vcc
.rx_rate
= 0; // ?
2439 int pcr
= atm_pcr_goal (rxtp
);
2441 // slight race (no locking) here so we may get -EAGAIN
2442 // later; the greedy bastards would deserve it :)
2443 PRINTD (DBG_QOS
, "snatching all remaining RX bandwidth");
2444 pcr
= dev
->rx_avail
;
2445 } else if (pcr
< 0) {
2449 // not really clear what further checking is needed
2450 error
= atm_pcr_check (rxtp
, vcc
.rx_rate
);
2452 PRINTD (DBG_QOS
, "RX PCR failed consistency check");
2459 // int scr = atm_scr_goal (rxtp);
2460 int scr
= 1<<16; // just for fun
2462 // slight race (no locking) here so we may get -EAGAIN
2463 // later; the greedy bastards would deserve it :)
2464 PRINTD (DBG_QOS
, "snatching all remaining RX bandwidth");
2465 scr
= dev
->rx_avail
;
2466 } else if (scr
< 0) {
2470 // not really clear what further checking is needed
2471 // error = atm_scr_check (rxtp, vcc.rx_rate);
2473 PRINTD (DBG_QOS
, "RX SCR failed consistency check");
2480 PRINTD (DBG_QOS
, "unsupported RX traffic class");
2488 // late abort useful for diagnostics
2489 if (vcc
.aal
!= aal5
) {
2490 PRINTD (DBG_QOS
, "AAL not supported");
2494 // get space for our vcc stuff and copy parameters into it
2495 vccp
= kmalloc (sizeof(hrz_vcc
), GFP_KERNEL
);
2497 PRINTK (KERN_ERR
, "out of memory!");
2502 // clear error and grab cell rate resource lock
2504 spin_lock (&dev
->rate_lock
);
2506 if (vcc
.tx_rate
> dev
->tx_avail
) {
2507 PRINTD (DBG_QOS
, "not enough TX PCR left");
2511 if (vcc
.rx_rate
> dev
->rx_avail
) {
2512 PRINTD (DBG_QOS
, "not enough RX PCR left");
2517 // really consume cell rates
2518 dev
->tx_avail
-= vcc
.tx_rate
;
2519 dev
->rx_avail
-= vcc
.rx_rate
;
2520 PRINTD (DBG_QOS
|DBG_VCC
, "reserving %u TX PCR and %u RX PCR",
2521 vcc
.tx_rate
, vcc
.rx_rate
);
2524 // release lock and exit on error
2525 spin_unlock (&dev
->rate_lock
);
2527 PRINTD (DBG_QOS
|DBG_VCC
, "insufficient cell rate resources");
2532 // this is "immediately before allocating the connection identifier
2533 // in hardware" - so long as the next call does not fail :)
2534 set_bit(ATM_VF_ADDR
,&atm_vcc
->flags
);
2536 // any errors here are very serious and should never occur
2538 if (rxtp
->traffic_class
!= ATM_NONE
) {
2539 if (dev
->rxer
[channel
]) {
2540 PRINTD (DBG_ERR
|DBG_VCC
, "VC already open for RX");
2544 error
= hrz_open_rx (dev
, channel
);
2549 // this link allows RX frames through
2550 dev
->rxer
[channel
] = atm_vcc
;
2553 // success, set elements of atm_vcc
2556 atm_vcc
->dev_data
= (void *) vccp
;
2558 // indicate readiness
2559 set_bit(ATM_VF_READY
,&atm_vcc
->flags
);
2564 /********** close VC **********/
2566 static void hrz_close (struct atm_vcc
* atm_vcc
) {
2567 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2568 hrz_vcc
* vcc
= HRZ_VCC(atm_vcc
);
2569 u16 channel
= vcc
->channel
;
2570 PRINTD (DBG_VCC
|DBG_FLOW
, "hrz_close");
2572 // indicate unreadiness
2573 clear_bit(ATM_VF_READY
,&atm_vcc
->flags
);
2575 if (atm_vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2578 // let any TX on this channel that has started complete
2579 // no restart, just keep trying
2580 while (tx_hold (dev
))
2582 // remove record of any tx_channel having been setup for this channel
2583 for (i
= 0; i
< TX_CHANS
; ++i
)
2584 if (dev
->tx_channel_record
[i
] == channel
) {
2585 dev
->tx_channel_record
[i
] = -1;
2588 if (dev
->last_vc
== channel
)
2593 if (atm_vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2594 // disable RXing - it tries quite hard
2595 hrz_close_rx (dev
, channel
);
2596 // forget the vcc - no more skbs will be pushed
2597 if (atm_vcc
!= dev
->rxer
[channel
])
2598 PRINTK (KERN_ERR
, "%s atm_vcc=%p rxer[channel]=%p",
2599 "arghhh! we're going to die!",
2600 atm_vcc
, dev
->rxer
[channel
]);
2601 dev
->rxer
[channel
] = 0;
2604 // atomically release our rate reservation
2605 spin_lock (&dev
->rate_lock
);
2606 PRINTD (DBG_QOS
|DBG_VCC
, "releasing %u TX PCR and %u RX PCR",
2607 vcc
->tx_rate
, vcc
->rx_rate
);
2608 dev
->tx_avail
+= vcc
->tx_rate
;
2609 dev
->rx_avail
+= vcc
->rx_rate
;
2610 spin_unlock (&dev
->rate_lock
);
2612 // free our structure
2614 // say the VPI/VCI is free again
2615 clear_bit(ATM_VF_ADDR
,&atm_vcc
->flags
);
2619 static int hrz_getsockopt (struct atm_vcc
* atm_vcc
, int level
, int optname
,
2620 void *optval
, int optlen
) {
2621 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2622 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_getsockopt");
2631 return -ENOPROTOOPT
;
2639 static int hrz_setsockopt (struct atm_vcc
* atm_vcc
, int level
, int optname
,
2640 void *optval
, int optlen
) {
2641 hrz_dev
* dev
= HRZ_DEV(atm_vcc
->dev
);
2642 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_setsockopt");
2651 return -ENOPROTOOPT
;
2660 static int hrz_sg_send (struct atm_vcc
* atm_vcc
,
2661 unsigned long start
,
2662 unsigned long size
) {
2663 if (atm_vcc
->qos
.aal
== ATM_AAL5
) {
2664 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_sg_send: yes");
2667 PRINTD (DBG_FLOW
|DBG_VCC
, "hrz_sg_send: no");
2673 static int hrz_ioctl (struct atm_dev
* atm_dev
, unsigned int cmd
, void *arg
) {
2674 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2675 PRINTD (DBG_FLOW
, "hrz_ioctl");
2679 unsigned char hrz_phy_get (struct atm_dev
* atm_dev
, unsigned long addr
) {
2680 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2681 PRINTD (DBG_FLOW
, "hrz_phy_get");
2685 static void hrz_phy_put (struct atm_dev
* atm_dev
, unsigned char value
,
2686 unsigned long addr
) {
2687 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2688 PRINTD (DBG_FLOW
, "hrz_phy_put");
2691 static int hrz_change_qos (struct atm_vcc
* atm_vcc
, struct atm_qos
*qos
, int flgs
) {
2692 hrz_dev
* dev
= HRZ_DEV(vcc
->dev
);
2693 PRINTD (DBG_FLOW
, "hrz_change_qos");
2698 /********** proc file contents **********/
2700 static int hrz_proc_read (struct atm_dev
* atm_dev
, loff_t
* pos
, char * page
) {
2701 hrz_dev
* dev
= HRZ_DEV(atm_dev
);
2703 PRINTD (DBG_FLOW
, "hrz_proc_read");
2705 /* more diagnostics here? */
2709 unsigned int count
= sprintf (page
, "vbr buckets:");
2711 for (i
= 0; i
< TX_CHANS
; ++i
)
2712 count
+= sprintf (page
, " %u/%u",
2713 query_tx_channel_config (dev
, i
, BUCKET_FULLNESS_ACCESS
),
2714 query_tx_channel_config (dev
, i
, BUCKET_CAPACITY_ACCESS
));
2715 count
+= sprintf (page
+count
, ".\n");
2721 return sprintf (page
,
2722 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2723 dev
->tx_cell_count
, dev
->rx_cell_count
,
2724 dev
->hec_error_count
, dev
->unassigned_cell_count
);
2727 return sprintf (page
,
2728 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2729 rd_regw (dev
, TX_FREE_BUFFER_COUNT_OFF
),
2730 rd_regw (dev
, RX_FREE_BUFFER_COUNT_OFF
),
2731 dev
->noof_spare_buffers
);
2734 return sprintf (page
,
2735 "cps remaining: TX %u, RX %u\n",
2736 dev
->tx_avail
, dev
->rx_avail
);
2741 static const struct atmdev_ops hrz_ops
= {
2745 sg_send
: hrz_sg_send
,
2746 proc_read
: hrz_proc_read
,
2750 static int __init
hrz_probe (void) {
2751 struct pci_dev
* pci_dev
;
2754 PRINTD (DBG_FLOW
, "hrz_probe");
2758 while ((pci_dev
= pci_find_device
2759 (PCI_VENDOR_ID_MADGE
, PCI_DEVICE_ID_MADGE_HORIZON
, pci_dev
)
2763 // adapter slot free, read resources from PCI configuration space
2764 u32 iobase
= pci_resource_start (pci_dev
, 0);
2765 u32
* membase
= bus_to_virt (pci_resource_start (pci_dev
, 1));
2766 u8 irq
= pci_dev
->irq
;
2769 if (check_region (iobase
, HRZ_IO_EXTENT
)) {
2770 PRINTD (DBG_WARN
, "IO range already in use");
2774 if (pci_enable_device (pci_dev
))
2777 dev
= kmalloc (sizeof(hrz_dev
), GFP_KERNEL
);
2779 // perhaps we should be nice: deregister all adapters and abort?
2780 PRINTD (DBG_ERR
, "out of memory");
2784 memset (dev
, 0, sizeof(hrz_dev
));
2786 // grab IRQ and install handler - move this someplace more sensible
2787 if (request_irq (irq
,
2789 SA_SHIRQ
, /* irqflags guess */
2790 DEV_LABEL
, /* name guess */
2792 PRINTD (DBG_WARN
, "request IRQ failed!");
2793 // free_irq is at "endif"
2796 PRINTD (DBG_INFO
, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2797 iobase
, irq
, membase
);
2799 dev
->atm_dev
= atm_dev_register (DEV_LABEL
, &hrz_ops
, -1, NULL
);
2800 if (!(dev
->atm_dev
)) {
2801 PRINTD (DBG_ERR
, "failed to register Madge ATM adapter");
2805 PRINTD (DBG_INFO
, "registered Madge ATM adapter (no. %d) (%p) at %p",
2806 dev
->atm_dev
->number
, dev
, dev
->atm_dev
);
2807 dev
->atm_dev
->dev_data
= (void *) dev
;
2808 dev
->pci_dev
= pci_dev
;
2810 /* XXX DEV_LABEL is a guess */
2811 request_region (iobase
, HRZ_IO_EXTENT
, DEV_LABEL
);
2813 // enable bus master accesses
2814 pci_set_master (pci_dev
);
2816 // frobnicate latency (upwards, usually)
2817 pci_read_config_byte (pci_dev
, PCI_LATENCY_TIMER
, &lat
);
2819 PRINTD (DBG_INFO
, "%s PCI latency timer from %hu to %hu",
2820 "changing", lat
, pci_lat
);
2821 pci_write_config_byte (pci_dev
, PCI_LATENCY_TIMER
, pci_lat
);
2822 } else if (lat
< MIN_PCI_LATENCY
) {
2823 PRINTK (KERN_INFO
, "%s PCI latency timer from %hu to %hu",
2824 "increasing", lat
, MIN_PCI_LATENCY
);
2825 pci_write_config_byte (pci_dev
, PCI_LATENCY_TIMER
, MIN_PCI_LATENCY
);
2828 dev
->iobase
= iobase
;
2830 dev
->membase
= membase
;
2832 dev
->rx_q_entry
= dev
->rx_q_reset
= &memmap
->rx_q_entries
[0];
2833 dev
->rx_q_wrap
= &memmap
->rx_q_entries
[RX_CHANS
-1];
2835 // these next three are performance hacks
2840 dev
->tx_regions
= 0;
2845 dev
->tx_cell_count
= 0;
2846 dev
->rx_cell_count
= 0;
2847 dev
->hec_error_count
= 0;
2848 dev
->unassigned_cell_count
= 0;
2850 dev
->noof_spare_buffers
= 0;
2854 for (i
= 0; i
< TX_CHANS
; ++i
)
2855 dev
->tx_channel_record
[i
] = -1;
2860 // Allocate cell rates and remember ASIC version
2861 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2862 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2863 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2865 if (hrz_init (dev
)) {
2866 // to be really pedantic, this should be ATM_OC3c_PCR
2867 dev
->tx_avail
= ATM_OC3_PCR
;
2868 dev
->rx_avail
= ATM_OC3_PCR
;
2869 set_bit (ultra
, &dev
->flags
); // NOT "|= ultra" !
2871 dev
->tx_avail
= ((25600000/8)*26)/(27*53);
2872 dev
->rx_avail
= ((25600000/8)*26)/(27*53);
2873 PRINTD (DBG_WARN
, "Buggy ASIC: no TX bus-mastering.");
2876 // rate changes spinlock
2877 spin_lock_init (&dev
->rate_lock
);
2879 // on-board memory access spinlock; we want atomic reads and
2880 // writes to adapter memory (handles IRQ and SMP)
2881 spin_lock_init (&dev
->mem_lock
);
2883 #if LINUX_VERSION_CODE >= 0x20303
2884 init_waitqueue_head (&dev
->tx_queue
);
2889 // vpi in 0..4, vci in 6..10
2890 dev
->atm_dev
->ci_range
.vpi_bits
= vpi_bits
;
2891 dev
->atm_dev
->ci_range
.vci_bits
= 10-vpi_bits
;
2893 // update count and linked list
2895 dev
->prev
= hrz_devs
;
2900 /* not currently reached */
2901 atm_dev_deregister (dev
->atm_dev
);
2902 } /* atm_dev_register */
2903 free_irq (irq
, dev
);
2906 } /* kmalloc and while */
2910 static void __init
hrz_check_args (void) {
2911 #ifdef DEBUG_HORIZON
2912 PRINTK (KERN_NOTICE
, "debug bitmap is %hx", debug
&= DBG_MASK
);
2915 PRINTK (KERN_NOTICE
, "no debug support in this image");
2918 if (vpi_bits
> HRZ_MAX_VPI
)
2919 PRINTK (KERN_ERR
, "vpi_bits has been limited to %hu",
2920 vpi_bits
= HRZ_MAX_VPI
);
2922 if (max_tx_size
> TX_AAL5_LIMIT
)
2923 PRINTK (KERN_NOTICE
, "max_tx_size has been limited to %hu",
2924 max_tx_size
= TX_AAL5_LIMIT
);
2926 if (max_rx_size
> RX_AAL5_LIMIT
)
2927 PRINTK (KERN_NOTICE
, "max_rx_size has been limited to %hu",
2928 max_rx_size
= RX_AAL5_LIMIT
);
2936 MODULE_AUTHOR(maintainer_string
);
2937 MODULE_DESCRIPTION(description_string
);
2938 MODULE_PARM(debug
, "h");
2939 MODULE_PARM(vpi_bits
, "h");
2940 MODULE_PARM(max_tx_size
, "h");
2941 MODULE_PARM(max_rx_size
, "h");
2942 MODULE_PARM(pci_lat
, "b");
2943 MODULE_PARM_DESC(debug
, "debug bitmap, see .h file");
2944 MODULE_PARM_DESC(vpi_bits
, "number of bits (0..4) to allocate to VPIs");
2945 MODULE_PARM_DESC(max_tx_size
, "maximum size of TX AAL5 frames");
2946 MODULE_PARM_DESC(max_rx_size
, "maximum size of RX AAL5 frames");
2947 MODULE_PARM_DESC(pci_lat
, "PCI latency in bus cycles");
2949 /********** module entry **********/
2951 int init_module (void) {
2954 // sanity check - cast is needed since printk does not support %Zu
2955 if (sizeof(struct MEMMAP
) != 128*1024/4) {
2956 PRINTK (KERN_ERR
, "Fix struct MEMMAP (is %lu fakewords).",
2957 (unsigned long) sizeof(struct MEMMAP
));
2970 init_timer (&housekeeping
);
2971 housekeeping
.function
= do_housekeeping
;
2973 housekeeping
.data
= 1;
2974 set_timer (&housekeeping
, 0);
2976 PRINTK (KERN_ERR
, "no (usable) adapters found");
2979 return devs
? 0 : -ENODEV
;
2982 /********** module exit **********/
2984 void cleanup_module (void) {
2986 PRINTD (DBG_FLOW
, "cleanup_module");
2989 housekeeping
.data
= 0;
2990 del_timer (&housekeeping
);
2994 hrz_devs
= dev
->prev
;
2996 PRINTD (DBG_INFO
, "closing %p (atm_dev = %p)", dev
, dev
->atm_dev
);
2998 atm_dev_deregister (dev
->atm_dev
);
2999 free_irq (dev
->irq
, dev
);
3000 release_region (dev
->iobase
, HRZ_IO_EXTENT
);
3009 /********** monolithic entry **********/
3011 int __init
hrz_detect (void) {
3014 // sanity check - cast is needed since printk does not support %Zu
3015 if (sizeof(struct MEMMAP
) != 128*1024/4) {
3016 PRINTK (KERN_ERR
, "Fix struct MEMMAP (is %lu fakewords).",
3017 (unsigned long) sizeof(struct MEMMAP
));
3023 // what about command line arguments?
3031 init_timer (&housekeeping
);
3032 housekeeping
.function
= do_housekeeping
;
3034 housekeeping
.data
= 1;
3035 set_timer (&housekeeping
, 0);
3037 PRINTK (KERN_ERR
, "no (usable) adapters found");