include/asm-parisc/system.h

   1 #ifndef __PARISC_SYSTEM_H
   2 #define __PARISC_SYSTEM_H
   3
   4 #include <asm/psw.h>
   5
   6 /* The program status word as bitfields.  */
   7 struct pa_psw {
   8         unsigned int y:1;
   9         unsigned int z:1;
  10         unsigned int rv:2;
  11         unsigned int w:1;
  12         unsigned int e:1;
  13         unsigned int s:1;
  14         unsigned int t:1;
  15
  16         unsigned int h:1;
  17         unsigned int l:1;
  18         unsigned int n:1;
  19         unsigned int x:1;
  20         unsigned int b:1;
  21         unsigned int c:1;
  22         unsigned int v:1;
  23         unsigned int m:1;
  24
  25         unsigned int cb:8;
  26
  27         unsigned int o:1;
  28         unsigned int g:1;
  29         unsigned int f:1;
  30         unsigned int r:1;
  31         unsigned int q:1;
  32         unsigned int p:1;
  33         unsigned int d:1;
  34         unsigned int i:1;
  35 };
  36
  37 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
  38
  39 struct task_struct;
  40
  41 extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
  42
  43 #define prepare_to_switch()     do { } while(0)
  44 #define switch_to(prev, next, last) do {                        \
  45         (last) = _switch_to(prev, next);                        \
  46 } while(0)
  47
  48 /* borrowed this from sparc64 -- probably the SMP case is hosed for us */
  49 #ifdef CONFIG_SMP
  50 #define smp_mb()        mb()
  51 #define smp_rmb()       rmb()
  52 #define smp_wmb()       wmb()
  53 #else
  54 /* This is simply the barrier() macro from linux/kernel.h but when serial.c
  55  * uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
  56  * hasn't yet been included yet so it fails, thus repeating the macro here.
  57  */
  58 #define smp_mb()        __asm__ __volatile__("":::"memory");
  59 #define smp_rmb()       __asm__ __volatile__("":::"memory");
  60 #define smp_wmb()       __asm__ __volatile__("":::"memory");
  61 #endif
  62
  63 /* interrupt control */
  64 #define __save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory")
  65 #define __restore_flags(x) __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory")
  66 #define __cli() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
  67 #define __sti() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
  68
  69 #define local_irq_save(x) \
  70         __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" )
  71 #define local_irq_restore(x) \
  72         __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" )
  73 #define local_irq_disable() __cli()
  74 #define local_irq_enable()  __sti()
  75
  76 #ifdef CONFIG_SMP
  77 #else
  78 #define cli() __cli()
  79 #define sti() __sti()
  80 #define save_flags(x) __save_flags(x)
  81 #define restore_flags(x) __restore_flags(x)
  82 #endif
  83
  84
  85 #define mfctl(reg)      ({              \
  86         unsigned long cr;               \
  87         __asm__ __volatile__(           \
  88                 "mfctl " #reg ",%0" :   \
  89                  "=r" (cr)              \
  90         );                              \
  91         cr;                             \
  92 })
  93
  94 #define mtctl(gr, cr) \
  95         __asm__ __volatile__("mtctl %0,%1" \
  96                 : /* no outputs */ \
  97                 : "r" (gr), "i" (cr))
  98
  99 /* these are here to de-mystefy the calling code, and to provide hooks */
 100 /* which I needed for debugging EIEM problems -PB */
 101 #define get_eiem() mfctl(15)
 102 static inline void set_eiem(unsigned long val)
 103 {
 104         mtctl(val, 15);
 105 }
 106
 107 #define mfsp(reg)       ({              \
 108         unsigned long cr;               \
 109         __asm__ __volatile__(           \
 110                 "mfsp " #reg ",%0" :    \
 111                  "=r" (cr)              \
 112         );                              \
 113         cr;                             \
 114 })
 115
 116 #define mtsp(gr, cr) \
 117         __asm__ __volatile__("mtsp %0,%1" \
 118                 : /* no outputs */ \
 119                 : "r" (gr), "i" (cr))
 120
 121
 122 #define mb()  __asm__ __volatile__ ("sync" : : :"memory")
 123 #define wmb() mb()
 124
 125 extern unsigned long __xchg(unsigned long, unsigned long *, int);
 126
 127 #define xchg(ptr,x) \
 128  (__typeof__(*(ptr)))__xchg((unsigned long)(x),(unsigned long*)(ptr),sizeof(*(ptr)))
 129
 130 /* LDCW, the only atomic read-write operation PA-RISC has.  Sigh. */
 131 #define __ldcw(a) ({ \
 132         unsigned __ret; \
 133         __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \
 134         __ret; \
 135 })
 136
 137 #ifdef CONFIG_SMP
 138 /*
 139  * Your basic SMP spinlocks, allowing only a single CPU anywhere
 140  */
 141
 142 typedef struct {
 143         volatile unsigned int __attribute__((aligned(16))) lock;
 144 } spinlock_t;
 145 #endif
 146
 147 #endif