include/asm-i386/pgtable-3level.h

   1 #ifndef _I386_PGTABLE_3LEVEL_H
   2 #define _I386_PGTABLE_3LEVEL_H
   3
   4 /*
   5  * Intel Physical Address Extension (PAE) Mode - three-level page
   6  * tables on PPro+ CPUs.
   7  *
   8  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
   9  */
  10
  11 /*
  12  * PGDIR_SHIFT determines what a top-level page table entry can map
  13  */
  14 #define PGDIR_SHIFT     30
  15 #define PTRS_PER_PGD    4
  16
  17 /*
  18  * PMD_SHIFT determines the size of the area a middle-level
  19  * page table can map
  20  */
  21 #define PMD_SHIFT       21
  22 #define PTRS_PER_PMD    512
  23
  24 /*
  25  * entries per page directory level
  26  */
  27 #define PTRS_PER_PTE    512
  28
  29 #define pte_ERROR(e) \
  30         printk("%s:%d: bad pte %p(%016Lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
  31 #define pmd_ERROR(e) \
  32         printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
  33 #define pgd_ERROR(e) \
  34         printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
  35
  36 /*
  37  * Subtle, in PAE mode we cannot have zeroes in the top level
  38  * page directory, the CPU enforces this. (ie. the PGD entry
  39  * always has to have the present bit set.) The CPU caches
  40  * the 4 pgd entries internally, so there is no extra memory
  41  * load on TLB miss, despite one more level of indirection.
  42  */
  43 #define EMPTY_PGD (__pa(empty_zero_page) + 1)
  44 #define pgd_none(x)     (pgd_val(x) == EMPTY_PGD)
  45 extern inline int pgd_bad(pgd_t pgd)            { return 0; }
  46 extern inline int pgd_present(pgd_t pgd)        { return !pgd_none(pgd); }
  47
  48 #define set_pte(pteptr,pteval) \
  49                 set_64bit((unsigned long long *)(pteptr),pte_val(pteval))
  50 #define set_pmd(pmdptr,pmdval) \
  51                 set_64bit((unsigned long long *)(pmdptr),pmd_val(pmdval))
  52 #define set_pgd(pgdptr,pgdval) \
  53                 set_64bit((unsigned long long *)(pgdptr),pgd_val(pgdval))
  54
  55 /*
  56  * Pentium-II errata A13: in PAE mode we explicitly have to flush
  57  * the TLB via cr3 if the top-level pgd is changed... This was one tough
  58  * thing to find out - guess i should first read all the documentation
  59  * next time around ;)
  60  */
  61 extern inline void __pgd_clear (pgd_t * pgd)
  62 {
  63         set_pgd(pgd, __pgd(EMPTY_PGD));
  64 }
  65
  66 extern inline void pgd_clear (pgd_t * pgd)
  67 {
  68         __pgd_clear(pgd);
  69         __flush_tlb();
  70 }
  71
  72 #define pgd_page(pgd) \
  73 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
  74
  75 /* Find an entry in the second-level page table.. */
  76 #define pmd_offset(dir, address) ((pmd_t *) pgd_page(*(dir)) + \
  77                         __pmd_offset(address))
  78
  79 #endif /* _I386_PGTABLE_3LEVEL_H */