?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Import 2.3.30
[davej-history.git] / arch / alpha / kernel / sys_sio.c
blobf26991f55813fadba636cd75ab81f65afd243416
1 /*
2 * linux/arch/alpha/kernel/sys_sio.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Code for all boards that route the PCI interrupts through the SIO
9 * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
10 * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
11 */
12
13 #include <linux/config.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/mm.h>
17 #include <linux/sched.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20
21 #include <asm/compiler.h>
22 #include <asm/ptrace.h>
23 #include <asm/system.h>
24 #include <asm/dma.h>
25 #include <asm/irq.h>
26 #include <asm/mmu_context.h>
27 #include <asm/io.h>
28 #include <asm/pgtable.h>
29 #include <asm/core_apecs.h>
30 #include <asm/core_lca.h>
31
32 #include "proto.h"
33 #include <asm/hw_irq.h>
34 #include "pci_impl.h"
35 #include "machvec_impl.h"
36
37 static void
38 sio_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
39 {
40 if (irq >= 8)
41 outb(mask >> 8, 0xA1);
42 else
43 outb(mask, 0x21);
44 }
45
46 static void __init
47 sio_init_irq(void)
48 {
49 STANDARD_INIT_IRQ_PROLOG;
50
51 if (alpha_using_srm)
52 alpha_mv.device_interrupt = srm_device_interrupt;
53
54 enable_irq(2); /* enable cascade */
55 }
56
57 static inline void __init
58 xl_init_arch(void)
59 {
60 struct pci_controler *hose;
61
62 /*
63 * Set up the PCI->physical memory translation windows. For
64 * the XL we *must* use both windows, in order to maximize the
65 * amount of physical memory that can be used to DMA from the
66 * ISA bus, and still allow PCI bus devices access to all of
67 * host memory.
68 *
69 * See <asm/apecs.h> for window bases and sizes.
70 *
71 * This restriction due to the true XL motherboards' 82379AB SIO
72 * PCI<->ISA bridge chip which passes only 27 bits of address...
73 */
74
75 *(vuip)APECS_IOC_PB1R = 1<<19 | (APECS_XL_DMA_WIN1_BASE & 0xfff00000U);
76 *(vuip)APECS_IOC_PM1R = (APECS_XL_DMA_WIN1_SIZE - 1) & 0xfff00000U;
77 *(vuip)APECS_IOC_TB1R = 0;
78
79 *(vuip)APECS_IOC_PB2R = 1<<19 | (APECS_XL_DMA_WIN2_BASE & 0xfff00000U);
80 *(vuip)APECS_IOC_PM2R = (APECS_XL_DMA_WIN2_SIZE - 1) & 0xfff00000U;
81 *(vuip)APECS_IOC_TB2R = 0;
82
83 /*
84 * Finally, clear the HAXR2 register, which gets used for PCI
85 * Config Space accesses. That is the way we want to use it,
86 * and we do not want to depend on what ARC or SRM might have
87 * left behind...
88 */
89
90 *(vuip)APECS_IOC_HAXR2 = 0; mb();
91
92 /*
93 * Create our single hose.
94 */
95
96 hose = alloc_pci_controler();
97 hose->io_space = &ioport_resource;
98 hose->mem_space = &iomem_resource;
99 hose->config_space = LCA_CONF;
100 hose->index = 0;
101 }
102
103 static inline void __init
104 alphabook1_init_arch(void)
105 {
106 /* The AlphaBook1 has LCD video fixed at 800x600,
107 37 rows and 100 cols. */
108 screen_info.orig_y = 37;
109 screen_info.orig_video_cols = 100;
110 screen_info.orig_video_lines = 37;
111
112 lca_init_arch();
113 }
114
115
116 /*
117 * sio_route_tab selects irq routing in PCI/ISA bridge so that:
118 * PIRQ0 -> irq 15
119 * PIRQ1 -> irq 9
120 * PIRQ2 -> irq 10
121 * PIRQ3 -> irq 11
122 *
123 * This probably ought to be configurable via MILO. For
124 * example, sound boards seem to like using IRQ 9.
125 *
126 * This is NOT how we should do it. PIRQ0-X should have
127 * their own IRQ's, the way intel uses the IO-APIC irq's.
128 */
129
130 static void __init
131 sio_pci_route(void)
132 {
133 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60,
134 alpha_mv.sys.sio.route_tab);
135 }
136
137 static unsigned int __init
138 sio_collect_irq_levels(void)
139 {
140 unsigned int level_bits = 0;
141 struct pci_dev *dev;
142
143 /* Iterate through the devices, collecting IRQ levels. */
144 for (dev = pci_devices; dev; dev = dev->next) {
145 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
146 (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
147 continue;
148
149 if (dev->irq)
150 level_bits |= (1 << dev->irq);
151 }
152 return level_bits;
153 }
154
155 static void __init
156 sio_fixup_irq_levels(unsigned int level_bits)
157 {
158 unsigned int old_level_bits;
159
160 /*
161 * Now, make all PCI interrupts level sensitive. Notice:
162 * these registers must be accessed byte-wise. inw()/outw()
163 * don't work.
164 *
165 * Make sure to turn off any level bits set for IRQs 9,10,11,15,
166 * so that the only bits getting set are for devices actually found.
167 * Note that we do preserve the remainder of the bits, which we hope
168 * will be set correctly by ARC/SRM.
169 *
170 * Note: we at least preserve any level-set bits on AlphaBook1
171 */
172 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
173
174 level_bits |= (old_level_bits & 0x71ff);
175
176 outb((level_bits >> 0) & 0xff, 0x4d0);
177 outb((level_bits >> 8) & 0xff, 0x4d1);
178 }
179
180 static inline int __init
181 noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
182 {
183 /*
184 * The Noname board has 5 PCI slots with each of the 4
185 * interrupt pins routed to different pins on the PCI/ISA
186 * bridge (PIRQ0-PIRQ3). The table below is based on
187 * information available at:
188 *
189 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
190 *
191 * I have no information on the Avanti interrupt routing, but
192 * the routing seems to be identical to the Noname except
193 * that the Avanti has an additional slot whose routing I'm
194 * unsure of.
195 *
196 * pirq_tab[0] is a fake entry to deal with old PCI boards
197 * that have the interrupt pin number hardwired to 0 (meaning
198 * that they use the default INTA line, if they are interrupt
199 * driven at all).
200 */
201 static char irq_tab[][5] __initlocaldata = {
202 /*INT A B C D */
203 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
204 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
205 { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
206 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
207 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
208 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
209 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
210 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
211 { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
212 };
213 const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
214 int irq = COMMON_TABLE_LOOKUP, tmp;
215 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
216 return irq >= 0 ? tmp : -1;
217 }
218
219 static inline int __init
220 p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
221 {
222 static char irq_tab[][5] __initlocaldata = {
223 /*INT A B C D */
224 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
225 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
226 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
227 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
228 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
229 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
230 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
231 };
232 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
233 int irq = COMMON_TABLE_LOOKUP, tmp;
234 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
235 return irq >= 0 ? tmp : -1;
236 }
237
238 static inline void __init
239 noname_init_pci(void)
240 {
241 common_init_pci();
242 sio_pci_route();
243 sio_fixup_irq_levels(sio_collect_irq_levels());
244 ns87312_enable_ide(0x26e);
245 }
246
247 static inline void __init
248 alphabook1_init_pci(void)
249 {
250 struct pci_dev *dev;
251 unsigned char orig, config;
252
253 common_init_pci();
254 sio_pci_route();
255
256 /*
257 * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
258 * is sensitive to PCI bus bursts, so we must DISABLE
259 * burst mode for the NCR 8xx SCSI... :-(
260 *
261 * Note that the NCR810 SCSI driver must preserve the
262 * setting of the bit in order for this to work. At the
263 * moment (2.0.29), ncr53c8xx.c does NOT do this, but
264 * 53c7,8xx.c DOES.
265 */
266
267 dev = NULL;
268 while ((dev = pci_find_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
269 if (dev->device == PCI_DEVICE_ID_NCR_53C810
270 || dev->device == PCI_DEVICE_ID_NCR_53C815
271 || dev->device == PCI_DEVICE_ID_NCR_53C820
272 || dev->device == PCI_DEVICE_ID_NCR_53C825) {
273 unsigned long io_port;
274 unsigned char ctest4;
275
276 io_port = dev->resource[0].start;
277 ctest4 = inb(io_port+0x21);
278 if (!(ctest4 & 0x80)) {
279 printk("AlphaBook1 NCR init: setting"
280 " burst disable\n");
281 outb(ctest4 | 0x80, io_port+0x21);
282 }
283 }
284 }
285
286 /* Do not set *ANY* level triggers for AlphaBook1. */
287 sio_fixup_irq_levels(0);
288
289 /* Make sure that register PR1 indicates 1Mb mem */
290 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
291 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
292 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
293 if ((config & 0xc0) != 0xc0) {
294 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
295 config |= 0xc0;
296 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
297 }
298 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
299 }
300
301
302 /*
303 * The System Vectors
304 */
305
306 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
307 struct alpha_machine_vector alphabook1_mv __initmv = {
308 vector_name: "AlphaBook1",
309 DO_EV4_MMU,
310 DO_DEFAULT_RTC,
311 DO_LCA_IO,
312 DO_LCA_BUS,
313 machine_check: lca_machine_check,
314 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
315 min_io_address: DEFAULT_IO_BASE,
316 min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
317
318 nr_irqs: 16,
319 irq_probe_mask: _PROBE_MASK(16),
320 update_irq_hw: sio_update_irq_hw,
321 ack_irq: common_ack_irq,
322 device_interrupt: isa_device_interrupt,
323
324 init_arch: alphabook1_init_arch,
325 init_irq: sio_init_irq,
326 init_pit: common_init_pit,
327 init_pci: alphabook1_init_pci,
328 kill_arch: NULL,
329 pci_map_irq: noname_map_irq,
330 pci_swizzle: common_swizzle,
331
332 sys: { sio: {
333 /* NCR810 SCSI is 14, PCMCIA controller is 15. */
334 route_tab: 0x0e0f0a0a,
335 }}
336 };
337 ALIAS_MV(alphabook1)
338 #endif
339
340 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
341 struct alpha_machine_vector avanti_mv __initmv = {
342 vector_name: "Avanti",
343 DO_EV4_MMU,
344 DO_DEFAULT_RTC,
345 DO_APECS_IO,
346 DO_APECS_BUS,
347 machine_check: apecs_machine_check,
348 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
349 min_io_address: DEFAULT_IO_BASE,
350 min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
351
352 nr_irqs: 16,
353 irq_probe_mask: _PROBE_MASK(16),
354 update_irq_hw: sio_update_irq_hw,
355 ack_irq: common_ack_irq,
356 device_interrupt: isa_device_interrupt,
357
358 init_arch: apecs_init_arch,
359 init_irq: sio_init_irq,
360 init_pit: common_init_pit,
361 init_pci: noname_init_pci,
362 pci_map_irq: noname_map_irq,
363 pci_swizzle: common_swizzle,
364
365 sys: { sio: {
366 route_tab: 0x0b0a0e0f,
367 }}
368 };
369 ALIAS_MV(avanti)
370 #endif
371
372 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
373 struct alpha_machine_vector noname_mv __initmv = {
374 vector_name: "Noname",
375 DO_EV4_MMU,
376 DO_DEFAULT_RTC,
377 DO_LCA_IO,
378 DO_LCA_BUS,
379 machine_check: lca_machine_check,
380 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
381 min_io_address: DEFAULT_IO_BASE,
382 min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
383
384 nr_irqs: 16,
385 irq_probe_mask: _PROBE_MASK(16),
386 update_irq_hw: sio_update_irq_hw,
387 ack_irq: common_ack_irq,
388 device_interrupt: srm_device_interrupt,
389
390 init_arch: lca_init_arch,
391 init_irq: sio_init_irq,
392 init_pit: common_init_pit,
393 init_pci: noname_init_pci,
394 pci_map_irq: noname_map_irq,
395 pci_swizzle: common_swizzle,
396
397 sys: { sio: {
398 /* For UDB, the only available PCI slot must not map to IRQ 9,
399 since that's the builtin MSS sound chip. That PCI slot
400 will map to PIRQ1 (for INTA at least), so we give it IRQ 15
401 instead.
402
403 Unfortunately we have to do this for NONAME as well, since
404 they are co-indicated when the platform type "Noname" is
405 selected... :-( */
406
407 route_tab: 0x0b0a0f0d,
408 }}
409 };
410 ALIAS_MV(noname)
411 #endif
412
413 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
414 struct alpha_machine_vector p2k_mv __initmv = {
415 vector_name: "Platform2000",
416 DO_EV4_MMU,
417 DO_DEFAULT_RTC,
418 DO_LCA_IO,
419 DO_LCA_BUS,
420 machine_check: lca_machine_check,
421 max_dma_address: ALPHA_MAX_DMA_ADDRESS,
422 min_io_address: DEFAULT_IO_BASE,
423 min_mem_address: APECS_AND_LCA_DEFAULT_MEM_BASE,
424
425 nr_irqs: 16,
426 irq_probe_mask: P2K_PROBE_MASK,
427 update_irq_hw: sio_update_irq_hw,
428 ack_irq: common_ack_irq,
429 device_interrupt: srm_device_interrupt,
430
431 init_arch: lca_init_arch,
432 init_irq: sio_init_irq,
433 init_pit: common_init_pit,
434 init_pci: noname_init_pci,
435 pci_map_irq: p2k_map_irq,
436 pci_swizzle: common_swizzle,
437
438 sys: { sio: {
439 route_tab: 0x0b0a090f,
440 }}
441 };
442 ALIAS_MV(p2k)
443 #endif
444
445 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
446 struct alpha_machine_vector xl_mv __initmv = {
447 vector_name: "XL",
448 DO_EV4_MMU,
449 DO_DEFAULT_RTC,
450 DO_APECS_IO,
451 BUS(apecs_xl),
452 machine_check: apecs_machine_check,
453 max_dma_address: ALPHA_XL_MAX_DMA_ADDRESS,
454 min_io_address: DEFAULT_IO_BASE,
455 min_mem_address: XL_DEFAULT_MEM_BASE,
456
457 nr_irqs: 16,
458 irq_probe_mask: _PROBE_MASK(16),
459 update_irq_hw: sio_update_irq_hw,
460 ack_irq: common_ack_irq,
461 device_interrupt: isa_device_interrupt,
462
463 init_arch: xl_init_arch,
464 init_irq: sio_init_irq,
465 init_pit: common_init_pit,
466 init_pci: noname_init_pci,
467 pci_map_irq: noname_map_irq,
468 pci_swizzle: common_swizzle,
469
470 sys: { sio: {
471 route_tab: 0x0b0a090f,
472 }}
473 };
474 ALIAS_MV(xl)
475 #endif
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux