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1 /* $Id: timer.h,v 1.2 1998/03/15 17:23:52 ecd Exp $
2 * timer.h: System timer definitions for sun5.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 */
7 #ifndef _SPARC64_TIMER_H
8 #define _SPARC64_TIMER_H
10 /* How timers work:
12 * On uniprocessors we just use counter zero for the system wide
13 * ticker, this performs thread scheduling, clock book keeping,
14 * and runs timer based events. Previously we used the Ultra
15 * %tick interrupt for this purpose.
17 * On multiprocessors we pick one cpu as the master level 10 tick
18 * processor. Here this counter zero tick handles clock book
19 * keeping and timer events only. Each Ultra has it's level
20 * 14 %tick interrupt set to fire off as well, even the master
21 * tick cpu runs this locally. This ticker performs thread
22 * scheduling, system/user tick counting for the current thread,
23 * and also profiling if enabled.
26 /* Two timers, traditionally steered to PIL's 10 and 14 respectively.
27 * But since INO packets are used on sun5, we could use any PIL level
28 * we like, however for now we use the normal ones.
30 * The 'reg' and 'interrupts' properties for these live in nodes named
31 * 'counter-timer'. The first of three 'reg' properties describe where
32 * the sun5_timer registers are. The other two I have no idea. (XXX)
34 struct sun5_timer {
35 u64 count0;
36 u64 limit0;
37 u64 count1;
38 u64 limit1;
41 #define SUN5_LIMIT_ENABLE 0x80000000
42 #define SUN5_LIMIT_TOZERO 0x40000000
43 #define SUN5_LIMIT_ZRESTART 0x20000000
44 #define SUN5_LIMIT_CMASK 0x1fffffff
46 /* Given a HZ value, set the limit register to so that the timer IRQ
47 * gets delivered that often.
49 #define SUN5_HZ_TO_LIMIT(__hz) (1000000/(__hz))
51 #ifdef __SMP__
52 extern unsigned long timer_tick_offset;
53 extern void timer_tick_interrupt(struct pt_regs *);
54 #endif
56 #endif /* _SPARC64_TIMER_H */