include/asm-sparc64/sysio.h

   1 /* $Id: sysio.h,v 1.9 1999/08/30 10:15:03 davem Exp $
   2  * sysio.h: UltraSparc sun5 specific SBUS definitions.
   3  *
   4  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef __SPARC64_SYSIO_H
   8 #define __SPARC64_SYSIO_H
   9
  10 #include <linux/types.h>
  11
  12 /* SUN5 SYSIO Register Set, one per controller probed. */
  13 struct sysio_regs {
  14 /*0x0000*/      volatile u64    upa_id;         /* SYSIO UPA Port ID Register   */
  15 /*0x0008*/      volatile u64    upa_cfg;        /* SYSIO UPA Config Register    */
  16 /*0x0010*/      volatile u64    control;        /* SYSIO Control Register       */
  17 /*0x0018*/      volatile u64    _unused1;
  18 /*0x0020*/      volatile u64    ecc_control;    /* ECC Control Register         */
  19 /*0x0028*/      volatile u64    _unused2;
  20
  21                 /* Uncorrectable Error Fault Registers */
  22 /*0x0030*/      volatile u64    ue_afsr;        /* UE Async Fault Status        */
  23 /*0x0038*/      volatile u64    ue_afar;        /* UE Async Fault Address       */
  24
  25                 /* Correctable Error Fault Registers */
  26 /*0x0040*/      volatile u64    ce_afsr;        /* CE Async Fault Status        */
  27 /*0x0048*/      volatile u64    ce_afar;        /* CE Async Fault Address       */
  28
  29                 volatile u64    __pad0[0x16];
  30
  31                 /* Performance Monitoring Registers */
  32 /*0x0100*/      volatile u64    pmon_control;
  33 /*0x0108*/      volatile u64    pmon_counter;
  34
  35                 volatile u64    __pad1[0x3de];
  36
  37                 /* SBUS Module Registers */
  38 /*0x2000*/      volatile u64    sbus_control;   /* SBUS Control Register        */
  39 /*0x2008*/      volatile u64    _unused3;
  40 /*0x2010*/      volatile u64    sbus_afsr;      /* SBUS Async Fault Status      */
  41 /*0x2018*/      volatile u64    sbus_afar;      /* SBUS Async Fault Address     */
  42
  43                 /* SBUS Slot Configuration Registers.
  44                  * On Fusion/Electron/Pulsar desktops/servers slots 4-->6
  45                  * are for on-board devices, in particular for Electron/Pulsar
  46                  * they are:
  47                  *
  48                  *      slot 4) Audio
  49                  *      slot 5) MACIO
  50                  *      slot 6) SLAVIO
  51                  *
  52                  * On Sunfire/Starfire/Wildfire enterprise boxen these upper slots
  53                  * are unused.
  54                  */
  55 /*0x2020*/      volatile u64    sbus_s0cfg;     /* SBUS Slot 0 Config           */
  56 /*0x2028*/      volatile u64    sbus_s1cfg;     /* SBUS Slot 1 Config           */
  57 /*0x2030*/      volatile u64    sbus_s2cfg;     /* SBUS Slot 2 Config           */
  58 /*0x2038*/      volatile u64    sbus_s3cfg;     /* SBUS Slot 3 Config           */
  59 /*0x2040*/      volatile u64    sbus_s4cfg;     /* SBUS Slot 4 Config           */
  60 /*0x2048*/      volatile u64    sbus_s5cfg;     /* SBUS Slot 5 Config           */
  61 /*0x2050*/      volatile u64    sbus_s6cfg;     /* SBUS Slot 6 Config           */
  62
  63                 volatile u64    __pad2[0x75];
  64
  65                 /* SBUS IOMMU lives here */
  66 /*0x2400*/      volatile u64    iommu_control;  /* IOMMU Control                */
  67 /*0x2408*/      volatile u64    iommu_tsbbase;  /* IOMMU TSB Base               */
  68 /*0x2410*/      volatile u64    iommu_flush;    /* IOMMU Flush Register         */
  69
  70                 volatile u64    __pad3[0x7d];
  71
  72                 /* SBUS/IOMMU Streaming Buffer Registers */
  73 /*0x2800*/      volatile u64    sbuf_control;   /* StrBuffer Control            */
  74 /*0x2808*/      volatile u64    sbuf_pflush;    /* StrBuffer Page Flush         */
  75 /*0x2810*/      volatile u64    sbuf_fsync;     /* StrBuffer Flush Synchronization Reg */
  76
  77                 volatile u64    __pad4[0x7d];
  78
  79                 /* Interrupt mapping/control registers */
  80 /*0x2c00*/      volatile u32    _uim0, imap_slot0;      /* SBUS Slot 0 Int Mapping */
  81 /*0x2c08*/      volatile u32    _uim1, imap_slot1;      /* SBUS Slot 1 Int Mapping */
  82 /*0x2c10*/      volatile u32    _uim2, imap_slot2;      /* SBUS Slot 2 Int Mapping */
  83 /*0x2c18*/      volatile u32    _uim3, imap_slot3;      /* SBUS Slot 3 Int Mapping */
  84
  85                 /* Interrupt Retry Timer. */
  86 /*0x2c20*/      volatile u32    _irpad, irq_retry;
  87
  88                 volatile u64    __pad5[0x7b];
  89
  90                 /* The following are only used on Fusion/Electron/Pulsar
  91                  * desktop systems, they mean nothing on Sunfire/Starfire/Wildfire
  92                  */
  93 /*0x3000*/      volatile u32    _uis, imap_scsi;        /* SCSI Int Mapping     */
  94 /*0x3008*/      volatile u32    _uie, imap_eth;         /* Ethernet Int Mapping */
  95 /*0x3010*/      volatile u32    _uip, imap_bpp;         /* Parallel Port Int Mapping */
  96 /*0x3018*/      volatile u32    _uia, imap_audio;       /* Audio Int Mapping    */
  97 /*0x3020*/      volatile u32    _uipf, imap_pfail;      /* Power Fail Int Mapping */
  98 /*0x3028*/      volatile u32    _uik, imap_kms;         /* Kbd/Ms/Serial Int Mapping */
  99 /*0x3030*/      volatile u32    _uif, imap_flpy;        /* Floppy Int Mapping   */
 100 /*0x3038*/      volatile u32    _uishw, imap_shw;       /* Spare HW Int Mapping */
 101 /*0x3040*/      volatile u32    _uikbd, imap_kbd;       /* Kbd Only Int Mapping */
 102 /*0x3048*/      volatile u32    _uims, imap_ms;         /* Mouse Only Int Mapping */
 103 /*0x3050*/      volatile u32    _uiser, imap_ser;       /* Serial Only Int Mapping */
 104 /*0x3058*/      volatile u64    _imap_unused;
 105 /*0x3060*/      volatile u32    _uit0, imap_tim0;       /* Timer 0 Int Mapping  */
 106 /*0x3068*/      volatile u32    _uit1, imap_tim1;       /* Timer 1 Int Mapping  */
 107 /*0x3070*/      volatile u32    _uiue, imap_ue;         /* UE Int Mapping       */
 108 /*0x3078*/      volatile u32    _uice, imap_ce;         /* CE Int Mapping       */
 109 /*0x3080*/      volatile u32    _uisbe, imap_sberr;     /* SBUS Err Int Mapping */
 110 /*0x3088*/      volatile u32    _uipm, imap_pmgmt;      /* Power Mgmt Int Mapping */
 111 /*0x3090*/      volatile u32    _uigfx, imap_gfx;       /* OB Graphics Int Mapping */
 112 /*0x3098*/      volatile u32    _uieupa, imap_eupa;     /* UPA Expansion Int Mapping */
 113
 114                 volatile u64    __pad6[0x6c];
 115
 116                 /* Interrupt Clear Registers */
 117 /*0x3400*/      volatile u32    __ucu0, iclr_unused0;
 118 /*0x3408*/      volatile u32    _ucs0, iclr_slot0;
 119                 volatile u64    __pad7[0x7];
 120 /*0x3448*/      volatile u32    _ucs1, iclr_slot1;
 121                 volatile u64    __pad8[0x7];
 122 /*0x3488*/      volatile u32    _ucs2, iclr_slot2;
 123                 volatile u64    __pad9[0x7];
 124 /*0x34c8*/      volatile u32    _ucs3, iclr_slot3;
 125                 volatile u64    __pad10[0x66];
 126 /*0x3800*/      volatile u32    _ucscsi, iclr_scsi;
 127 /*0x3808*/      volatile u32    _uceth, iclr_eth;
 128 /*0x3810*/      volatile u32    _ucbpp, iclr_bpp;
 129 /*0x3818*/      volatile u32    _ucaudio, iclr_audio;
 130 /*0x3820*/      volatile u32    _ucpfail, iclr_pfail;
 131 /*0x3828*/      volatile u32    _uckms, iclr_kms;
 132 /*0x3830*/      volatile u32    _ucflpy, iclr_flpt;
 133 /*0x3838*/      volatile u32    _ucshw, iclr_shw;
 134 /*0x3840*/      volatile u32    _uckbd, iclr_kbd;
 135 /*0x3848*/      volatile u32    _ucms, iclr_ms;
 136 /*0x3850*/      volatile u32    _ucser, iclr_ser;
 137 /*0x3858*/      volatile u64    iclr_unused1;
 138 /*0x3860*/      volatile u32    _uctim0, iclr_tim0;
 139 /*0x3868*/      volatile u32    _uctim1, iclr_tim1;
 140 /*0x3870*/      volatile u32    _ucue, iclr_ue;
 141 /*0x3878*/      volatile u32    _ucce, iclr_ce;
 142 /*0x3880*/      volatile u32    _ucserr, iclr_serr;
 143 /*0x3888*/      volatile u32    _ucpmgmt, iclr_pmgmt;
 144
 145                 volatile u64    __pad11[0x6e];
 146
 147                 /* Counters/Timers */
 148 /*0x3c00*/      volatile u64    tim0_cnt;
 149 /*0x3c08*/      volatile u64    tim0_lim;
 150 /*0x3c10*/      volatile u64    tim1_cnt;
 151 /*0x3c18*/      volatile u64    tim1_lim;
 152
 153                 volatile u64    __pad12[0x7c];
 154
 155                 /* DMA Scoreboard Diagnostic Registers */
 156 /*0x4000*/      volatile u64    dscore_reg0;    /* DMA Scoreboard Diag Reg 0    */
 157 /*0x4008*/      volatile u64    dscore_reg1;    /* DMA Scoreboard Diag Reg 1    */
 158
 159                 volatile u64    __pad13[0x7e];
 160
 161                 /* SBUS IOMMU Diagnostic Registers */
 162 /*0x4400*/      volatile u64    sbus_vdiag;     /* SBUS VADDR Diagnostic Register */
 163 /*0x4408*/      volatile u64    sbus_tcompare;  /* SBUS IOMMU TLB Tag Compare     */
 164
 165                 volatile u64    __pad14[0x1e];
 166
 167                 /* More IOMMU diagnostic things */
 168 /*0x4500*/      volatile u64    iommu_lru[16];  /* IOMMU LRU Queue Diagnostic Access */
 169 /*0x4580*/      volatile u64    iommu_tag[16];  /* IOMMU TLB Tag Diagnostic Access   */
 170 /*0x4600*/      volatile u64    iommu_data[32]; /* IOMMU TLB Data RAM Diag Access    */
 171
 172                 volatile u64    __pad15[0x20];
 173
 174                 /* Interrupt State Diagnostics */
 175 /*0x4800*/      volatile u64    sbus_istate;
 176 /*0x4808*/      volatile u64    obio_istate;
 177
 178                 volatile u64    __pad16[0xfe];
 179
 180                 /* Streaming Buffer Diagnostic Area */
 181 /*0x5000*/      volatile u64    sbuf_data[128]; /* StrBuffer Data Ram Diagnostic */
 182 /*0x5400*/      volatile u64    sbuf_errs[128]; /* StrBuffer Error Status Diagnostics */
 183 /*0x5800*/      volatile u64    sbuf_ptag[16];  /* StrBuffer Page Tag Diagnostics */
 184 /*0x5880*/      volatile u64    _unusedXXX[16];
 185 /*0x5900*/      volatile u64    sbuf_ltag[16];  /* StrBuffer Line Tag Diagnostics */
 186 };
 187
 188 /* SYSIO UPA Port ID */
 189 #define SYSIO_UPPID_FESC        0xff00000000000000 /* FCode escape, 0xfc           */
 190 #define SYSIO_UPPID_RESV1       0x00fffff800000000 /* Reserved                     */
 191 #define SYSIO_UPPID_ENV         0x0000000400000000 /* Cannot generate ECC          */
 192 #define SYSIO_UPPID_ORD         0x0000000200000000 /* One Outstanding Read         */
 193 #define SYSIO_UPPID_RESV2       0x0000000180000000 /* Reserved                     */
 194 #define SYSIO_UPPID_PDQ         0x000000007e000000 /* Data Queue size              */
 195 #define SYSIO_UPPID_PRQ         0x0000000001e00000 /* Request Queue size           */
 196 #define SYSIO_UPPID_UCAP        0x00000000001f0000 /* UPA Capabilities             */
 197 #define SYSIO_UPPID_JEDEC       0x000000000000ffff /* JEDEC ID for SYSIO           */
 198
 199 /* SYSIO UPA Configuration Register */
 200 #define SYSIO_UPCFG_RESV        0xffffffffffffff00 /* Reserved                     */
 201 #define SYSIO_UPCFG_SCIQ1       0x00000000000000f0 /* Unused, always zero          */
 202 #define SYSIO_UPCFG_SCIQ2       0x000000000000000f /* Requests Queue size (0x2)    */
 203
 204 /* SYSIO Control Register */
 205 #define SYSIO_CONTROL_IMPL      0xf000000000000000 /* Implementation of this SYSIO */
 206 #define SYSIO_CONTROL_VER       0x0f00000000000000 /* Version of this SYSIO        */
 207 #define SYSIO_CONTROL_MID       0x00f8000000000000 /* UPA Module ID of SYSIO       */
 208 #define SYSIO_CONTROL_IGN       0x0007c00000000000 /* Interrupt Group Number       */
 209 #define SYSIO_CONTROL_RESV      0x00003ffffffffff0 /* Reserved                     */
 210 #define SYSIO_CONTROL_APCKEN    0x0000000000000008 /* Address Parity Check Enable  */
 211 #define SYSIO_CONTROL_APERR     0x0000000000000004 /* Incoming System Addr Parerr  */
 212 #define SYSIO_CONTROL_IAP       0x0000000000000002 /* Invert UPA Parity            */
 213 #define SYSIO_CONTROL_MODE      0x0000000000000001 /* SYSIO clock mode             */
 214
 215 /* SYSIO ECC Control Register */
 216 #define SYSIO_ECNTRL_ECCEN      0x8000000000000000 /* Enable ECC Checking          */
 217 #define SYSIO_ECNTRL_UEEN       0x4000000000000000 /* Enable UE Interrupts         */
 218 #define SYSIO_ECNTRL_CEEN       0x2000000000000000 /* Enable CE Interrupts         */
 219
 220 /* Uncorrectable Error AFSR, AFAR holds low 40bits of faulting physical address. */
 221 #define SYSIO_UEAFSR_PPIO       0x8000000000000000 /* Primary PIO is cause         */
 222 #define SYSIO_UEAFSR_PDRD       0x4000000000000000 /* Primary DVMA read is cause   */
 223 #define SYSIO_UEAFSR_PDWR       0x2000000000000000 /* Primary DVMA write is cause  */
 224 #define SYSIO_UEAFSR_SPIO       0x1000000000000000 /* Secondary PIO is cause       */
 225 #define SYSIO_UEAFSR_SDRD       0x0800000000000000 /* Secondary DVMA read is cause */
 226 #define SYSIO_UEAFSR_SDWR       0x0400000000000000 /* Secondary DVMA write is cause*/
 227 #define SYSIO_UEAFSR_RESV1      0x03ff000000000000 /* Reserved                     */
 228 #define SYSIO_UEAFSR_DOFF       0x0000e00000000000 /* Doubleword Offset            */
 229 #define SYSIO_UEAFSR_SIZE       0x00001c0000000000 /* Bad transfer size is 2**SIZE */
 230 #define SYSIO_UEAFSR_MID        0x000003e000000000 /* UPA MID causing the fault    */
 231 #define SYSIO_UEAFSR_RESV2      0x0000001fffffffff /* Reserved                     */
 232
 233 /* Correctable Error AFSR, AFAR holds low 40bits of faulting physical address. */
 234 #define SYSIO_CEAFSR_PPIO       0x8000000000000000 /* Primary PIO is cause         */
 235 #define SYSIO_CEAFSR_PDRD       0x4000000000000000 /* Primary DVMA read is cause   */
 236 #define SYSIO_CEAFSR_PDWR       0x2000000000000000 /* Primary DVMA write is cause  */
 237 #define SYSIO_CEAFSR_SPIO       0x1000000000000000 /* Secondary PIO is cause       */
 238 #define SYSIO_CEAFSR_SDRD       0x0800000000000000 /* Secondary DVMA read is cause */
 239 #define SYSIO_CEAFSR_SDWR       0x0400000000000000 /* Secondary DVMA write is cause*/
 240 #define SYSIO_CEAFSR_RESV1      0x0300000000000000 /* Reserved                     */
 241 #define SYSIO_CEAFSR_ESYND      0x00ff000000000000 /* Syndrome Bits                */
 242 #define SYSIO_CEAFSR_DOFF       0x0000e00000000000 /* Double Offset                */
 243 #define SYSIO_CEAFSR_SIZE       0x00001c0000000000 /* Bad transfer size is 2**SIZE */
 244 #define SYSIO_CEAFSR_MID        0x000003e000000000 /* UPA MID causing the fault    */
 245 #define SYSIO_CEAFSR_RESV2      0x0000001fffffffff /* Reserved                     */
 246
 247 /* DMA Scoreboard Diagnostic Register(s) */
 248 #define SYSIO_DSCORE_VALID      0x0040000000000000 /* Entry is valid               */
 249 #define SYSIO_DSCORE_C          0x0020000000000000 /* Transaction cacheable        */
 250 #define SYSIO_DSCORE_READ       0x0010000000000000 /* Transaction was a read       */
 251 #define SYSIO_DSCORE_TAG        0x000f000000000000 /* Transaction ID               */
 252 #define SYSIO_DSCORE_ADDR       0x0000ffffffffff80 /* Transaction PADDR            */
 253 #define SYSIO_DSCORE_SIZE       0x0000000000000030 /* Transaction size             */
 254 #define SYSIO_DSCORE_SRC        0x000000000000000f /* Transaction source           */
 255
 256 /* SYSIO SBUS Control Register */
 257 #define SYSIO_SBCNTRL_IMPL      0xf000000000000000 /* Implementation               */
 258 #define SYSIO_SBCNTRL_REV       0x0f00000000000000 /* Revision                     */
 259 #define SYSIO_SBCNTRL_RESV1     0x00c0000000000000 /* Reserved                     */
 260 #define SYSIO_SBCNTRL_DPERR     0x003f000000000000 /* DMA Write Parity Error       */
 261 #define SYSIO_SBCNTRL_RESV2     0x0000800000000000 /* Reserved                     */
 262 #define SYSIO_SBCNTRL_PPERR     0x00007f0000000000 /* PIO Load Parity Error        */
 263 #define SYSIO_SBCNTRL_RESV      0x000000fffffff800 /* Reserved                     */
 264 #define SYSIO_SBCNTRL_FAST      0x0000000000000400 /* Enable Fast-SBUS mode.       */
 265 #define SYSIO_SBCNTRL_WEN       0x0000000000000200 /* Power Mgmt Wake Enable       */
 266 #define SYSIO_SBCNTRL_EEN       0x0000000000000100 /* SBUS Error Interrupt Enable  */
 267 #define SYSIO_SBCNTRL_RESV3     0x00000000000000c0 /* Reserved                     */
 268 #define SYSIO_SBCNTRL_AEN       0x000000000000003f /* SBUS DVMA Arbitration Enable */
 269
 270 /* SYSIO SBUS AFSR, AFAR holds low 40 bits of physical address causing the fault. */
 271 #define SYSIO_SBAFSR_PLE        0x8000000000000000 /* Primary Late PIO Error       */
 272 #define SYSIO_SBAFSR_PTO        0x4000000000000000 /* Primary SBUS Timeout         */
 273 #define SYSIO_SBAFSR_PBERR      0x2000000000000000 /* Primary SBUS Error ACK       */
 274 #define SYSIO_SBAFSR_SLE        0x1000000000000000 /* Secondary Late PIO Error     */
 275 #define SYSIO_SBAFSR_STO        0x0800000000000000 /* Secondary SBUS Timeout       */
 276 #define SYSIO_SBAFSR_SBERR      0x0400000000000000 /* Secondary SBUS Error ACK     */
 277 #define SYSIO_SBAFSR_RESV1      0x03ff000000000000 /* Reserved                     */
 278 #define SYSIO_SBAFSR_RD         0x0000800000000000 /* Primary was late PIO read    */
 279 #define SYSIO_SBAFSR_RESV2      0x0000600000000000 /* Reserved                     */
 280 #define SYSIO_SBAFSR_SIZE       0x00001c0000000000 /* Size of transfer             */
 281 #define SYSIO_SBAFSR_MID        0x000003e000000000 /* MID causing the error        */
 282 #define SYSIO_SBAFSR_RESV3      0x0000001fffffffff /* Reserved                     */
 283
 284 /* SYSIO SBUS Slot Configuration Register(s) */
 285 #define SYSIO_SBSCFG_RESV1      0xfffffffff8000000 /* Reserved                     */
 286 #define SYSIO_SBSCFG_SADDR      0x0000000007ff0000 /* Segment Address (PA[40:30])  */
 287 #define SYSIO_SBSCFG_CP         0x0000000000008000 /* Bypasses are cacheable       */
 288 #define SYSIO_SBSCFG_ETM        0x0000000000004000 /* Ext Transfer Mode supported  */
 289 #define SYSIO_SBSCFG_PE         0x0000000000002000 /* SBUS Parity Checking Enable  */
 290 #define SYSIO_SBSCFG_RESV2      0x0000000000001fe0 /* Reserved                     */
 291 #define SYSIO_SBSCFG_BA64       0x0000000000000010 /* 64-byte bursts supported     */
 292 #define SYSIO_SBSCFG_BA32       0x0000000000000008 /* 32-byte bursts supported     */
 293 #define SYSIO_SBSCFG_BA16       0x0000000000000004 /* 16-byte bursts supported     */
 294 #define SYSIO_SBSCFG_BA8        0x0000000000000002 /* 8-byte bursts supported      */
 295 #define SYSIO_SBSCFG_BY         0x0000000000000001 /* IOMMU Bypass Enable          */
 296
 297 /* IOMMU things defined fully in asm-sparc64/iommu.h */
 298
 299 /* Streaming Buffer Control Register */
 300 #define SYSIO_SBUFCTRL_IMPL     0xf000000000000000 /* Implementation               */
 301 #define SYSIO_SBUFCTRL_REV      0x0f00000000000000 /* Revision                     */
 302 #define SYSIO_SBUFCTRL_DE       0x0000000000000002 /* Diag Mode Enable             */
 303 #define SYSIO_SBUFCTRL_SB_EN    0x0000000000000001 /* Streaming Buffer Enable      */
 304
 305 /* Streaming Buffer Page Invalidate/Flush Register */
 306 #define SYSIO_SBUFFLUSH_ADDR    0x00000000ffffe000 /* DVMA Page to be flushed      */
 307 #define SYSIO_SBUFFLUSH_RESV    0x0000000000001fff /* Ignored bits                 */
 308
 309 /* Streaming Buffer Flush Synchronization Register */
 310 #define SYSIO_SBUFSYNC_ADDR     0x000001fffffffffc /* Physical address to update   */
 311 #define SYSIO_SBUFSYNC_RESV     0x0000000000000003 /* Ignored bits                 */
 312
 313 /* SYSIO Interrupt mapping register(s). */
 314 #define SYSIO_IMAP_VALID        0x80000000      /* This enables delivery.          */
 315 #define SYSIO_IMAP_TID          0x7c000000      /* Target ID (MID to send it to)   */
 316 #define SYSIO_IMAP_RESV         0x03fff800      /* Reserved.                       */
 317 #define SYSIO_IMAP_IGN          0x000007c0      /* Interrupt Group Number.         */
 318 #define SYSIO_IMAP_INO          0x0000003f      /* Interrupt Number Offset.        */
 319 #define SYSIO_IMAP_INR          0x000007ff      /* Interrupt # (Gfx/UPA_slave only)*/
 320
 321 /* SYSIO Interrupt clear pseudo register(s). */
 322 #define SYSIO_ICLR_IDLE         0x00000000      /* Transition to idle state.       */
 323 #define SYSIO_ICLR_TRANSMIT     0x00000001      /* Transition to transmit state.   */
 324 #define SYSIO_ICLR_RESV         0x00000002      /* Reserved.                       */
 325 #define SYSIO_ICLR_PENDING      0x00000003      /* Transition to pending state.    */
 326
 327 /* SYSIO Interrupt Retry Timer register. */
 328 #define SYSIO_IRETRY_LIMIT      0x000000ff      /* The retry interval.             */
 329
 330 /* SYSIO Interrupt State registers. */
 331 #define SYSIO_ISTATE_IDLE       0x0 /* No interrupt received or pending */
 332 #define SYSIO_ISTATE_TRANSMIT   0x1 /* Received, but IRQ not dispatched */
 333 #define SYSIO_ISTATE_ILLEGAL    0x2 /* Impossible state                 */
 334 #define SYSIO_ISTATE_PENDING    0x3 /* Received and dispatched          */
 335
 336 /* Two ways to get at the right bits, your choice... note that level
 337  * zero is illegal.  For slots 0 --> 3 the formula for the bit range
 338  * in the register is:
 339  *
 340  *      LSB     ((SBUS_SLOT X 16) + (SBUS_LEVEL X 2))
 341  *      MSB     ((SBUS_SLOT X 16) + (SBUS_LEVEL X 2)) + 1
 342  *
 343  * Thus the following macro.
 344  */
 345 #define SYSIO_SBUS_ISTATE(regval, slot, level)  \
 346         (((regval) >> (((slot) * 16) + ((level) * 2))) & 0x3)
 347
 348 #define SYSIO_SBUS_ISTATE_S0L1  0x000000000000000c /* Slot 0, level 1 */
 349 #define SYSIO_SBUS_ISTATE_S0L2  0x0000000000000030 /* Slot 0, level 2 */
 350 #define SYSIO_SBUS_ISTATE_S0L3  0x00000000000000c0 /* Slot 0, level 3 */
 351 #define SYSIO_SBUS_ISTATE_S0L4  0x0000000000000300 /* Slot 0, level 4 */
 352 #define SYSIO_SBUS_ISTATE_S0L5  0x0000000000000c00 /* Slot 0, level 5 */
 353 #define SYSIO_SBUS_ISTATE_S0L6  0x0000000000003000 /* Slot 0, level 6 */
 354 #define SYSIO_SBUS_ISTATE_S0L7  0x000000000000c000 /* Slot 0, level 7 */
 355 #define SYSIO_SBUS_ISTATE_S1L1  0x00000000000c0000 /* Slot 1, level 1 */
 356 #define SYSIO_SBUS_ISTATE_S1L2  0x0000000000300000 /* Slot 1, level 2 */
 357 #define SYSIO_SBUS_ISTATE_S1L3  0x0000000000c00000 /* Slot 1, level 3 */
 358 #define SYSIO_SBUS_ISTATE_S1L4  0x0000000003000000 /* Slot 1, level 4 */
 359 #define SYSIO_SBUS_ISTATE_S1L5  0x000000000c000000 /* Slot 1, level 5 */
 360 #define SYSIO_SBUS_ISTATE_S1L6  0x0000000030000000 /* Slot 1, level 6 */
 361 #define SYSIO_SBUS_ISTATE_S1L7  0x00000000c0000000 /* Slot 1, level 7 */
 362 #define SYSIO_SBUS_ISTATE_S2L1  0x0000000c00000000 /* Slot 2, level 1 */
 363 #define SYSIO_SBUS_ISTATE_S2L2  0x0000003000000000 /* Slot 2, level 2 */
 364 #define SYSIO_SBUS_ISTATE_S2L3  0x000000c000000000 /* Slot 2, level 3 */
 365 #define SYSIO_SBUS_ISTATE_S2L4  0x0000030000000000 /* Slot 2, level 4 */
 366 #define SYSIO_SBUS_ISTATE_S2L5  0x00000c0000000000 /* Slot 2, level 5 */
 367 #define SYSIO_SBUS_ISTATE_S2L6  0x0000300000000000 /* Slot 2, level 6 */
 368 #define SYSIO_SBUS_ISTATE_S2L7  0x0000c00000000000 /* Slot 2, level 7 */
 369 #define SYSIO_SBUS_ISTATE_S3L1  0x000c000000000000 /* Slot 3, level 1 */
 370 #define SYSIO_SBUS_ISTATE_S3L2  0x0030000000000000 /* Slot 3, level 2 */
 371 #define SYSIO_SBUS_ISTATE_S3L3  0x00c0000000000000 /* Slot 3, level 3 */
 372 #define SYSIO_SBUS_ISTATE_S3L4  0x0300000000000000 /* Slot 3, level 4 */
 373 #define SYSIO_SBUS_ISTATE_S3L5  0x0c00000000000000 /* Slot 3, level 5 */
 374 #define SYSIO_SBUS_ISTATE_S3L6  0x3000000000000000 /* Slot 3, level 6 */
 375 #define SYSIO_SBUS_ISTATE_S3L7  0xc000000000000000 /* Slot 3, level 7 */
 376
 377 /* For OBIO devices things are a bit different, you just have to know what
 378  * you are looking for.
 379  */
 380 #define SYSIO_OBIO_ISTATE_SCSI  0x0000000000000003 /* Scsi              */
 381 #define SYSIO_OBIO_ISTATE_ETH   0x000000000000000c /* Ethernet          */
 382 #define SYSIO_OBIO_ISTATE_PP    0x0000000000000030 /* Parallel Port     */
 383 #define SYSIO_OBIO_ISTATE_AUDIO 0x00000000000000c0 /* Sun Audio         */
 384 #define SYSIO_OBIO_ISTATE_PFAIL 0x0000000000000300 /* Power Fail        */
 385 #define SYSIO_OBIO_ISTATE_KBMS  0x0000000000000c00 /* kbd/mouse/serial  */
 386 #define SYSIO_OBIO_ISTATE_FLPY  0x0000000000003000 /* Floppy Controller */
 387 #define SYSIO_OBIO_ISTATE_SPHW  0x000000000000c000 /* Spare HW          */
 388 #define SYSIO_OBIO_ISTATE_KBD   0x0000000000030000 /* Keyboard          */
 389 #define SYSIO_OBIO_ISTATE_MS    0x00000000000c0000 /* Mouse             */
 390 #define SYSIO_OBIO_ISTATE_SER   0x0000000000300000 /* Serial            */
 391 #define SYSIO_OBIO_ISTATE_TIM0  0x0000000000c00000 /* Timer 0           */
 392 #define SYSIO_OBIO_ISTATE_TIM1  0x0000000003000000 /* Timer 1           */
 393 #define SYSIO_OBIO_ISTATE_UE    0x000000000c000000 /* Uncorrectable Err */
 394 #define SYSIO_OBIO_ISTATE_CE    0x0000000030000000 /* Correctable Err   */
 395 #define SYSIO_OBIO_ISTATE_SERR  0x00000000c0000000 /* SBUS Err          */
 396 #define SYSIO_OBIO_ISTATE_PMGMT 0x0000000300000000 /* Power Management  */
 397 #define SYSIO_OBIO_ISTATE_RSVI  0x0000000400000000 /* Reserved Int      */
 398 #define SYSIO_OBIO_ISTATE_EUPA  0x0000000800000000 /* Expansion UPA (creator) */
 399 #define SYSIO_OBIO_ISTATE_RESV  0xfffffff000000000 /* Reserved...       */
 400
 401 /* SYSIO Counter and Limit registers are documented in timer.h as these
 402  * are generic SUN4U things.
 403  */
 404
 405 /* SYSIO Performance Monitor Control register. */
 406 #define SYSIO_PCNTRL_CLR1       0x0000000000008000 /* Clear SEL1 counter              */
 407 #define SYSIO_PCNTRL_SEL1_SDR   0x0000000000000000 /* SEL1: Streaming DVMA reads      */
 408 #define SYSIO_PCNTRL_SEL1_SDW   0x0000000000000100 /* SEL1: Streaming DVMA writes     */
 409 #define SYSIO_PCNTRL_SEL1_CDR   0x0000000000000200 /* SEL1: Consistent DVMA reads     */
 410 #define SYSIO_PCNTRL_SEL1_CDW   0x0000000000000300 /* SEL1: Consistent DVMA writes    */
 411 #define SYSIO_PCNTRL_SEL1_TMISS 0x0000000000000400 /* SEL1: IOMMU TLB misses          */
 412 #define SYSIO_PCNTRL_SEL1_SMISS 0x0000000000000500 /* SEL1: Streaming Buffer misses   */
 413 #define SYSIO_PCNTRL_SEL1_SDC   0x0000000000000600 /* SEL1: SBUS dvma cycles          */
 414 #define SYSIO_PCNTRL_SEL1_DB    0x0000000000000700 /* SEL1: DVMA bytes transferred    */
 415 #define SYSIO_PCNTRL_SEL1_IRQ   0x0000000000000800 /* SEL1: Interrupts                */
 416 #define SYSIO_PCNTRL_SEL1_UIN   0x0000000000000900 /* SEL1: UPA IRQ NACK's            */
 417 #define SYSIO_PCNTRL_SEL1_PRD   0x0000000000000a00 /* SEL1: PIO reads                 */
 418 #define SYSIO_PCNTRL_SEL1_PWR   0x0000000000000b00 /* SEL1: PIO writes                */
 419 #define SYSIO_PCNTRL_SEL1_SRR   0x0000000000000c00 /* SEL1: SBUS reruns               */
 420 #define SYSIO_PCNTRL_SEL1_SPIO  0x0000000000000d00 /* SEL1: SYSIO PIO cycles          */
 421 #define SYSIO_PCNTRL_CLR0       0x0000000000000080 /* Clear SEL0 counter              */
 422 #define SYSIO_PCNTRL_SEL0_SDR   0x0000000000000000 /* SEL0: Streaming DVMA reads      */
 423 #define SYSIO_PCNTRL_SEL0_SDW   0x0000000000000001 /* SEL0: Streaming DVMA writes     */
 424 #define SYSIO_PCNTRL_SEL0_CDR   0x0000000000000002 /* SEL0: Consistent DVMA reads     */
 425 #define SYSIO_PCNTRL_SEL0_CDW   0x0000000000000003 /* SEL0: Consistent DVMA writes    */
 426 #define SYSIO_PCNTRL_SEL0_TMISS 0x0000000000000004 /* SEL0: IOMMU TLB misses          */
 427 #define SYSIO_PCNTRL_SEL0_SMISS 0x0000000000000005 /* SEL0: Streaming Buffer misses   */
 428 #define SYSIO_PCNTRL_SEL0_SDC   0x0000000000000006 /* SEL0: SBUS dvma cycles          */
 429 #define SYSIO_PCNTRL_SEL0_DB    0x0000000000000007 /* SEL0: DVMA bytes transferred    */
 430 #define SYSIO_PCNTRL_SEL0_IRQ   0x0000000000000008 /* SEL0: Interrupts                */
 431 #define SYSIO_PCNTRL_SEL0_UIN   0x0000000000000009 /* SEL0: UPA IRQ NACK's            */
 432 #define SYSIO_PCNTRL_SEL0_PRD   0x000000000000000a /* SEL0: PIO reads                 */
 433 #define SYSIO_PCNTRL_SEL0_PWR   0x000000000000000b /* SEL0: PIO writes                */
 434 #define SYSIO_PCNTRL_SEL0_SRR   0x000000000000000c /* SEL0: SBUS reruns               */
 435 #define SYSIO_PCNTRL_SEL0_SPIO  0x000000000000000d /* SEL0: SYSIO PIO cycles          */
 436
 437 /* SYSIO Performance Monitor Counter register. */
 438 #define SYSIO_PCOUNT_CNT0       0xffffffff00000000 /* Counter zero  */
 439 #define SYSIO_PCOUNT_CNT1       0x00000000ffffffff /* Counter one  */
 440
 441 #endif /* !(__SPARC64_SYSIO_H) */