include/asm-sparc64/sab82532.h

   1 /* $Id: sab82532.h,v 1.5 1999/05/12 11:21:22 davem Exp $
   2  * sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
   3  *
   4  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   5  */
   6
   7 #ifndef _SPARC64_SAB82532_H
   8 #define _SPARC64_SAB82532_H
   9
  10 #include <linux/types.h>
  11 #include <linux/serial.h>
  12
  13 struct sab82532_async_rd_regs {
  14         u8      rfifo[0x20];    /* Receive FIFO                         */
  15         u8      star;           /* Status Register                      */
  16         u8      __pad1;
  17         u8      mode;           /* Mode Register                        */
  18         u8      timr;           /* Timer Register                       */
  19         u8      xon;            /* XON Character                        */
  20         u8      xoff;           /* XOFF Character                       */
  21         u8      tcr;            /* Termination Character Register       */
  22         u8      dafo;           /* Data Format                          */
  23         u8      rfc;            /* RFIFO Control Register               */
  24         u8      __pad2;
  25         u8      rbcl;           /* Receive Byte Count Low               */
  26         u8      rbch;           /* Receive Byte Count High              */
  27         u8      ccr0;           /* Channel Configuration Register 0     */
  28         u8      ccr1;           /* Channel Configuration Register 1     */
  29         u8      ccr2;           /* Channel Configuration Register 2     */
  30         u8      ccr3;           /* Channel Configuration Register 3     */
  31         u8      __pad3[4];
  32         u8      vstr;           /* Version Status Register              */
  33         u8      __pad4[3];
  34         u8      gis;            /* Global Interrupt Status              */
  35         u8      ipc;            /* Interrupt Port Configuration         */
  36         u8      isr0;           /* Interrupt Status 0                   */
  37         u8      isr1;           /* Interrupt Status 1                   */
  38         u8      pvr;            /* Port Value Register                  */
  39         u8      pis;            /* Port Interrupt Status                */
  40         u8      pcr;            /* Port Configuration Register          */
  41         u8      ccr4;           /* Channel Configuration Register 4     */
  42 };
  43
  44 struct sab82532_async_wr_regs {
  45         u8      xfifo[0x20];    /* Transmit FIFO                        */
  46         u8      cmdr;           /* Command Register                     */
  47         u8      __pad1;
  48         u8      mode;
  49         u8      timr;
  50         u8      xon;
  51         u8      xoff;
  52         u8      tcr;
  53         u8      dafo;
  54         u8      rfc;
  55         u8      __pad2;
  56         u8      xbcl;           /* Transmit Byte Count Low              */
  57         u8      xbch;           /* Transmit Byte Count High             */
  58         u8      ccr0;
  59         u8      ccr1;
  60         u8      ccr2;
  61         u8      ccr3;
  62         u8      tsax;           /* Time-Slot Assignment Reg. Transmit   */
  63         u8      tsar;           /* Time-Slot Assignment Reg. Receive    */
  64         u8      xccr;           /* Transmit Channel Capacity Register   */
  65         u8      rccr;           /* Receive Channel Capacity Register    */
  66         u8      bgr;            /* Baud Rate Generator Register         */
  67         u8      tic;            /* Transmit Immediate Character         */
  68         u8      mxn;            /* Mask XON Character                   */
  69         u8      mxf;            /* Mask XOFF Character                  */
  70         u8      iva;            /* Interrupt Vector Address             */
  71         u8      ipc;
  72         u8      imr0;           /* Interrupt Mask Register 0            */
  73         u8      imr1;           /* Interrupt Mask Register 1            */
  74         u8      pvr;
  75         u8      pim;            /* Port Interrupt Mask                  */
  76         u8      pcr;
  77         u8      ccr4;
  78 };
  79
  80 struct sab82532_async_rw_regs { /* Read/Write registers                 */
  81         u8      __pad1[0x20];
  82         u8      __pad2;
  83         u8      __pad3;
  84         u8      mode;
  85         u8      timr;
  86         u8      xon;
  87         u8      xoff;
  88         u8      tcr;
  89         u8      dafo;
  90         u8      rfc;
  91         u8      __pad4;
  92         u8      __pad5;
  93         u8      __pad6;
  94         u8      ccr0;
  95         u8      ccr1;
  96         u8      ccr2;
  97         u8      ccr3;
  98         u8      __pad7;
  99         u8      __pad8;
 100         u8      __pad9;
 101         u8      __pad10;
 102         u8      __pad11;
 103         u8      __pad12;
 104         u8      __pad13;
 105         u8      __pad14;
 106         u8      __pad15;
 107         u8      ipc;
 108         u8      __pad16;
 109         u8      __pad17;
 110         u8      pvr;
 111         u8      __pad18;
 112         u8      pcr;
 113         u8      ccr4;
 114 };
 115
 116 union sab82532_async_regs {
 117         __volatile__ struct sab82532_async_rd_regs      r;
 118         __volatile__ struct sab82532_async_wr_regs      w;
 119         __volatile__ struct sab82532_async_rw_regs      rw;
 120 };
 121
 122 #define NR_PORTS                         2
 123
 124 union sab82532_irq_status {
 125         unsigned short                   stat;
 126         struct {
 127                 unsigned char            isr0;
 128                 unsigned char            isr1;
 129         } sreg;
 130 };
 131
 132 struct sab82532 {
 133         int                              magic;
 134         int                              baud_base;
 135         union sab82532_async_regs       *regs;
 136         int                              irq;
 137         int                              flags;         /* defined in tty.h */
 138         int                              type;          /* SAB82532 version */
 139         struct tty_struct               *tty;
 140         int                              read_status_mask;
 141         int                              ignore_status_mask;
 142         int                              timeout;
 143         int                              xmit_fifo_size;
 144         int                              recv_fifo_size;
 145         int                              custom_divisor;
 146         int                              baud;
 147         int                              x_char;
 148         int                              close_delay;
 149         unsigned short                   closing_wait;
 150         unsigned short                   closing_wait2;
 151         int                              all_sent;
 152         int                              is_console;
 153         unsigned char                    interrupt_mask0;
 154         unsigned char                    interrupt_mask1;
 155         unsigned char                    pvr_dtr_bit;
 156         unsigned char                    pvr_dsr_bit;
 157         unsigned char                    dcd;
 158         unsigned char                    cts;
 159         unsigned char                    dsr;
 160         unsigned long                    event;
 161         unsigned long                    last_active;
 162         int                              line;
 163         int                              count;
 164         int                              blocked_open;
 165         long                             session;
 166         long                             pgrp;
 167         unsigned char                   *xmit_buf;
 168         int                              xmit_head;
 169         int                              xmit_tail;
 170         int                              xmit_cnt;
 171         struct tq_struct                 tqueue;
 172         struct tq_struct                 tqueue_hangup;
 173         struct async_icount              icount;
 174         struct termios                   normal_termios;
 175         struct termios                   callout_termios;
 176         wait_queue_head_t                open_wait;
 177         wait_queue_head_t                close_wait;
 178         wait_queue_head_t                delta_msr_wait;
 179         struct sab82532                 *next;
 180         struct sab82532                 *prev;
 181 };
 182
 183
 184 /* RFIFO Status Byte */
 185 #define SAB82532_RSTAT_PE               0x80
 186 #define SAB82532_RSTAT_FE               0x40
 187 #define SAB82532_RSTAT_PARITY           0x01
 188
 189 /* Status Register (STAR) */
 190 #define SAB82532_STAR_XDOV              0x80
 191 #define SAB82532_STAR_XFW               0x40
 192 #define SAB82532_STAR_RFNE              0x20
 193 #define SAB82532_STAR_FCS               0x10
 194 #define SAB82532_STAR_TEC               0x08
 195 #define SAB82532_STAR_CEC               0x04
 196 #define SAB82532_STAR_CTS               0x02
 197
 198 /* Command Register (CMDR) */
 199 #define SAB82532_CMDR_RMC               0x80
 200 #define SAB82532_CMDR_RRES              0x40
 201 #define SAB82532_CMDR_RFRD              0x20
 202 #define SAB82532_CMDR_STI               0x10
 203 #define SAB82532_CMDR_XF                0x08
 204 #define SAB82532_CMDR_XRES              0x01
 205
 206 /* Mode Register (MODE) */
 207 #define SAB82532_MODE_FRTS              0x40
 208 #define SAB82532_MODE_FCTS              0x20
 209 #define SAB82532_MODE_FLON              0x10
 210 #define SAB82532_MODE_RAC               0x08
 211 #define SAB82532_MODE_RTS               0x04
 212 #define SAB82532_MODE_TRS               0x02
 213 #define SAB82532_MODE_TLP               0x01
 214
 215 /* Timer Register (TIMR) */
 216 #define SAB82532_TIMR_CNT_MASK          0xe0
 217 #define SAB82532_TIMR_VALUE_MASK        0x1f
 218
 219 /* Data Format (DAFO) */
 220 #define SAB82532_DAFO_XBRK              0x40
 221 #define SAB82532_DAFO_STOP              0x20
 222 #define SAB82532_DAFO_PAR_SPACE         0x00
 223 #define SAB82532_DAFO_PAR_ODD           0x08
 224 #define SAB82532_DAFO_PAR_EVEN          0x10
 225 #define SAB82532_DAFO_PAR_MARK          0x18
 226 #define SAB82532_DAFO_PARE              0x04
 227 #define SAB82532_DAFO_CHL8              0x00
 228 #define SAB82532_DAFO_CHL7              0x01
 229 #define SAB82532_DAFO_CHL6              0x02
 230 #define SAB82532_DAFO_CHL5              0x03
 231
 232 /* RFIFO Control Register (RFC) */
 233 #define SAB82532_RFC_DPS                0x40
 234 #define SAB82532_RFC_DXS                0x20
 235 #define SAB82532_RFC_RFDF               0x10
 236 #define SAB82532_RFC_RFTH_1             0x00
 237 #define SAB82532_RFC_RFTH_4             0x04
 238 #define SAB82532_RFC_RFTH_16            0x08
 239 #define SAB82532_RFC_RFTH_32            0x0c
 240 #define SAB82532_RFC_TCDE               0x01
 241
 242 /* Received Byte Count High (RBCH) */
 243 #define SAB82532_RBCH_DMA               0x80
 244 #define SAB82532_RBCH_CAS               0x20
 245
 246 /* Transmit Byte Count High (XBCH) */
 247 #define SAB82532_XBCH_DMA               0x80
 248 #define SAB82532_XBCH_CAS               0x20
 249 #define SAB82532_XBCH_XC                0x10
 250
 251 /* Channel Configuration Register 0 (CCR0) */
 252 #define SAB82532_CCR0_PU                0x80
 253 #define SAB82532_CCR0_MCE               0x40
 254 #define SAB82532_CCR0_SC_NRZ            0x00
 255 #define SAB82532_CCR0_SC_NRZI           0x08
 256 #define SAB82532_CCR0_SC_FM0            0x10
 257 #define SAB82532_CCR0_SC_FM1            0x14
 258 #define SAB82532_CCR0_SC_MANCH          0x18
 259 #define SAB82532_CCR0_SM_HDLC           0x00
 260 #define SAB82532_CCR0_SM_SDLC_LOOP      0x01
 261 #define SAB82532_CCR0_SM_BISYNC         0x02
 262 #define SAB82532_CCR0_SM_ASYNC          0x03
 263
 264 /* Channel Configuration Register 1 (CCR1) */
 265 #define SAB82532_CCR1_ODS               0x10
 266 #define SAB82532_CCR1_BCR               0x08
 267 #define SAB82532_CCR1_CM_MASK           0x07
 268
 269 /* Channel Configuration Register 2 (CCR2) */
 270 #define SAB82532_CCR2_SOC1              0x80
 271 #define SAB82532_CCR2_SOC0              0x40
 272 #define SAB82532_CCR2_BR9               0x80
 273 #define SAB82532_CCR2_BR8               0x40
 274 #define SAB82532_CCR2_BDF               0x20
 275 #define SAB82532_CCR2_SSEL              0x10
 276 #define SAB82532_CCR2_XCS0              0x20
 277 #define SAB82532_CCR2_RCS0              0x10
 278 #define SAB82532_CCR2_TOE               0x08
 279 #define SAB82532_CCR2_RWX               0x04
 280 #define SAB82532_CCR2_DIV               0x01
 281
 282 /* Channel Configuration Register 3 (CCR3) */
 283 #define SAB82532_CCR3_PSD               0x01
 284
 285 /* Time Slot Assignment Register Transmit (TSAX) */
 286 #define SAB82532_TSAX_TSNX_MASK         0xfc
 287 #define SAB82532_TSAX_XCS2              0x02    /* see also CCR2 */
 288 #define SAB82532_TSAX_XCS1              0x01
 289
 290 /* Time Slot Assignment Register Receive (TSAR) */
 291 #define SAB82532_TSAR_TSNR_MASK         0xfc
 292 #define SAB82532_TSAR_RCS2              0x02    /* see also CCR2 */
 293 #define SAB82532_TSAR_RCS1              0x01
 294
 295 /* Version Status Register (VSTR) */
 296 #define SAB82532_VSTR_CD                0x80
 297 #define SAB82532_VSTR_DPLA              0x40
 298 #define SAB82532_VSTR_VN_MASK           0x0f
 299 #define SAB82532_VSTR_VN_1              0x00
 300 #define SAB82532_VSTR_VN_2              0x01
 301 #define SAB82532_VSTR_VN_3_2            0x02
 302
 303 /* Global Interrupt Status Register (GIS) */
 304 #define SAB82532_GIS_PI                 0x80
 305 #define SAB82532_GIS_ISA1               0x08
 306 #define SAB82532_GIS_ISA0               0x04
 307 #define SAB82532_GIS_ISB1               0x02
 308 #define SAB82532_GIS_ISB0               0x01
 309
 310 /* Interrupt Vector Address (IVA) */
 311 #define SAB82532_IVA_MASK               0xf1
 312
 313 /* Interrupt Port Configuration (IPC) */
 314 #define SAB82532_IPC_VIS                0x80
 315 #define SAB82532_IPC_SLA1               0x10
 316 #define SAB82532_IPC_SLA0               0x08
 317 #define SAB82532_IPC_CASM               0x04
 318 #define SAB82532_IPC_IC_OPEN_DRAIN      0x00
 319 #define SAB82532_IPC_IC_ACT_LOW         0x01
 320 #define SAB82532_IPC_IC_ACT_HIGH        0x03
 321
 322 /* Interrupt Status Register 0 (ISR0) */
 323 #define SAB82532_ISR0_TCD               0x80
 324 #define SAB82532_ISR0_TIME              0x40
 325 #define SAB82532_ISR0_PERR              0x20
 326 #define SAB82532_ISR0_FERR              0x10
 327 #define SAB82532_ISR0_PLLA              0x08
 328 #define SAB82532_ISR0_CDSC              0x04
 329 #define SAB82532_ISR0_RFO               0x02
 330 #define SAB82532_ISR0_RPF               0x01
 331
 332 /* Interrupt Status Register 1 (ISR1) */
 333 #define SAB82532_ISR1_BRK               0x80
 334 #define SAB82532_ISR1_BRKT              0x40
 335 #define SAB82532_ISR1_ALLS              0x20
 336 #define SAB82532_ISR1_XOFF              0x10
 337 #define SAB82532_ISR1_TIN               0x08
 338 #define SAB82532_ISR1_CSC               0x04
 339 #define SAB82532_ISR1_XON               0x02
 340 #define SAB82532_ISR1_XPR               0x01
 341
 342 /* Interrupt Mask Register 0 (IMR0) */
 343 #define SAB82532_IMR0_TCD               0x80
 344 #define SAB82532_IMR0_TIME              0x40
 345 #define SAB82532_IMR0_PERR              0x20
 346 #define SAB82532_IMR0_FERR              0x10
 347 #define SAB82532_IMR0_PLLA              0x08
 348 #define SAB82532_IMR0_CDSC              0x04
 349 #define SAB82532_IMR0_RFO               0x02
 350 #define SAB82532_IMR0_RPF               0x01
 351
 352 /* Interrupt Mask Register 1 (IMR1) */
 353 #define SAB82532_IMR1_BRK               0x80
 354 #define SAB82532_IMR1_BRKT              0x40
 355 #define SAB82532_IMR1_ALLS              0x20
 356 #define SAB82532_IMR1_XOFF              0x10
 357 #define SAB82532_IMR1_TIN               0x08
 358 #define SAB82532_IMR1_CSC               0x04
 359 #define SAB82532_IMR1_XON               0x02
 360 #define SAB82532_IMR1_XPR               0x01
 361
 362 /* Port Interrupt Status Register (PIS) */
 363 #define SAB82532_PIS_SYNC_B             0x08
 364 #define SAB82532_PIS_DTR_B              0x04
 365 #define SAB82532_PIS_DTR_A              0x02
 366 #define SAB82532_PIS_SYNC_A             0x01
 367
 368 /* Channel Configuration Register 4 (CCR4) */
 369 #define SAB82532_CCR4_MCK4              0x80
 370 #define SAB82532_CCR4_EBRG              0x40
 371 #define SAB82532_CCR4_TST1              0x20
 372 #define SAB82532_CCR4_ICD               0x10
 373
 374
 375 #endif /* !(_SPARC64_SAB82532_H) */