include/asm-sparc64/pgtable.h

   1 /* $Id: pgtable.h,v 1.110 1999/08/30 10:14:57 davem Exp $
   2  * pgtable.h: SpitFire page table operations.
   3  *
   4  * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #ifndef _SPARC64_PGTABLE_H
   9 #define _SPARC64_PGTABLE_H
  10
  11 /* This file contains the functions and defines necessary to modify and use
  12  * the SpitFire page tables.
  13  */
  14
  15 #ifndef __ASSEMBLY__
  16 #include <linux/mm.h>
  17 #include <linux/pagemap.h>
  18 #endif
  19 #include <asm/spitfire.h>
  20 #include <asm/asi.h>
  21 #include <asm/mmu_context.h>
  22 #include <asm/system.h>
  23
  24 #ifndef __ASSEMBLY__
  25 #include <asm/sbus.h>
  26
  27 /* Certain architectures need to do special things when pte's
  28  * within a page table are directly modified.  Thus, the following
  29  * hook is made available.
  30  */
  31 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
  32
  33 /* PMD_SHIFT determines the size of the area a second-level page table can map */
  34 #define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-3))
  35 #define PMD_SIZE        (1UL << PMD_SHIFT)
  36 #define PMD_MASK        (~(PMD_SIZE-1))
  37
  38 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  39 #define PGDIR_SHIFT     (PAGE_SHIFT + (PAGE_SHIFT-3) + (PAGE_SHIFT-2))
  40 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  41 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  42
  43 /* Entries per page directory level. */
  44 #define PTRS_PER_PTE            (1UL << (PAGE_SHIFT-3))
  45
  46 /* We the first one in this file, what we export to the kernel
  47  * is different so we can optimize correctly for 32-bit tasks.
  48  */
  49 #define REAL_PTRS_PER_PMD       (1UL << (PAGE_SHIFT-2))
  50 #define PTRS_PER_PMD            ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
  51                                  (REAL_PTRS_PER_PMD >> 2) : (REAL_PTRS_PER_PMD)))
  52
  53 /* We cannot use the top 16G because VPTE table lives there. */
  54 #define PTRS_PER_PGD            ((1UL << (PAGE_SHIFT-3))-1)
  55
  56 /* Kernel has a separate 44bit address space. */
  57 #define USER_PTRS_PER_PGD       ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
  58                                  (1) : (PTRS_PER_PGD)))
  59
  60 #define PTE_TABLE_SIZE  0x2000  /* 1024 entries 8 bytes each */
  61 #define PMD_TABLE_SIZE  0x2000  /* 2048 entries 4 bytes each */
  62 #define PGD_TABLE_SIZE  0x1000  /* 1024 entries 4 bytes each */
  63
  64 /* the no. of pointers that fit on a page */
  65 #define PTRS_PER_PAGE   (1UL << (PAGE_SHIFT-3))
  66
  67 /* NOTE: TLB miss handlers depend heavily upon where this is. */
  68 #define VMALLOC_START           0x0000000140000000UL
  69 #define VMALLOC_VMADDR(x)       ((unsigned long)(x))
  70 #define VMALLOC_END             0x0000000200000000UL
  71
  72 #endif /* !(__ASSEMBLY__) */
  73
  74 /* SpitFire TTE bits. */
  75 #define _PAGE_VALID     0x8000000000000000      /* Valid TTE                          */
  76 #define _PAGE_R         0x8000000000000000      /* Used to keep ref bit up to date    */
  77 #define _PAGE_SZ4MB     0x6000000000000000      /* 4MB Page                           */
  78 #define _PAGE_SZ512K    0x4000000000000000      /* 512K Page                          */
  79 #define _PAGE_SZ64K     0x2000000000000000      /* 64K Page                           */
  80 #define _PAGE_SZ8K      0x0000000000000000      /* 8K Page                            */
  81 #define _PAGE_NFO       0x1000000000000000      /* No Fault Only                      */
  82 #define _PAGE_IE        0x0800000000000000      /* Invert Endianness                  */
  83 #define _PAGE_SOFT2     0x07FC000000000000      /* Second set of software bits        */
  84 #define _PAGE_DIAG      0x0003FE0000000000      /* Diagnostic TTE bits                */
  85 #define _PAGE_PADDR     0x000001FFFFFFE000      /* Physical Address bits [40:13]      */
  86 #define _PAGE_SOFT      0x0000000000001F80      /* First set of software bits         */
  87 #define _PAGE_L         0x0000000000000040      /* Locked TTE                         */
  88 #define _PAGE_CP        0x0000000000000020      /* Cacheable in Physical Cache        */
  89 #define _PAGE_CV        0x0000000000000010      /* Cacheable in Virtual Cache         */
  90 #define _PAGE_E         0x0000000000000008      /* side-Effect                        */
  91 #define _PAGE_P         0x0000000000000004      /* Privileged Page                    */
  92 #define _PAGE_W         0x0000000000000002      /* Writable                           */
  93 #define _PAGE_G         0x0000000000000001      /* Global                             */
  94
  95 /* Here are the SpitFire software bits we use in the TTE's. */
  96 #define _PAGE_MODIFIED  0x0000000000000800      /* Modified Page (ie. dirty)          */
  97 #define _PAGE_ACCESSED  0x0000000000000400      /* Accessed Page (ie. referenced)     */
  98 #define _PAGE_READ      0x0000000000000200      /* Readable SW Bit                    */
  99 #define _PAGE_WRITE     0x0000000000000100      /* Writable SW Bit                    */
 100 #define _PAGE_PRESENT   0x0000000000000080      /* Present Page (ie. not swapped out) */
 101
 102 #define _PAGE_CACHE     (_PAGE_CP | _PAGE_CV)
 103
 104 #define __DIRTY_BITS    (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
 105 #define __ACCESS_BITS   (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
 106 #define __PRIV_BITS     _PAGE_P
 107
 108 #define PAGE_NONE       __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED)
 109
 110 /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
 111 #define PAGE_SHARED     __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
 112                                   __ACCESS_BITS | _PAGE_WRITE)
 113
 114 #define PAGE_COPY       __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
 115                                   __ACCESS_BITS)
 116
 117 #define PAGE_READONLY   __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
 118                                   __ACCESS_BITS)
 119
 120 #define PAGE_KERNEL     __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
 121                                   __PRIV_BITS | __ACCESS_BITS | __DIRTY_BITS)
 122
 123 #define PAGE_INVALID    __pgprot (0)
 124
 125 #define _PFN_MASK       _PAGE_PADDR
 126
 127 #define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_MODIFIED | _PAGE_ACCESSED | _PAGE_PRESENT)
 128
 129 #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | __ACCESS_BITS | _PAGE_E)
 130
 131 #define __P000  PAGE_NONE
 132 #define __P001  PAGE_READONLY
 133 #define __P010  PAGE_COPY
 134 #define __P011  PAGE_COPY
 135 #define __P100  PAGE_READONLY
 136 #define __P101  PAGE_READONLY
 137 #define __P110  PAGE_COPY
 138 #define __P111  PAGE_COPY
 139
 140 #define __S000  PAGE_NONE
 141 #define __S001  PAGE_READONLY
 142 #define __S010  PAGE_SHARED
 143 #define __S011  PAGE_SHARED
 144 #define __S100  PAGE_READONLY
 145 #define __S101  PAGE_READONLY
 146 #define __S110  PAGE_SHARED
 147 #define __S111  PAGE_SHARED
 148
 149 #ifndef __ASSEMBLY__
 150
 151 extern pte_t __bad_page(void);
 152
 153 #define BAD_PAGE        __bad_page()
 154
 155 /* First physical page can be anywhere, the following is needed so that
 156  * va-->pa and vice versa conversions work properly without performance
 157  * hit for all __pa()/__va() operations.
 158  */
 159 extern unsigned long phys_base;
 160 #define ZERO_PAGE(vaddr)        ((unsigned long)__va(phys_base))
 161
 162 /* Allocate a block of RAM which is aligned to its size.
 163  * This procedure can be used until the call to mem_init().
 164  */
 165 extern void *sparc_init_alloc(unsigned long *kbrk, unsigned long size);
 166
 167 /* Cache and TLB flush operations. */
 168
 169 /* These are the same regardless of whether this is an SMP kernel or not. */
 170 #define flush_cache_mm(__mm) \
 171         do { if ((__mm) == current->mm) flushw_user(); } while(0)
 172 #define flush_cache_range(mm, start, end) \
 173         flush_cache_mm(mm)
 174 #define flush_cache_page(vma, page) \
 175         flush_cache_mm((vma)->vm_mm)
 176
 177 /* These operations are unnecessary on the SpitFire since D-CACHE is write-through. */
 178 #define flush_icache_range(start, end)          do { } while (0)
 179 #define flush_page_to_ram(page)                 do { } while (0)
 180
 181 extern void __flush_dcache_range(unsigned long start, unsigned long end);
 182
 183 extern void __flush_cache_all(void);
 184
 185 extern void __flush_tlb_all(void);
 186 extern void __flush_tlb_mm(unsigned long context, unsigned long r);
 187 extern void __flush_tlb_range(unsigned long context, unsigned long start,
 188                               unsigned long r, unsigned long end,
 189                               unsigned long pgsz, unsigned long size);
 190 extern void __flush_tlb_page(unsigned long context, unsigned long page, unsigned long r);
 191
 192 #ifndef __SMP__
 193
 194 #define flush_cache_all()       __flush_cache_all()
 195 #define flush_tlb_all()         __flush_tlb_all()
 196
 197 #define flush_tlb_mm(__mm) \
 198 do { if(CTX_VALID((__mm)->context)) \
 199         __flush_tlb_mm(CTX_HWBITS((__mm)->context), SECONDARY_CONTEXT); \
 200 } while(0)
 201
 202 #define flush_tlb_range(__mm, start, end) \
 203 do { if(CTX_VALID((__mm)->context)) { \
 204         unsigned long __start = (start)&PAGE_MASK; \
 205         unsigned long __end = (end)&PAGE_MASK; \
 206         __flush_tlb_range(CTX_HWBITS((__mm)->context), __start, \
 207                           SECONDARY_CONTEXT, __end, PAGE_SIZE, \
 208                           (__end - __start)); \
 209      } \
 210 } while(0)
 211
 212 #define flush_tlb_page(vma, page) \
 213 do { struct mm_struct *__mm = (vma)->vm_mm; \
 214      if(CTX_VALID(__mm->context)) \
 215         __flush_tlb_page(CTX_HWBITS(__mm->context), (page)&PAGE_MASK, \
 216                          SECONDARY_CONTEXT); \
 217 } while(0)
 218
 219 #else /* __SMP__ */
 220
 221 extern void smp_flush_cache_all(void);
 222 extern void smp_flush_tlb_all(void);
 223 extern void smp_flush_tlb_mm(struct mm_struct *mm);
 224 extern void smp_flush_tlb_range(struct mm_struct *mm, unsigned long start,
 225                                 unsigned long end);
 226 extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page);
 227
 228 #define flush_cache_all()       smp_flush_cache_all()
 229 #define flush_tlb_all()         smp_flush_tlb_all()
 230
 231 extern __inline__ void flush_tlb_mm(struct mm_struct *mm)
 232 {
 233         if (CTX_VALID(mm->context))
 234                 smp_flush_tlb_mm(mm);
 235 }
 236
 237 extern __inline__ void flush_tlb_range(struct mm_struct *mm, unsigned long start,
 238                                        unsigned long end)
 239 {
 240         if (CTX_VALID(mm->context))
 241                 smp_flush_tlb_range(mm, start, end);
 242 }
 243
 244 extern __inline__ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 245 {
 246         struct mm_struct *mm = vma->vm_mm;
 247
 248         if (CTX_VALID(mm->context))
 249                 smp_flush_tlb_page(mm, page);
 250 }
 251
 252 #endif
 253
 254 #define mk_pte(page, pgprot)            (__pte(__pa(page) | pgprot_val(pgprot)))
 255 #define mk_pte_phys(physpage, pgprot)   (__pte((physpage) | pgprot_val(pgprot)))
 256 #define pte_modify(_pte, newprot) \
 257         (pte_val(_pte) = ((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
 258 #define pmd_set(pmdp, ptep)     \
 259         (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
 260 #define pgd_set(pgdp, pmdp)     \
 261         (pgd_val(*(pgdp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
 262 #define pte_page(pte)   ((unsigned long) __va(((pte_val(pte)&~PAGE_OFFSET)&~(0xfffUL))))
 263 #define pmd_page(pmd)                   ((unsigned long) __va((pmd_val(pmd)<<11UL)))
 264 #define pgd_page(pgd)                   ((unsigned long) __va((pgd_val(pgd)<<11UL)))
 265 #define pte_none(pte)                   (!pte_val(pte))
 266 #define pte_present(pte)                (pte_val(pte) & _PAGE_PRESENT)
 267 #define pte_clear(pte)                  (pte_val(*(pte)) = 0UL)
 268 #define pmd_none(pmd)                   (!pmd_val(pmd))
 269 #define pmd_bad(pmd)                    (0)
 270 #define pmd_present(pmd)                (pmd_val(pmd) != 0UL)
 271 #define pmd_clear(pmdp)                 (pmd_val(*(pmdp)) = 0UL)
 272 #define pgd_none(pgd)                   (!pgd_val(pgd))
 273 #define pgd_bad(pgd)                    (0)
 274 #define pgd_present(pgd)                (pgd_val(pgd) != 0UL)
 275 #define pgd_clear(pgdp)                 (pgd_val(*(pgdp)) = 0UL)
 276
 277 /* The following only work if pte_present() is true.
 278  * Undefined behaviour if not..
 279  */
 280 #define pte_read(pte)           (pte_val(pte) & _PAGE_READ)
 281 #define pte_write(pte)          (pte_val(pte) & _PAGE_WRITE)
 282 #define pte_dirty(pte)          (pte_val(pte) & _PAGE_MODIFIED)
 283 #define pte_young(pte)          (pte_val(pte) & _PAGE_ACCESSED)
 284 #define pte_wrprotect(pte)      (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
 285 #define pte_rdprotect(pte)      (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
 286 #define pte_mkclean(pte)        (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
 287 #define pte_mkold(pte)          (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
 288
 289 /* Be very careful when you change these three, they are delicate. */
 290 static __inline__ pte_t pte_mkyoung(pte_t _pte)
 291 {       if(pte_val(_pte) & _PAGE_READ)
 292                 return __pte(pte_val(_pte)|(_PAGE_ACCESSED|_PAGE_R));
 293         else
 294                 return __pte(pte_val(_pte)|(_PAGE_ACCESSED));
 295 }
 296
 297 static __inline__ pte_t pte_mkwrite(pte_t _pte)
 298 {       if(pte_val(_pte) & _PAGE_MODIFIED)
 299                 return __pte(pte_val(_pte)|(_PAGE_WRITE|_PAGE_W));
 300         else
 301                 return __pte(pte_val(_pte)|(_PAGE_WRITE));
 302 }
 303
 304 static __inline__ pte_t pte_mkdirty(pte_t _pte)
 305 {       if(pte_val(_pte) & _PAGE_WRITE)
 306                 return __pte(pte_val(_pte)|(_PAGE_MODIFIED|_PAGE_W));
 307         else
 308                 return __pte(pte_val(_pte)|(_PAGE_MODIFIED));
 309 }
 310
 311 /* to find an entry in a page-table-directory. */
 312 #define pgd_offset(mm, address) ((mm)->pgd + ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD)))
 313
 314 /* to find an entry in a kernel page-table-directory */
 315 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 316
 317 /* Find an entry in the second-level page table.. */
 318 #define pmd_offset(dir, address)        ((pmd_t *) pgd_page(*(dir)) + \
 319                                         ((address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1)))
 320
 321 /* Find an entry in the third-level page table.. */
 322 #define pte_offset(dir, address)        ((pte_t *) pmd_page(*(dir)) + \
 323                                         ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
 324
 325 /* Very stupidly, we used to get new pgd's and pmd's, init their contents
 326  * to point to the NULL versions of the next level page table, later on
 327  * completely re-init them the same way, then free them up.  This wasted
 328  * a lot of work and caused unnecessary memory traffic.  How broken...
 329  * We fix this by caching them.
 330  */
 331
 332 #ifdef __SMP__
 333 /* Sliiiicck */
 334 #define pgt_quicklists  cpu_data[smp_processor_id()]
 335 #else
 336 extern struct pgtable_cache_struct {
 337         unsigned long *pgd_cache;
 338         unsigned long *pte_cache;
 339         unsigned int pgcache_size;
 340         unsigned int pgdcache_size;
 341 } pgt_quicklists;
 342 #endif
 343 #define pgd_quicklist           (pgt_quicklists.pgd_cache)
 344 #define pmd_quicklist           ((unsigned long *)0)
 345 #define pte_quicklist           (pgt_quicklists.pte_cache)
 346 #define pgtable_cache_size      (pgt_quicklists.pgcache_size)
 347 #define pgd_cache_size          (pgt_quicklists.pgdcache_size)
 348
 349 #ifndef __SMP__
 350
 351 extern __inline__ void free_pgd_fast(pgd_t *pgd)
 352 {
 353         struct page *page = mem_map + MAP_NR(pgd);
 354
 355         if (!page->pprev_hash) {
 356                 (unsigned long *)page->next_hash = pgd_quicklist;
 357                 pgd_quicklist = (unsigned long *)page;
 358         }
 359         (unsigned long)page->pprev_hash |=
 360                 (((unsigned long)pgd & (PAGE_SIZE / 2)) ? 2 : 1);
 361         pgd_cache_size++;
 362 }
 363
 364 extern __inline__ pgd_t *get_pgd_fast(void)
 365 {
 366         struct page *ret;
 367
 368         if ((ret = (struct page *)pgd_quicklist) != NULL) {
 369                 unsigned long mask = (unsigned long)ret->pprev_hash;
 370                 unsigned long off = 0;
 371
 372                 if (mask & 1)
 373                         mask &= ~1;
 374                 else {
 375                         off = PAGE_SIZE / 2;
 376                         mask &= ~2;
 377                 }
 378                 (unsigned long)ret->pprev_hash = mask;
 379                 if (!mask)
 380                         pgd_quicklist = (unsigned long *)ret->next_hash;
 381                 ret = (struct page *)(page_address(ret) + off);
 382                 pgd_cache_size--;
 383         } else {
 384                 ret = (struct page *) __get_free_page(GFP_KERNEL);
 385                 if(ret) {
 386                         struct page *page = mem_map + MAP_NR(ret);
 387
 388                         memset(ret, 0, PAGE_SIZE);
 389                         (unsigned long)page->pprev_hash = 2;
 390                         (unsigned long *)page->next_hash = pgd_quicklist;
 391                         pgd_quicklist = (unsigned long *)page;
 392                         pgd_cache_size++;
 393                 }
 394         }
 395         return (pgd_t *)ret;
 396 }
 397
 398 #else /* __SMP__ */
 399
 400 extern __inline__ void free_pgd_fast(pgd_t *pgd)
 401 {
 402         *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
 403         pgd_quicklist = (unsigned long *) pgd;
 404         pgtable_cache_size++;
 405 }
 406
 407 extern __inline__ pgd_t *get_pgd_fast(void)
 408 {
 409         unsigned long *ret;
 410
 411         if((ret = pgd_quicklist) != NULL) {
 412                 pgd_quicklist = (unsigned long *)(*ret);
 413                 ret[0] = 0;
 414                 pgtable_cache_size--;
 415         } else {
 416                 ret = (unsigned long *) __get_free_page(GFP_KERNEL);
 417                 if(ret)
 418                         memset(ret, 0, PAGE_SIZE);
 419         }
 420         return (pgd_t *)ret;
 421 }
 422
 423 extern __inline__ void free_pgd_slow(pgd_t *pgd)
 424 {
 425         free_page((unsigned long)pgd);
 426 }
 427
 428 #endif /* __SMP__ */
 429
 430 extern pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long address_premasked);
 431
 432 extern __inline__ pmd_t *get_pmd_fast(void)
 433 {
 434         unsigned long *ret;
 435
 436         if((ret = (unsigned long *)pte_quicklist) != NULL) {
 437                 pte_quicklist = (unsigned long *)(*ret);
 438                 ret[0] = 0;
 439                 pgtable_cache_size--;
 440         }
 441         return (pmd_t *)ret;
 442 }
 443
 444 extern __inline__ void free_pmd_fast(pgd_t *pmd)
 445 {
 446         *(unsigned long *)pmd = (unsigned long) pte_quicklist;
 447         pte_quicklist = (unsigned long *) pmd;
 448         pgtable_cache_size++;
 449 }
 450
 451 extern __inline__ void free_pmd_slow(pmd_t *pmd)
 452 {
 453         free_page((unsigned long)pmd);
 454 }
 455
 456 extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
 457
 458 extern __inline__ pte_t *get_pte_fast(void)
 459 {
 460         unsigned long *ret;
 461
 462         if((ret = (unsigned long *)pte_quicklist) != NULL) {
 463                 pte_quicklist = (unsigned long *)(*ret);
 464                 ret[0] = 0;
 465                 pgtable_cache_size--;
 466         }
 467         return (pte_t *)ret;
 468 }
 469
 470 extern __inline__ void free_pte_fast(pte_t *pte)
 471 {
 472         *(unsigned long *)pte = (unsigned long) pte_quicklist;
 473         pte_quicklist = (unsigned long *) pte;
 474         pgtable_cache_size++;
 475 }
 476
 477 extern __inline__ void free_pte_slow(pte_t *pte)
 478 {
 479         free_page((unsigned long)pte);
 480 }
 481
 482 #define pte_free_kernel(pte)    free_pte_fast(pte)
 483 #define pte_free(pte)           free_pte_fast(pte)
 484 #define pmd_free_kernel(pmd)    free_pmd_fast(pmd)
 485 #define pmd_free(pmd)           free_pmd_fast(pmd)
 486 #define pgd_free(pgd)           free_pgd_fast(pgd)
 487 #define pgd_alloc()             get_pgd_fast()
 488
 489 extern inline pte_t * pte_alloc(pmd_t *pmd, unsigned long address)
 490 {
 491         address = (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
 492         if (pmd_none(*pmd)) {
 493                 pte_t *page = get_pte_fast();
 494
 495                 if (!page)
 496                         return get_pte_slow(pmd, address);
 497                 pmd_set(pmd, page);
 498                 return page + address;
 499         }
 500         return (pte_t *) pmd_page(*pmd) + address;
 501 }
 502
 503 extern inline pmd_t * pmd_alloc(pgd_t *pgd, unsigned long address)
 504 {
 505         address = (address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD - 1);
 506         if (pgd_none(*pgd)) {
 507                 pmd_t *page = get_pmd_fast();
 508
 509                 if (!page)
 510                         return get_pmd_slow(pgd, address);
 511                 pgd_set(pgd, page);
 512                 return page + address;
 513         }
 514         return (pmd_t *) pgd_page(*pgd) + address;
 515 }
 516
 517 #define pte_alloc_kernel(pmd, addr)     pte_alloc(pmd, addr)
 518 #define pmd_alloc_kernel(pgd, addr)     pmd_alloc(pgd, addr)
 519
 520 extern int do_check_pgt_cache(int, int);
 521
 522 /* Nothing to do on sparc64 :) */
 523 #define set_pgdir(address, entry)       do { } while(0)
 524
 525 extern pgd_t swapper_pg_dir[1];
 526 /* Routines for getting a dvma scsi buffer. */
 527 struct mmu_sglist {
 528         char *addr;
 529         char *__dont_touch;
 530         unsigned int len;
 531         __u32 dvma_addr;
 532         __u32 dvma_len;
 533 };
 534
 535 extern __u32 mmu_get_scsi_one(char *, unsigned long, struct linux_sbus *sbus);
 536 extern void  mmu_get_scsi_sgl(struct mmu_sglist *, int, struct linux_sbus *sbus);
 537
 538 extern void mmu_release_scsi_one(u32 vaddr, unsigned long len,
 539                                  struct linux_sbus *sbus);
 540 extern void mmu_release_scsi_sgl(struct mmu_sglist *sg, int sz, struct linux_sbus *sbus);
 541
 542 #define NEED_DMA_SYNCHRONIZATION
 543 #define mmu_sync_dma(dma_addr, len, sbus_instance)      \
 544         mmu_release_scsi_one((dma_addr), (len), (sbus_instance))
 545
 546 /* These do nothing with the way I have things setup. */
 547 #define mmu_lockarea(vaddr, len)                (vaddr)
 548 #define mmu_unlockarea(vaddr, len)              do { } while(0)
 549
 550 /* There used to be some funny code here which tried to guess which
 551  * TLB wanted the mapping, that wasn't accurate enough to justify it's
 552  * existance.  The real way to do that is to have each TLB miss handler
 553  * pass in a distinct code to do_sparc64_fault() and do it more accurately
 554  * there.
 555  *
 556  * What we do need to handle here is prevent I-cache corruption.  The
 557  * deal is that the I-cache snoops stores from other CPUs and all DMA
 558  * activity, however stores from the local processor are not snooped.
 559  * The dynamic linker and our signal handler mechanism take care of
 560  * the cases where they write into instruction space, but when a page
 561  * is copied in the kernel and then executed in user-space is not handled
 562  * right.  This leads to corruptions if things are "just right", consider
 563  * the following scenerio:
 564  * 1) Process 1 frees up a page that was used for the PLT of libc in
 565  *    it's address space.
 566  * 2) Process 2 writes into a page in the PLT of libc for the first
 567  *    time.  do_wp_page() copies the page locally, the local I-cache of
 568  *    the processor does not notice the writes during the page copy.
 569  *    The new page used just so happens to be the one just freed in #1.
 570  * 3) After the PLT write, later the cpu calls into an unresolved PLT
 571  *    entry, the CPU executes old instructions from process 1's PLT
 572  *    table.
 573  * 4) Splat.
 574  */
 575 extern void flush_icache_page(unsigned long phys_page);
 576 #define update_mmu_cache(__vma, __address, _pte) \
 577 do { \
 578         unsigned short __flags = ((__vma)->vm_flags); \
 579         if ((__flags & VM_EXEC) != 0 && \
 580             ((pte_val(_pte) & (_PAGE_PRESENT | _PAGE_WRITE | _PAGE_MODIFIED)) == \
 581              (_PAGE_PRESENT | _PAGE_WRITE | _PAGE_MODIFIED))) { \
 582                 flush_icache_page(pte_page(_pte) - page_offset); \
 583         } \
 584 } while(0)
 585
 586 /* Make a non-present pseudo-TTE. */
 587 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 588 { pte_t pte; pte_val(pte) = (type<<PAGE_SHIFT)|(offset<<(PAGE_SHIFT+8)); return pte; }
 589
 590 extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
 591 {
 592         pte_t pte;
 593         pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE;
 594         pte_val(pte) |= (((unsigned long)space) << 32);
 595         return pte;
 596 }
 597
 598 #define SWP_TYPE(entry)         (((entry>>PAGE_SHIFT) & 0xff))
 599 #define SWP_OFFSET(entry)       ((entry) >> (PAGE_SHIFT+8))
 600 #define SWP_ENTRY(type,offset)  pte_val(mk_swap_pte((type),(offset)))
 601
 602 extern __inline__ unsigned long
 603 sun4u_get_pte (unsigned long addr)
 604 {
 605         pgd_t *pgdp;
 606         pmd_t *pmdp;
 607         pte_t *ptep;
 608
 609         if (addr >= PAGE_OFFSET)
 610                 return addr & _PAGE_PADDR;
 611         pgdp = pgd_offset_k (addr);
 612         pmdp = pmd_offset (pgdp, addr);
 613         ptep = pte_offset (pmdp, addr);
 614         return pte_val (*ptep) & _PAGE_PADDR;
 615 }
 616
 617 extern __inline__ unsigned long
 618 __get_phys (unsigned long addr)
 619 {
 620         return sun4u_get_pte (addr);
 621 }
 622
 623 extern __inline__ int
 624 __get_iospace (unsigned long addr)
 625 {
 626         return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
 627 }
 628
 629 extern void * module_map (unsigned long size);
 630 extern void module_unmap (void *addr);
 631 extern unsigned long *sparc64_valid_addr_bitmap;
 632
 633 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 634 #define PageSkip(page)          (test_bit(PG_skip, &(page)->flags))
 635 #define kern_addr_valid(addr)   (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
 636
 637 extern int io_remap_page_range(unsigned long from, unsigned long offset,
 638                                unsigned long size, pgprot_t prot, int space);
 639
 640 #endif /* !(__ASSEMBLY__) */
 641
 642 #endif /* !(_SPARC64_PGTABLE_H) */