1 /* $Id: asi.h,v 1.1 1996/11/20 12:59:45 davem Exp $ */
5 /* asi.h: Address Space Identifier values for the V9.
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
10 /* V9 Architecture mandary ASIs. */
11 #define ASI_N 0x04 /* Nucleus */
12 #define ASI_NL 0x0c /* Nucleus, little endian */
13 #define ASI_AIUP 0x10 /* Primary, user */
14 #define ASI_AIUS 0x11 /* Secondary, user */
15 #define ASI_AIUPL 0x18 /* Primary, user, little endian */
16 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
17 #define ASI_P 0x80 /* Primary, implicit */
18 #define ASI_S 0x81 /* Secondary, implicit */
19 #define ASI_PNF 0x82 /* Primary, no fault */
20 #define ASI_SNF 0x83 /* Secondary, no fault */
21 #define ASI_PL 0x88 /* Primary, implicit, little endian */
22 #define ASI_SL 0x89 /* Secondary, implicit, little endian */
23 #define ASI_PNFL 0x8a /* Primary, no fault, little endian */
24 #define ASI_SNFL 0x8b /* Secondary, no fault, little endian */
26 /* SpitFire extended ASIs. */
27 #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cachable */
28 #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-cachable, E-bit */
29 #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cachable, little endian */
30 #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-cachable, E-bit, little endian */
31 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* Cachable, qword load */
32 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cachable, qword load, little endian */
33 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
34 #define ASI_DCACHE_DATA 0x46 /* Data cache data-ram diag access */
35 #define ASI_DCACHE_TAG 0x47 /* Data cache tag/valid ram diag access */
36 #define ASI_INTR_DISPATCH_STAT 0x48 /* IRQ vector dispatch status */
37 #define ASI_INTR_RECEIVE 0x49 /* IRQ vector receive status */
38 #define ASI_UPA_CONFIG 0x4a /* UPA config space */
39 #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
40 #define ASI_AFSR 0x4c /* Async fault status register */
41 #define ASI_AFAR 0x4d /* Async fault address register */
42 #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag access */
43 #define ASI_IMMU 0x50 /* Insn-MMU main register space */
44 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer register */
45 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer register */
46 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in register */
47 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access register */
48 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read register */
49 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
50 #define ASI_DMMU 0x58 /* Data-MMU main register space */
51 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer register */
52 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer register */
53 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer register */
54 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in register */
55 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access register */
56 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read register */
57 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
58 #define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag access */
59 #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag access */
60 #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag access */
61 #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag access */
62 #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
63 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block load/store */
64 #define ASI_EC_W 0x76 /* E-cache diag write access */
65 #define ASI_UDB_ERROR_W 0x77 /* External UDB error registers write */
66 #define ASI_UDB_CONTROL_W 0x77 /* External UDB control registers write */
67 #define ASI_UDB_INTR_W 0x77 /* External UDB IRQ vector dispatch write */
68 #define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st */
69 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st */
70 #define ASI_EC_R 0x7e /* E-cache diag read access */
71 #define ASI_UDBH_ERROR_R 0x7f /* External UDB error registers read hi */
72 #define ASI_UDBL_ERROR_R 0x7f /* External UDB error registers read low */
73 #define ASI_UDBH_CONTROL_R 0x7f /* External UDB control registers read hi */
74 #define ASI_UDBL_CONTROL_R 0x7f /* External UDB control registers read low */
75 #define ASI_UDB_INTR_R 0x7f /* External UDB IRQ vector dispatch read */
76 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
77 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
78 #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
79 #define ASI_PST16_S 0xc3 /* Seconary, 4 16-bit, partial */
80 #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
81 #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
82 #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, little */
83 #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, little */
84 #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, little */
85 #define ASI_PST16_SL 0xcb /* Seconary, 4 16-bit, partial, little */
86 #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, little */
87 #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, little */
88 #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
89 #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
90 #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
91 #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
92 #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, little */
93 #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, little */
94 #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, little */
95 #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st, little */
96 #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
97 #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
98 #define ASI_BLK_P 0xf0 /* Primary, blk ld/st */
99 #define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */
100 #define ASI_BLK_PL 0xf8 /* Primary, blk ld/st, little */
101 #define ASI_BLK_SL 0xf9 /* Secondary, blk ld/st, little */
103 #endif /* _SPARC64_ASI_H */
