Import 2.3.18pre1
[davej-history.git] / include / asm-sparc / perfctr.h
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1 /*----------------------------------------
2 PERFORMANCE INSTRUMENTATION
3 Guillaume Thouvenin 08/10/98
4 David S. Miller 10/06/98
5 ---------------------------------------*/
6 #ifndef PERF_COUNTER_API
7 #define PERF_COUNTER_API
9 /* sys_perfctr() interface. First arg is operation code
10 * from enumeration below. The meaning of further arguments
11 * are determined by the operation code.
13 * int sys_perfctr(int opcode, unsigned long arg0,
14 * unsigned long arg1, unsigned long arg2)
16 * Pointers which are passed by the user are pointers to 64-bit
17 * integers.
19 * Once enabled, performance counter state is retained until the
20 * process either exits or performs an exec. That is, performance
21 * counters remain enabled for fork/clone children.
23 enum perfctr_opcode {
24 /* Enable UltraSparc performance counters, ARG0 is pointer
25 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
26 * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
27 * the initial PCR register value to use.
29 PERFCTR_ON,
31 /* Disable UltraSparc performance counters. The PCR is written
32 * with zero and the user counter accumulator pointers and
33 * working PCR register value are forgotten.
35 PERFCTR_OFF,
37 /* Add current D0 and D1 PIC values into user pointers given
38 * in PERFCTR_ON operation. The PIC is cleared before returning.
40 PERFCTR_READ,
42 /* Clear the PIC register. */
43 PERFCTR_CLRPIC,
45 /* Begin using a new PCR value, the pointer to which is passed
46 * in ARG0. The PIC is also cleared after the new PCR value is
47 * written.
49 PERFCTR_SETPCR,
51 /* Store in pointer given in ARG0 the current PCR register value
52 * being used.
54 PERFCTR_GETPCR
57 /* I don't want the kernel's namespace to be polluted with this
58 * stuff when this file is included. --DaveM
60 #ifndef __KERNEL__
62 #define PRIV 0x00000001
63 #define USR 0x00000002
64 #define SYS 0x00000004
66 /* Pic.S0 Selection Bit Field Encoding */
67 #define CYCLE_CNT 0x00000000
68 #define INSTR_CNT 0x00000010
69 #define DISPATCH0_IC_MISS 0x00000020
70 #define DISPATCH0_STOREBUF 0x00000030
71 #define IC_REF 0x00000080
72 #define DC_RD 0x00000090
73 #define DC_WR 0x000000A0
74 #define LOAD_USE 0x000000B0
75 #define EC_REF 0x000000C0
76 #define EC_WRITE_HIT_RDO 0x000000D0
77 #define EC_SNOOP_INV 0x000000E0
78 #define EC_RD_HIT 0x000000F0
80 /* Pic.S1 Selection Bit Field Encoding */
81 #define CYCLE_CNT_D1 0x00000000
82 #define INSTR_CNT_D1 0x00000800
83 #define DISPATCH0_IC_MISPRED 0x00001000
84 #define DISPATCH0_FP_USE 0x00001800
85 #define IC_HIT 0x00004000
86 #define DC_RD_HIT 0x00004800
87 #define DC_WR_HIT 0x00005000
88 #define LOAD_USE_RAW 0x00005800
89 #define EC_HIT 0x00006000
90 #define EC_WB 0x00006800
91 #define EC_SNOOP_CB 0x00007000
92 #define EC_IT_HIT 0x00007800
94 struct vcounter_struct {
95 unsigned long long vcnt0;
96 unsigned long long vcnt1;
99 #endif /* !(__KERNEL__) */
101 #endif /* !(PERF_COUNTER_API) */