include/asm-sparc/cache.h

   1 /* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $
   2  * cache.h:  Cache specific code for the Sparc.  These include flushing
   3  *           and direct tag/data line access.
   4  *
   5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   6  */
   7
   8 #ifndef _SPARC_CACHE_H
   9 #define _SPARC_CACHE_H
  10
  11 #include <asm/asi.h>
  12
  13 #define L1_CACHE_BYTES 32
  14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
  15
  16 #define SMP_CACHE_BYTES 32
  17
  18 #ifdef MODULE
  19 #define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
  20 #else
  21 #define __cacheline_aligned                                     \
  22   __attribute__((__aligned__(SMP_CACHE_BYTES),                  \
  23                  __section__(".data.cacheline_aligned")))
  24 #endif
  25
  26 /* Direct access to the instruction cache is provided through and
  27  * alternate address space.  The IDC bit must be off in the ICCR on
  28  * HyperSparcs for these accesses to work.  The code below does not do
  29  * any checking, the caller must do so.  These routines are for
  30  * diagnostics only, but could end up being useful.  Use with care.
  31  * Also, you are asking for trouble if you execute these in one of the
  32  * three instructions following a %asr/%psr access or modification.
  33  */
  34
  35 /* First, cache-tag access. */
  36 extern __inline__ unsigned int get_icache_tag(int setnum, int tagnum)
  37 {
  38         unsigned int vaddr, retval;
  39
  40         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  41         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
  42                              "=r" (retval) :
  43                              "r" (vaddr), "i" (ASI_M_TXTC_TAG));
  44         return retval;
  45 }
  46
  47 extern __inline__ void put_icache_tag(int setnum, int tagnum, unsigned int entry)
  48 {
  49         unsigned int vaddr;
  50
  51         vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
  52         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
  53                              "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
  54                              "memory");
  55 }
  56
  57 /* Second cache-data access.  The data is returned two-32bit quantities
  58  * at a time.
  59  */
  60 extern __inline__ void get_icache_data(int setnum, int tagnum, int subblock,
  61                                        unsigned int *data)
  62 {
  63         unsigned int value1, value2, vaddr;
  64
  65         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  66                 ((subblock&0x3) << 3);
  67         __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
  68                              "or %%g0, %%g2, %0\n\t"
  69                              "or %%g0, %%g3, %1\n\t" :
  70                              "=r" (value1), "=r" (value2) :
  71                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  72                              "g2", "g3");
  73         data[0] = value1; data[1] = value2;
  74 }
  75
  76 extern __inline__ void put_icache_data(int setnum, int tagnum, int subblock,
  77                                        unsigned int *data)
  78 {
  79         unsigned int value1, value2, vaddr;
  80
  81         vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
  82                 ((subblock&0x3) << 3);
  83         value1 = data[0]; value2 = data[1];
  84         __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
  85                              "or %%g0, %1, %%g3\n\t"
  86                              "stda %%g2, [%2] %3\n\t" : :
  87                              "r" (value1), "r" (value2),
  88                              "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
  89                              "g2", "g3", "memory" /* no joke */);
  90 }
  91
  92 /* Different types of flushes with the ICACHE.  Some of the flushes
  93  * affect both the ICACHE and the external cache.  Others only clear
  94  * the ICACHE entries on the cpu itself.  V8's (most) allow
  95  * granularity of flushes on the packet (element in line), whole line,
  96  * and entire cache (ie. all lines) level.  The ICACHE only flushes are
  97  * ROSS HyperSparc specific and are in ross.h
  98  */
  99
 100 /* Flushes which clear out both the on-chip and external caches */
 101 extern __inline__ void flush_ei_page(unsigned int addr)
 102 {
 103         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 104                              "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
 105                              "memory");
 106 }
 107
 108 extern __inline__ void flush_ei_seg(unsigned int addr)
 109 {
 110         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 111                              "r" (addr), "i" (ASI_M_FLUSH_SEG) :
 112                              "memory");
 113 }
 114
 115 extern __inline__ void flush_ei_region(unsigned int addr)
 116 {
 117         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 118                              "r" (addr), "i" (ASI_M_FLUSH_REGION) :
 119                              "memory");
 120 }
 121
 122 extern __inline__ void flush_ei_ctx(unsigned int addr)
 123 {
 124         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 125                              "r" (addr), "i" (ASI_M_FLUSH_CTX) :
 126                              "memory");
 127 }
 128
 129 extern __inline__ void flush_ei_user(unsigned int addr)
 130 {
 131         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 132                              "r" (addr), "i" (ASI_M_FLUSH_USER) :
 133                              "memory");
 134 }
 135
 136 #endif /* !(_SPARC_CACHE_H) */