include/asm-ppc/dma.h

   1 /* $Id: dma.h,v 1.3 1997/03/16 06:20:39 cort Exp $
   2  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3  * Written by Hennus Bergman, 1992.
   4  * High DMA channel support & info by Hannu Savolainen
   5  * and John Boyd, Nov. 1992.
   6  * Changes for ppc sound by Christoph Nadig
   7  */
   8
   9 #include <linux/config.h>
  10 #include <asm/io.h>
  11 #include <linux/spinlock.h>
  12 #include <asm/system.h>
  13
  14 /*
  15  * Note: Adapted for PowerPC by Gary Thomas
  16  * Modified by Cort Dougan <cort@cs.nmt.edu>
  17  *
  18  * None of this really applies for Power Macintoshes.  There is
  19  * basically just enough here to get kernel/dma.c to compile.
  20  *
  21  * There may be some comments or restrictions made here which are
  22  * not valid for the PReP platform.  Take what you read
  23  * with a grain of salt.
  24  */
  25
  26
  27 #ifndef _ASM_DMA_H
  28 #define _ASM_DMA_H
  29
  30 #ifndef MAX_DMA_CHANNELS
  31 #define MAX_DMA_CHANNELS        8
  32 #endif
  33
  34 /* The maximum address that we can perform a DMA transfer to on this platform */
  35 /* Doesn't really apply... */
  36 #define MAX_DMA_ADDRESS      0xFFFFFFFF
  37
  38 /* in arch/ppc/kernel/setup.c -- Cort */
  39 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
  40 extern unsigned long ISA_DMA_THRESHOLD;
  41
  42
  43 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  44 #define dma_outb        outb_p
  45 #else
  46 #define dma_outb        outb
  47 #endif
  48
  49 #define dma_inb         inb
  50
  51 /*
  52  * NOTES about DMA transfers:
  53  *
  54  *  controller 1: channels 0-3, byte operations, ports 00-1F
  55  *  controller 2: channels 4-7, word operations, ports C0-DF
  56  *
  57  *  - ALL registers are 8 bits only, regardless of transfer size
  58  *  - channel 4 is not used - cascades 1 into 2.
  59  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  60  *  - channels 5-7 are word - addresses/counts are for physical words
  61  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  62  *  - transfer count loaded to registers is 1 less than actual count
  63  *  - controller 2 offsets are all even (2x offsets for controller 1)
  64  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  65  *  - page registers for 0-3 use bit 0, represent 64K pages
  66  *
  67  * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
  68  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
  69  * Note that addresses loaded into registers must be _physical_ addresses,
  70  * not logical addresses (which may differ if paging is active).
  71  *
  72  *  Address mapping for channels 0-3:
  73  *
  74  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  75  *    |  ...  |   |  ... |   |  ... |
  76  *    |  ...  |   |  ... |   |  ... |
  77  *    |  ...  |   |  ... |   |  ... |
  78  *   P7  ...  P0  A7 ... A0  A7 ... A0
  79  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  80  *
  81  *  Address mapping for channels 5-7:
  82  *
  83  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  84  *    |  ...  |   \   \   ... \  \  \  ... \  \
  85  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  86  *    |  ...  |     \   \   ... \  \  \  ... \
  87  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  88  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  89  *
  90  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  91  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  92  * the hardware level, so odd-byte transfers aren't possible).
  93  *
  94  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  95  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  96  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  97  *
  98  */
  99
 100 /* used in nasty hack for sound - see prep_setup_arch() -- Cort */
 101 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
 102 #ifdef CONFIG_CS4232
 103 #define SND_DMA1 ppc_cs4232_dma
 104 #define SND_DMA2 ppc_cs4232_dma2
 105 #else
 106 #ifdef CONFIG_MSS
 107 #define SND_DMA1 CONFIG_MSS_DMA
 108 #define SND_DMA2 CONFIG_MSS_DMA2
 109 #else
 110 #define SND_DMA1 -1
 111 #define SND_DMA2 -1
 112 #endif
 113 #endif
 114
 115 /* 8237 DMA controllers */
 116 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 117 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 118
 119 /* DMA controller registers */
 120 #define DMA1_CMD_REG            0x08    /* command register (w) */
 121 #define DMA1_STAT_REG           0x08    /* status register (r) */
 122 #define DMA1_REQ_REG            0x09    /* request register (w) */
 123 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 124 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
 125 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 126 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 127 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 128 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 129 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 130
 131 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 132 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 133 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 134 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 135 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 136 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 137 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 138 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 139 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 140 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 141
 142 #define DMA_ADDR_0              0x00    /* DMA address registers */
 143 #define DMA_ADDR_1              0x02
 144 #define DMA_ADDR_2              0x04
 145 #define DMA_ADDR_3              0x06
 146 #define DMA_ADDR_4              0xC0
 147 #define DMA_ADDR_5              0xC4
 148 #define DMA_ADDR_6              0xC8
 149 #define DMA_ADDR_7              0xCC
 150
 151 #define DMA_CNT_0               0x01    /* DMA count registers */
 152 #define DMA_CNT_1               0x03
 153 #define DMA_CNT_2               0x05
 154 #define DMA_CNT_3               0x07
 155 #define DMA_CNT_4               0xC2
 156 #define DMA_CNT_5               0xC6
 157 #define DMA_CNT_6               0xCA
 158 #define DMA_CNT_7               0xCE
 159
 160 #define DMA_LO_PAGE_0              0x87    /* DMA page registers */
 161 #define DMA_LO_PAGE_1              0x83
 162 #define DMA_LO_PAGE_2              0x81
 163 #define DMA_LO_PAGE_3              0x82
 164 #define DMA_LO_PAGE_5              0x8B
 165 #define DMA_LO_PAGE_6              0x89
 166 #define DMA_LO_PAGE_7              0x8A
 167
 168 #define DMA_HI_PAGE_0              0x487    /* DMA page registers */
 169 #define DMA_HI_PAGE_1              0x483
 170 #define DMA_HI_PAGE_2              0x481
 171 #define DMA_HI_PAGE_3              0x482
 172 #define DMA_HI_PAGE_5              0x48B
 173 #define DMA_HI_PAGE_6              0x489
 174 #define DMA_HI_PAGE_7              0x48A
 175
 176 #define DMA1_EXT_REG               0x40B
 177 #define DMA2_EXT_REG               0x4D6
 178
 179 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 180 #define DMA_AUTOINIT     0x10
 181
 182 extern spinlock_t  dma_spin_lock;
 183
 184 static __inline__ unsigned long claim_dma_lock(void)
 185 {
 186         unsigned long flags;
 187         spin_lock_irqsave(&dma_spin_lock, flags);
 188         return flags;
 189 }
 190
 191 static __inline__ void release_dma_lock(unsigned long flags)
 192 {
 193         spin_unlock_irqrestore(&dma_spin_lock, flags);
 194 }
 195
 196 /* enable/disable a specific DMA channel */
 197 static __inline__ void enable_dma(unsigned int dmanr)
 198 {
 199         /*
 200          * The Radstone PPC2 and PPC2a boards have inverted DREQ
 201          * lines (active low) so each command needs to be logically
 202          * ORed with 0x40
 203          */
 204         unsigned char ucDmaCmd=0x00;
 205
 206         if(_prep_type==_PREP_Radstone)
 207         {
 208                 switch(ucSystemType)
 209                 {
 210                         case RS_SYS_TYPE_PPC2:
 211                         case RS_SYS_TYPE_PPC2a:
 212                         case RS_SYS_TYPE_PPC2ep:
 213                         {
 214                                 /*
 215                                  * DREQ lines are active low
 216                                  */
 217                                 ucDmaCmd=0x40;
 218                                 break;
 219                         }
 220
 221                         default:
 222                         {
 223                                 /*
 224                                  * DREQ lines are active high
 225                                  */
 226                                 break;
 227                         }
 228                 }
 229         }
 230
 231         if (dmanr != 4)
 232         {
 233                 dma_outb(0, DMA2_MASK_REG);  /* This may not be enabled */
 234                 dma_outb(ucDmaCmd, DMA2_CMD_REG);  /* Enable group */
 235         }
 236         if (dmanr<=3)
 237         {
 238                 dma_outb(dmanr,  DMA1_MASK_REG);
 239                 dma_outb(ucDmaCmd, DMA1_CMD_REG);  /* Enable group */
 240         } else
 241         {
 242                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 243         }
 244 }
 245
 246 static __inline__ void disable_dma(unsigned int dmanr)
 247 {
 248         if (dmanr<=3)
 249                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 250         else
 251                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 252 }
 253
 254 /* Clear the 'DMA Pointer Flip Flop'.
 255  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 256  * Use this once to initialize the FF to a known state.
 257  * After that, keep track of it. :-)
 258  * --- In order to do that, the DMA routines below should ---
 259  * --- only be used while interrupts are disabled! ---
 260  */
 261 static __inline__ void clear_dma_ff(unsigned int dmanr)
 262 {
 263         if (dmanr<=3)
 264                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 265         else
 266                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 267 }
 268
 269 /* set mode (above) for a specific DMA channel */
 270 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 271 {
 272         if (dmanr<=3)
 273                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 274         else
 275                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 276 }
 277
 278 /* Set only the page register bits of the transfer address.
 279  * This is used for successive transfers when we know the contents of
 280  * the lower 16 bits of the DMA current address register, but a 64k boundary
 281  * may have been crossed.
 282  */
 283 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
 284 {
 285         switch(dmanr) {
 286                 case 0:
 287                         dma_outb(pagenr, DMA_LO_PAGE_0);
 288                         dma_outb(pagenr>>8, DMA_HI_PAGE_0);
 289                         break;
 290                 case 1:
 291                         dma_outb(pagenr, DMA_LO_PAGE_1);
 292                         dma_outb(pagenr>>8, DMA_HI_PAGE_1);
 293                         break;
 294                 case 2:
 295                         dma_outb(pagenr, DMA_LO_PAGE_2);
 296                         dma_outb(pagenr>>8, DMA_HI_PAGE_2);
 297                         break;
 298                 case 3:
 299                         dma_outb(pagenr, DMA_LO_PAGE_3);
 300                         dma_outb(pagenr>>8, DMA_HI_PAGE_3);
 301                         break;
 302                 case 5:
 303                         if (SND_DMA1 == 5 || SND_DMA2 == 5)
 304                                 dma_outb(pagenr, DMA_LO_PAGE_5);
 305                         else
 306                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
 307                         dma_outb(pagenr>>8, DMA_HI_PAGE_5);
 308                         break;
 309                 case 6:
 310                         if (SND_DMA1 == 6 || SND_DMA2 == 6)
 311                                 dma_outb(pagenr, DMA_LO_PAGE_6);
 312                         else
 313                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
 314                         dma_outb(pagenr>>8, DMA_HI_PAGE_6);
 315                         break;
 316                 case 7:
 317                         if (SND_DMA1 == 7 || SND_DMA2 == 7)
 318                                 dma_outb(pagenr, DMA_LO_PAGE_7);
 319                         else
 320                                 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
 321                         dma_outb(pagenr>>8, DMA_HI_PAGE_7);
 322                   break;
 323         }
 324 }
 325
 326
 327 /* Set transfer address & page bits for specific DMA channel.
 328  * Assumes dma flipflop is clear.
 329  */
 330 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
 331 {
 332         if (dmanr <= 3)  {
 333             dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 334             dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 335         }  else  {
 336           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 337             dma_outb( phys  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 338             dma_outb( (phys>>8)  & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 339             dma_outb( (dmanr&3), DMA2_EXT_REG);
 340           } else {
 341             dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 342             dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 343           }
 344         }
 345         set_dma_page(dmanr, phys>>16);
 346 }
 347
 348
 349 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 350  * a specific DMA channel.
 351  * You must ensure the parameters are valid.
 352  * NOTE: from a manual: "the number of transfers is one more
 353  * than the initial word count"! This is taken into account.
 354  * Assumes dma flip-flop is clear.
 355  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 356  */
 357 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 358 {
 359         count--;
 360         if (dmanr <= 3)  {
 361             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 362             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 363         } else {
 364           if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
 365             dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 366             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 367           } else {
 368             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 369             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 370           }
 371         }
 372 }
 373
 374
 375 /* Get DMA residue count. After a DMA transfer, this
 376  * should return zero. Reading this while a DMA transfer is
 377  * still in progress will return unpredictable results.
 378  * If called before the channel has been used, it may return 1.
 379  * Otherwise, it returns the number of _bytes_ left to transfer.
 380  *
 381  * Assumes DMA flip-flop is clear.
 382  */
 383 static __inline__ int get_dma_residue(unsigned int dmanr)
 384 {
 385         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 386                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 387
 388         /* using short to get 16-bit wrap around */
 389         unsigned short count;
 390
 391         count = 1 + dma_inb(io_port);
 392         count += dma_inb(io_port) << 8;
 393
 394         return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
 395           ? count : (count<<1);
 396 }
 397
 398 /* These are in kernel/dma.c: */
 399 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 400 extern void free_dma(unsigned int dmanr);       /* release it again */
 401
 402 #ifdef CONFIG_PCI
 403 extern int isa_dma_bridge_buggy;
 404 #else
 405 #define isa_dma_bridge_buggy   (0)
 406 #endif
 407 #endif /* _ASM_DMA_H */