include/asm-mips/sgimc.h

   1 /* $Id: sgimc.h,v 1.1.1.1 1997/06/01 03:17:13 ralf Exp $
   2  * sgimc.h: Definitions for memory controller hardware found on
   3  *          SGI IP20, IP22, IP26, and IP28 machines.
   4  *
   5  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   6  */
   7
   8 #ifndef _MIPS_SGIMC_H
   9 #define _MIPS_SGIMC_H
  10
  11 struct sgimc_misc_ctrl {
  12         unsigned long _unused1;
  13         volatile unsigned long cpuctrl0;     /* CPU control register 0, readwrite */
  14 #define SGIMC_CCTRL0_REFS         0x0000000f /* REFS mask */
  15 #define SGIMC_CCTRL0_EREFRESH     0x00000010 /* Memory refresh enable */
  16 #define SGIMC_CCTRL0_EPERRGIO     0x00000020 /* GIO parity error enable */
  17 #define SGIMC_CCTRL0_EPERRMEM     0x00000040 /* Main mem parity error enable */
  18 #define SGIMC_CCTRL0_EPERRCPU     0x00000080 /* CPU bus parity error enable */
  19 #define SGIMC_CCTRL0_WDOG         0x00000100 /* Watchdog timer enable */
  20 #define SGIMC_CCTRL0_SYSINIT      0x00000200 /* System init bit */
  21 #define SGIMC_CCTRL0_GFXRESET     0x00000400 /* Graphics interface reset */
  22 #define SGIMC_CCTRL0_EISALOCK     0x00000800 /* Lock CPU from memory for EISA */
  23 #define SGIMC_CCTRL0_EPERRSCMD    0x00001000 /* SysCMD bus parity error enable */
  24 #define SGIMC_CCTRL0_IENAB        0x00002000 /* Allow interrupts from MC */
  25 #define SGIMC_CCTRL0_ESNOOP       0x00004000 /* Snooping I/O enable */
  26 #define SGIMC_CCTRL0_EPROMWR      0x00008000 /* Prom writes from cpu enable */
  27 #define SGIMC_CCTRL0_WRESETPMEM   0x00010000 /* Perform warm reset, preserves mem */
  28 #define SGIMC_CCTRL0_LENDIAN      0x00020000 /* Put MC in little-endian mode */
  29 #define SGIMC_CCTRL0_WRESETDMEM   0x00040000 /* Warm reset, destroys mem contents */
  30 #define SGIMC_CCTRL0_CMEMBADPAR   0x02000000 /* Generate bad perr from cpu to mem */
  31 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
  32 #define SGIMC_CCTRL0_GIOBTOB      0x08000000 /* Allow GIO back to back writes */
  33
  34         unsigned long _unused2;
  35         volatile unsigned long cpuctrl1;     /* CPU control register 1, readwrite */
  36 #define SGIMC_CCTRL1_EGIOTIMEO    0x00000010 /* GIO bus timeout enable */
  37 #define SGIMC_CCTRL1_FIXEDEHPC    0x00001000 /* Fixed HPC endianness */
  38 #define SGIMC_CCTRL1_LITTLEHPC    0x00002000 /* Little endian HPC */
  39 #define SGIMC_CCTRL1_FIXEDEEXP0   0x00004000 /* Fixed EXP0 endianness */
  40 #define SGIMC_CCTRL1_LITTLEEXP0   0x00008000 /* Little endian EXP0 */
  41 #define SGIMC_CCTRL1_FIXEDEEXP1   0x00010000 /* Fixed EXP1 endianness */
  42 #define SGIMC_CCTRL1_LITTLEEXP1   0x00020000 /* Little endian EXP1 */
  43
  44         unsigned long _unused3;
  45         volatile unsigned long watchdogt;    /* Watchdog reg rdonly, write clears */
  46
  47         unsigned long _unused4;
  48         volatile unsigned long systemid;     /* MC system ID register, readonly */
  49 #define SGIMC_SYSID_MASKREV       0x0000000f /* Revision of MC controller */
  50 #define SGIMC_SYSID_EPRESENT      0x00000010 /* Indicates presence of EISA bus */
  51
  52         unsigned long _unused5[3];
  53         volatile unsigned long divider;      /* Divider reg for RPSS */
  54
  55         unsigned long _unused6;
  56         volatile unsigned char eeprom;       /* EEPROM byte reg for r4k */
  57 #define SGIMC_EEPROM_PRE          0x00000001 /* eeprom chip PRE pin assertion */
  58 #define SGIMC_EEPROM_CSEL         0x00000002 /* Active high, eeprom chip select */
  59 #define SGIMC_EEPROM_SECLOCK      0x00000004 /* EEPROM serial clock */
  60 #define SGIMC_EEPROM_SDATAO       0x00000008 /* Serial EEPROM data-out */
  61 #define SGIMC_EEPROM_SDATAI       0x00000010 /* Serial EEPROM data-in */
  62
  63         unsigned char _unused7[3];
  64         unsigned long _unused8[3];
  65         volatile unsigned short rcntpre;     /* Preload refresh counter */
  66
  67         unsigned short _unused9;
  68         unsigned long _unused9a;
  69         volatile unsigned short rcounter;    /* Readonly refresh counter */
  70
  71         unsigned short _unused10;
  72         unsigned long _unused11[13];
  73         volatile unsigned long gioparm;      /* Parameter word for GIO64 */
  74 #define SGIMC_GIOPARM_HPC64       0x00000001 /* HPC talks to GIO using 64-bits */
  75 #define SGIMC_GIOPARM_GFX64       0x00000002 /* GFX talks to GIO using 64-bits */
  76 #define SGIMC_GIOPARM_EXP064      0x00000004 /* EXP(slot0) talks using 64-bits */
  77 #define SGIMC_GIOPARM_EXP164      0x00000008 /* EXP(slot1) talks using 64-bits */
  78 #define SGIMC_GIOPARM_EISA64      0x00000010 /* EISA bus talks 64-bits to GIO */
  79 #define SGIMC_GIOPARM_HPC264      0x00000020 /* 2nd HPX talks 64-bits to GIO */
  80 #define SGIMC_GIOPARM_RTIMEGFX    0x00000040 /* GFX device has realtime attr */
  81 #define SGIMC_GIOPARM_RTIMEEXP0   0x00000080 /* EXP(slot0) has realtime attr */
  82 #define SGIMC_GIOPARM_RTIMEEXP1   0x00000100 /* EXP(slot1) has realtime attr */
  83 #define SGIMC_GIOPARM_MASTEREISA  0x00000200 /* EISA bus can act as bus master */
  84 #define SGIMC_GIOPARM_ONEBUS      0x00000400 /* Exists one GIO64 pipelined bus */
  85 #define SGIMC_GIOPARM_MASTERGFX   0x00000800 /* GFX can act as a bus master */
  86 #define SGIMC_GIOPARM_MASTEREXP0  0x00001000 /* EXP(slot0) can bus master */
  87 #define SGIMC_GIOPARM_MASTEREXP1  0x00002000 /* EXP(slot1) can bus master */
  88 #define SGIMC_GIOPARM_PLINEEXP0   0x00004000 /* EXP(slot0) has pipeline attr */
  89 #define SGIMC_GIOPARM_PLINEEXP1   0x00008000 /* EXP(slot1) has pipeline attr */
  90
  91         unsigned long _unused13;
  92         volatile unsigned short cputp;       /* CPU bus arb time period */
  93
  94         unsigned short _unused14;
  95         unsigned long _unused15[3];
  96         volatile unsigned short lbursttp;    /* Time period for long bursts */
  97
  98         unsigned short _unused16;
  99         unsigned long _unused17[9];
 100         volatile unsigned long mconfig0;     /* Memory config register zero */
 101         unsigned long _unused18;
 102         volatile unsigned long mconfig1;     /* Memory config register one */
 103
 104         /* These defines apply to both mconfig registers above. */
 105 #define SGIMC_MCONFIG_FOURMB     0x00000000  /* Physical ram = 4megs */
 106 #define SGIMC_MCONFIG_EIGHTMB    0x00000100  /* Physical ram = 8megs */
 107 #define SGIMC_MCONFIG_SXTEENMB   0x00000300  /* Physical ram = 16megs */
 108 #define SGIMC_MCONFIG_TTWOMB     0x00000700  /* Physical ram = 32megs */
 109 #define SGIMC_MCONFIG_SFOURMB    0x00000f00  /* Physical ram = 64megs */
 110 #define SGIMC_MCONFIG_OTEIGHTMB  0x00001f00  /* Physical ram = 128megs */
 111 #define SGIMC_MCONFIG_RMASK      0x00001f00  /* Ram config bitmask */
 112
 113         unsigned long _unused19;
 114         volatile unsigned long cmacc;        /* Mem access config for CPU */
 115         unsigned long _unused20;
 116         volatile unsigned long gmacc;        /* Mem access config for GIO */
 117
 118         /* This define applies to both cmacc and gmacc registers above. */
 119 #define SGIMC_MACC_ALIASBIG       0x20000000 /* 512MB home for alias */
 120
 121         /* Error address/status regs from GIO and CPU perspectives. */
 122         unsigned long _unused21;
 123         volatile unsigned long cerr;         /* Error address reg for CPU */
 124         unsigned long _unused22;
 125         volatile unsigned long cstat;        /* Status reg for CPU */
 126         unsigned long _unused23;
 127         volatile unsigned long gerr;         /* Error address reg for GIO */
 128         unsigned long _unused24;
 129         volatile unsigned long gstat;        /* Status reg for GIO */
 130
 131         /* Special hard bus locking registers. */
 132         unsigned long _unused25;
 133         volatile unsigned char syssembit;    /* Uni-bit system semaphore */
 134         unsigned char _unused26[3];
 135         unsigned long _unused27;
 136         volatile unsigned char mlock;        /* Global GIO memory access lock */
 137         unsigned char _unused28[3];
 138         unsigned long _unused29;
 139         volatile unsigned char elock;        /* Locks EISA from GIO accesses */
 140
 141         /* GIO dma control registers. */
 142         unsigned char _unused30[3];
 143         unsigned long _unused31[14];
 144         volatile unsigned long gio_dma_trans;/* DMA mask to translation GIO addrs */
 145         unsigned long _unused32;
 146         volatile unsigned long gio_dma_sbits;/* DMA GIO addr substitution bits */
 147         unsigned long _unused33;
 148         volatile unsigned long dma_intr_cause; /* DMA IRQ cause indicator bits */
 149         unsigned long _unused34;
 150         volatile unsigned long dma_ctrl;     /* Main DMA control reg */
 151
 152         /* DMA TLB entry 0 */
 153         unsigned long _unused35;
 154         volatile unsigned long dtlb_hi0;
 155         unsigned long _unused36;
 156         volatile unsigned long dtlb_lo0;
 157
 158         /* DMA TLB entry 1 */
 159         unsigned long _unused37;
 160         volatile unsigned long dtlb_hi1;
 161         unsigned long _unused38;
 162         volatile unsigned long dtlb_lo1;
 163
 164         /* DMA TLB entry 2 */
 165         unsigned long _unused39;
 166         volatile unsigned long dtlb_hi2;
 167         unsigned long _unused40;
 168         volatile unsigned long dtlb_lo2;
 169
 170         /* DMA TLB entry 3 */
 171         unsigned long _unused41;
 172         volatile unsigned long dtlb_hi3;
 173         unsigned long _unused42;
 174         volatile unsigned long dtlb_lo3;
 175 };
 176
 177 /* MC misc control registers live at physical 0x1fa00000. */
 178 extern struct sgimc_misc_ctrl *mcmisc_regs;
 179 extern unsigned long *rpsscounter;          /* Chirps at 100ns */
 180
 181 struct sgimc_dma_ctrl {
 182         unsigned long _unused1;
 183         volatile unsigned long maddronly;   /* Address DMA goes at */
 184         unsigned long _unused2;
 185         volatile unsigned long maddrpdeflts; /* Same as above, plus set defaults */
 186         unsigned long _unused3;
 187         volatile unsigned long dmasz;       /* DMA count */
 188         unsigned long _unused4;
 189         volatile unsigned long ssize;       /* DMA stride size */
 190         unsigned long _unused5;
 191         volatile unsigned long gmaddronly;  /* Set GIO DMA but do not start trans */
 192         unsigned long _unused6;
 193         volatile unsigned long dmaddnpgo;   /* Set GIO DMA addr + start transfer */
 194         unsigned long _unused7;
 195         volatile unsigned long dmamode;     /* DMA mode config bit settings */
 196         unsigned long _unused8;
 197         volatile unsigned long dmacount;    /* Zoom and byte count for DMA */
 198         unsigned long _unused9;
 199         volatile unsigned long dmastart;    /* Pedal to the metal. */
 200         unsigned long _unused10;
 201         volatile unsigned long dmarunning;  /* DMA op is in progress */
 202         unsigned long _unused11;
 203
 204         /* Set dma addr, defaults, and kick it */
 205         volatile unsigned long maddr_defl_go; /* go go go! -lm */
 206 };
 207
 208 /* MC controller dma regs live at physical 0x1fa02000. */
 209 extern struct sgimc_dma_ctrl *dmactrlregs;
 210
 211 /* Base location of the two ram banks found in IP2[0268] machines. */
 212 #define SGIMC_SEG0_BADDR     0x08000000
 213 #define SGIMC_SEG1_BADDR     0x20000000
 214
 215 /* Maximum size of the above banks are per machine. */
 216 extern unsigned long sgimc_seg0_size, sgimc_seg1_size;
 217 #define SGIMC_SEG0_SIZE_ALL         0x10000000 /* 256MB */
 218 #define SGIMC_SEG1_SIZE_IP20_IP22   0x08000000 /* 128MB */
 219 #define SGIMC_SEG1_SIZE_IP26_IP28   0x20000000 /* 512MB */
 220
 221 extern void sgimc_init(void);
 222
 223 #endif /* !(_MIPS_SGIMC_H) */