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Import 2.3.18pre1
[davej-history.git] / include / asm-mips / mipsregs.h
blob4796db4586b723b4c32df6a1327f76d58fb138e5
1 /* $Id: mipsregs.h,v 1.6 1998/08/17 11:27:08 ralf Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 */
10 #ifndef __ASM_MIPS_MIPSREGS_H
11 #define __ASM_MIPS_MIPSREGS_H
12
13 #include <linux/linkage.h>
14
15 /*
16 * The following macros are especially useful for __asm__
17 * inline assembler.
18 */
19 #ifndef __STR
20 #define __STR(x) #x
21 #endif
22 #ifndef STR
23 #define STR(x) __STR(x)
24 #endif
25
26 /*
27 * Coprocessor 0 register names
28 */
29 #define CP0_INDEX $0
30 #define CP0_RANDOM $1
31 #define CP0_ENTRYLO0 $2
32 #define CP0_ENTRYLO1 $3
33 #define CP0_CONTEXT $4
34 #define CP0_PAGEMASK $5
35 #define CP0_WIRED $6
36 #define CP0_BADVADDR $8
37 #define CP0_COUNT $9
38 #define CP0_ENTRYHI $10
39 #define CP0_COMPARE $11
40 #define CP0_STATUS $12
41 #define CP0_CAUSE $13
42 #define CP0_EPC $14
43 #define CP0_PRID $15
44 #define CP0_CONFIG $16
45 #define CP0_LLADDR $17
46 #define CP0_WATCHLO $18
47 #define CP0_WATCHHI $19
48 #define CP0_XCONTEXT $20
49 #define CP0_FRAMEMASK $21
50 #define CP0_DIAGNOSTIC $22
51 #define CP0_PERFORMANCE $25
52 #define CP0_ECC $26
53 #define CP0_CACHEERR $27
54 #define CP0_TAGLO $28
55 #define CP0_TAGHI $29
56 #define CP0_ERROREPC $30
57
58 /*
59 * R4640/R4650 cp0 register names. These registers are listed
60 * here only for completeness; without MMU these CPUs are not useable
61 * by Linux. A future ELKS port might take make Linux run on them
62 * though ...
63 */
64 #define CP0_IBASE $0
65 #define CP0_IBOUND $1
66 #define CP0_DBASE $2
67 #define CP0_DBOUND $3
68 #define CP0_CALG $17
69 #define CP0_IWATCH $18
70 #define CP0_DWATCH $19
71
72 /*
73 * Coprocessor 1 (FPU) register names
74 */
75 #define CP1_REVISION $0
76 #define CP1_STATUS $31
77
78 /*
79 * Values for PageMask register
80 */
81 #define PM_4K 0x00000000
82 #define PM_16K 0x00006000
83 #define PM_64K 0x0001e000
84 #define PM_256K 0x0007e000
85 #define PM_1M 0x001fe000
86 #define PM_4M 0x007fe000
87 #define PM_16M 0x01ffe000
88
89 /*
90 * Values used for computation of new tlb entries
91 */
92 #define PL_4K 12
93 #define PL_16K 14
94 #define PL_64K 16
95 #define PL_256K 18
96 #define PL_1M 20
97 #define PL_4M 22
98 #define PL_16M 24
99
100 /*
101 * Macros to access the system control coprocessor
102 */
103 #define read_32bit_cp0_register(source) \
104 ({ int __res; \
105 __asm__ __volatile__( \
106 "mfc0\t%0,"STR(source) \
107 : "=r" (__res)); \
108 __res;})
109
110 /*
111 * For now use this only with interrupts disabled!
112 */
113 #define read_64bit_cp0_register(source) \
114 ({ int __res; \
115 __asm__ __volatile__( \
116 ".set\tmips3\n\t" \
117 "dmfc0\t%0,"STR(source)"\n\t" \
118 ".set\tmips0" \
119 : "=r" (__res)); \
120 __res;})
121
122 #define write_32bit_cp0_register(register,value) \
123 __asm__ __volatile__( \
124 "mtc0\t%0,"STR(register) \
125 : : "r" (value));
126
127 #define write_64bit_cp0_register(register,value) \
128 __asm__ __volatile__( \
129 ".set\tmips3\n\t" \
130 "dmtc0\t%0,"STR(register)"\n\t" \
131 ".set\tmips0" \
132 : : "r" (value))
133 /*
134 * R4x00 interrupt enable / cause bits
135 */
136 #define IE_SW0 (1<< 8)
137 #define IE_SW1 (1<< 9)
138 #define IE_IRQ0 (1<<10)
139 #define IE_IRQ1 (1<<11)
140 #define IE_IRQ2 (1<<12)
141 #define IE_IRQ3 (1<<13)
142 #define IE_IRQ4 (1<<14)
143 #define IE_IRQ5 (1<<15)
144
145 /*
146 * R4x00 interrupt cause bits
147 */
148 #define C_SW0 (1<< 8)
149 #define C_SW1 (1<< 9)
150 #define C_IRQ0 (1<<10)
151 #define C_IRQ1 (1<<11)
152 #define C_IRQ2 (1<<12)
153 #define C_IRQ3 (1<<13)
154 #define C_IRQ4 (1<<14)
155 #define C_IRQ5 (1<<15)
156
157 #ifndef _LANGUAGE_ASSEMBLY
158 /*
159 * Manipulate the status register.
160 * Mostly used to access the interrupt bits.
161 */
162 #define __BUILD_SET_CP0(name,register) \
163 extern __inline__ unsigned int \
164 set_cp0_##name(unsigned int change, unsigned int new) \
165 { \
166 unsigned int res; \
167 \
168 res = read_32bit_cp0_register(register); \
169 res &= ~change; \
170 res |= (new & change); \
171 if(change) \
172 write_32bit_cp0_register(register, res); \
173 \
174 return res; \
175 }
176
177 __BUILD_SET_CP0(status,CP0_STATUS)
178 __BUILD_SET_CP0(cause,CP0_CAUSE)
179 __BUILD_SET_CP0(config,CP0_CONFIG)
180
181 #endif /* defined (_LANGUAGE_ASSEMBLY) */
182
183 /*
184 * Inline code for use of the ll and sc instructions
185 *
186 * FIXME: This instruction is only available on MIPS ISA >=2.
187 * Since these operations are only being used for atomic operations
188 * the easiest workaround for the R[23]00 is to disable interrupts.
189 * This fails for R3000 SMP machines which use that many different
190 * technologies as replacement that it is difficult to create even
191 * just a hook for for all machines to hook into. The only good
192 * thing is that there is currently no R3000 SMP machine on the
193 * Linux/MIPS target list ...
194 */
195 #define load_linked(addr) \
196 ({ \
197 unsigned int __res; \
198 \
199 __asm__ __volatile__( \
200 "ll\t%0,(%1)" \
201 : "=r" (__res) \
202 : "r" ((unsigned long) (addr))); \
203 \
204 __res; \
205 })
206
207 #define store_conditional(addr,value) \
208 ({ \
209 int __res; \
210 \
211 __asm__ __volatile__( \
212 "sc\t%0,(%2)" \
213 : "=r" (__res) \
214 : "0" (value), "r" (addr)); \
215 \
216 __res; \
217 })
218
219 /*
220 * Bitfields in the R4xx0 cp0 status register
221 */
222 #define ST0_IE 0x00000001
223 #define ST0_EXL 0x00000002
224 #define ST0_ERL 0x00000004
225 #define ST0_KSU 0x00000018
226 # define KSU_USER 0x00000010
227 # define KSU_SUPERVISOR 0x00000008
228 # define KSU_KERNEL 0x00000000
229 #define ST0_UX 0x00000020
230 #define ST0_SX 0x00000040
231 #define ST0_KX 0x00000080
232
233 /*
234 * Bitfields in the R[23]000 cp0 status register.
235 */
236 #define ST0_IEC 0x00000001
237 #define ST0_KUC 0x00000002
238 #define ST0_IEP 0x00000004
239 #define ST0_KUP 0x00000008
240 #define ST0_IEO 0x00000010
241 #define ST0_KUO 0x00000020
242 /* bits 6 & 7 are reserved on R[23]000 */
243
244 /*
245 * Bits specific to the R4640/R4650
246 */
247 #define ST0_UM <1 << 4)
248 #define ST0_IL (1 << 23)
249 #define ST0_DL (1 << 24)
250
251 /*
252 * Status register bits available in all MIPS CPUs.
253 */
254 #define ST0_IM 0x0000ff00
255 #define STATUSB_IP0 8
256 #define STATUSF_IP0 (1 << 8)
257 #define STATUSB_IP1 9
258 #define STATUSF_IP1 (1 << 9)
259 #define STATUSB_IP2 10
260 #define STATUSF_IP2 (1 << 10)
261 #define STATUSB_IP3 11
262 #define STATUSF_IP3 (1 << 11)
263 #define STATUSB_IP4 12
264 #define STATUSF_IP4 (1 << 12)
265 #define STATUSB_IP5 13
266 #define STATUSF_IP5 (1 << 13)
267 #define STATUSB_IP6 14
268 #define STATUSF_IP6 (1 << 14)
269 #define STATUSB_IP7 15
270 #define STATUSF_IP7 (1 << 15)
271 #define ST0_DE 0x00010000
272 #define ST0_CE 0x00020000
273 #define ST0_CH 0x00040000
274 #define ST0_SR 0x00100000
275 #define ST0_BEV 0x00400000
276 #define ST0_RE 0x02000000
277 #define ST0_FR 0x04000000
278 #define ST0_CU 0xf0000000
279 #define ST0_CU0 0x10000000
280 #define ST0_CU1 0x20000000
281 #define ST0_CU2 0x40000000
282 #define ST0_CU3 0x80000000
283 #define ST0_XX 0x80000000 /* MIPS IV naming */
284
285 /*
286 * Bitfields and bit numbers in the coprocessor 0 cause register.
287 *
288 * Refer to to your MIPS R4xx0 manual, chapter 5 for explanation.
289 */
290 #define CAUSEB_EXCCODE 2
291 #define CAUSEF_EXCCODE (31 << 2)
292 #define CAUSEB_IP 8
293 #define CAUSEF_IP (255 << 8)
294 #define CAUSEB_IP0 8
295 #define CAUSEF_IP0 (1 << 8)
296 #define CAUSEB_IP1 9
297 #define CAUSEF_IP1 (1 << 9)
298 #define CAUSEB_IP2 10
299 #define CAUSEF_IP2 (1 << 10)
300 #define CAUSEB_IP3 11
301 #define CAUSEF_IP3 (1 << 11)
302 #define CAUSEB_IP4 12
303 #define CAUSEF_IP4 (1 << 12)
304 #define CAUSEB_IP5 13
305 #define CAUSEF_IP5 (1 << 13)
306 #define CAUSEB_IP6 14
307 #define CAUSEF_IP6 (1 << 14)
308 #define CAUSEB_IP7 15
309 #define CAUSEF_IP7 (1 << 15)
310 #define CAUSEB_IV 23
311 #define CAUSEF_IV (1 << 23)
312 #define CAUSEB_CE 28
313 #define CAUSEF_CE (3 << 28)
314 #define CAUSEB_BD 31
315 #define CAUSEF_BD (1 << 31)
316
317 /*
318 * Bits in the coprozessor 0 config register.
319 */
320 #define CONF_CM_CACHABLE_NO_WA 0
321 #define CONF_CM_CACHABLE_WA 1
322 #define CONF_CM_UNCACHED 2
323 #define CONF_CM_CACHABLE_NONCOHERENT 3
324 #define CONF_CM_CACHABLE_CE 4
325 #define CONF_CM_CACHABLE_COW 5
326 #define CONF_CM_CACHABLE_CUW 6
327 #define CONF_CM_CACHABLE_ACCELERATED 7
328 #define CONF_CM_CMASK 7
329 #define CONF_DB (1 << 4)
330 #define CONF_IB (1 << 5)
331 #define CONF_SC (1 << 17)
332
333 /*
334 * R10000 performance counter definitions.
335 *
336 * FIXME: The R10000 performance counter opens a nice way to implement CPU
337 * time accounting with a precission of one cycle. I don't have
338 * R10000 silicon but just a manual, so ...
339 */
340
341 /*
342 * Events counted by counter #0
343 */
344 #define CE0_CYCLES 0
345 #define CE0_INSN_ISSUED 1
346 #define CE0_LPSC_ISSUED 2
347 #define CE0_S_ISSUED 3
348 #define CE0_SC_ISSUED 4
349 #define CE0_SC_FAILED 5
350 #define CE0_BRANCH_DECODED 6
351 #define CE0_QW_WB_SECONDARY 7
352 #define CE0_CORRECTED_ECC_ERRORS 8
353 #define CE0_ICACHE_MISSES 9
354 #define CE0_SCACHE_I_MISSES 10
355 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
356 #define CE0_EXT_INTERVENTIONS_REQ 12
357 #define CE0_EXT_INVALIDATE_REQ 13
358 #define CE0_VIRTUAL_COHERENCY_COND 14
359 #define CE0_INSN_GRADUATED 15
360
361 /*
362 * Events counted by counter #1
363 */
364 #define CE1_CYCLES 0
365 #define CE1_INSN_GRADUATED 1
366 #define CE1_LPSC_GRADUATED 2
367 #define CE1_S_GRADUATED 3
368 #define CE1_SC_GRADUATED 4
369 #define CE1_FP_INSN_GRADUATED 5
370 #define CE1_QW_WB_PRIMARY 6
371 #define CE1_TLB_REFILL 7
372 #define CE1_BRANCH_MISSPREDICTED 8
373 #define CE1_DCACHE_MISS 9
374 #define CE1_SCACHE_D_MISSES 10
375 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
376 #define CE1_EXT_INTERVENTION_HITS 12
377 #define CE1_EXT_INVALIDATE_REQ 13
378 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
379 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
380
381 /*
382 * These flags define in which priviledge mode the counters count events
383 */
384 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
385 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
386 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
387 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
388
389 #ifndef _LANGUAGE_ASSEMBLY
390 /*
391 * Functions to access the performance counter and control registers
392 */
393 extern asmlinkage unsigned int read_perf_cntr(unsigned int counter);
394 extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val);
395 extern asmlinkage unsigned int read_perf_cntl(unsigned int counter);
396 extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val);
397 #endif
398
399 #endif /* __ASM_MIPS_MIPSREGS_H */
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