include/asm-mips/io.h

   1 #ifndef __ASM_MIPS_IO_H
   2 #define __ASM_MIPS_IO_H
   3
   4 /*
   5  * Slowdown I/O port space accesses for antique hardware.
   6  */
   7 #undef CONF_SLOWDOWN_IO
   8
   9 #include <asm/mipsconfig.h>
  10 #include <asm/addrspace.h>
  11
  12 /*
  13  * This file contains the definitions for the MIPS counterpart of the
  14  * x86 in/out instructions. This heap of macros and C results in much
  15  * better code than the approach of doing it in plain C.  The macros
  16  * result in code that is to fast for certain hardware.  On the other
  17  * side the performance of the string functions should be improved for
  18  * sake of certain devices like EIDE disks that do highspeed polled I/O.
  19  *
  20  *   Ralf
  21  *
  22  * This file contains the definitions for the x86 IO instructions
  23  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
  24  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
  25  * versions of the single-IO instructions (inb_p/inw_p/..).
  26  *
  27  * This file is not meant to be obfuscating: it's just complicated
  28  * to (a) handle it all in a way that makes gcc able to optimize it
  29  * as well as possible and (b) trying to avoid writing the same thing
  30  * over and over again with slight variations and possibly making a
  31  * mistake somewhere.
  32  */
  33
  34 /*
  35  * On MIPS I/O ports are memory mapped, so we access them using normal
  36  * load/store instructions. mips_io_port_base is the virtual address to
  37  * which all ports are being mapped.  For sake of efficiency some code
  38  * assumes that this is an address that can be loaded with a single lui
  39  * instruction, so the lower 16 bits must be zero.  Should be true on
  40  * on any sane architecture; generic code does not use this assumption.
  41  */
  42 extern unsigned long mips_io_port_base;
  43
  44 /*
  45  * Thanks to James van Artsdalen for a better timing-fix than
  46  * the two short jumps: using outb's to a nonexistent port seems
  47  * to guarantee better timings even on fast machines.
  48  *
  49  * On the other hand, I'd like to be sure of a non-existent port:
  50  * I feel a bit unsafe about using 0x80 (should be safe, though)
  51  *
  52  *              Linus
  53  *
  54  */
  55
  56 #define __SLOW_DOWN_IO \
  57         __asm__ __volatile__( \
  58                 "sb\t$0,0x80(%0)" \
  59                 : : "r" (mips_io_port_base));
  60
  61 #ifdef CONF_SLOWDOWN_IO
  62 #ifdef REALLY_SLOW_IO
  63 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
  64 #else
  65 #define SLOW_DOWN_IO __SLOW_DOWN_IO
  66 #endif
  67 #else
  68 #define SLOW_DOWN_IO
  69 #endif
  70
  71 /*
  72  * Change virtual addresses to physical addresses and vv.
  73  * These are trivial on the 1:1 Linux/MIPS mapping
  74  */
  75 extern inline unsigned long virt_to_phys(volatile void * address)
  76 {
  77         return PHYSADDR(address);
  78 }
  79
  80 extern inline void * phys_to_virt(unsigned long address)
  81 {
  82         return (void *)KSEG0ADDR(address);
  83 }
  84
  85 extern void * ioremap(unsigned long phys_addr, unsigned long size);
  86 extern void iounmap(void *addr);
  87
  88 /*
  89  * IO bus memory addresses are also 1:1 with the physical address
  90  */
  91 extern inline unsigned long virt_to_bus(volatile void * address)
  92 {
  93         return PHYSADDR(address);
  94 }
  95
  96 extern inline void * bus_to_virt(unsigned long address)
  97 {
  98         return (void *)KSEG0ADDR(address);
  99 }
 100
 101 /*
 102  * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
 103  * for the processor.
 104  */
 105 extern unsigned long isa_slot_offset;
 106
 107 /*
 108  * readX/writeX() are used to access memory mapped devices. On some
 109  * architectures the memory mapped IO stuff needs to be accessed
 110  * differently. On the x86 architecture, we just read/write the
 111  * memory location directly.
 112  *
 113  * On MIPS, we have the whole physical address space mapped at all
 114  * times, so "ioremap()" and "iounmap()" do not need to do anything.
 115  * (This isn't true for all machines but we still handle these cases
 116  * with wired TLB entries anyway ...)
 117  *
 118  * We cheat a bit and always return uncachable areas until we've fixed
 119  * the drivers to handle caching properly.
 120  */
 121 extern inline void * ioremap(unsigned long offset, unsigned long size)
 122 {
 123         return (void *) KSEG1ADDR(offset);
 124 }
 125
 126 /*
 127  * This one maps high address device memory and turns off caching for that area.
 128  * it's useful if some control registers are in such an area and write combining
 129  * or read caching is not desirable:
 130  */
 131 extern inline void * ioremap_nocache (unsigned long offset, unsigned long size)
 132 {
 133         return (void *) KSEG1ADDR(offset);
 134 }
 135
 136 extern inline void iounmap(void *addr)
 137 {
 138 }
 139
 140 /*
 141  * XXX We need system specific versions of these to handle EISA address bits
 142  * 24-31 on SNI.
 143  * XXX more SNI hacks.
 144  */
 145 #define readb(addr) (*(volatile unsigned char *) (0xa0000000 + (unsigned long)(addr)))
 146 #define readw(addr) (*(volatile unsigned short *) (0xa0000000 + (unsigned long)(addr)))
 147 #define readl(addr) (*(volatile unsigned int *) (0xa0000000 + (unsigned long)(addr)))
 148
 149 #define writeb(b,addr) (*(volatile unsigned char *) (0xa0000000 + (unsigned long)(addr)) = (b))
 150 #define writew(b,addr) (*(volatile unsigned short *) (0xa0000000 + (unsigned long)(addr)) = (b))
 151 #define writel(b,addr) (*(volatile unsigned int *) (0xa0000000 + (unsigned long)(addr)) = (b))
 152
 153 #define memset_io(a,b,c)        memset((void *)(0xa0000000 + (unsigned long)a),(b),(c))
 154 #define memcpy_fromio(a,b,c)    memcpy((a),(void *)(0xa0000000 + (unsigned long)(b)),(c))
 155 #define memcpy_toio(a,b,c)      memcpy((void *)(0xa0000000 + (unsigned long)(a)),(b),(c))
 156
 157 /* END SNI HACKS ... */
 158
 159 /*
 160  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
 161  * just copy it. The net code will then do the checksum later.
 162  */
 163 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
 164
 165 static inline int check_signature(unsigned long io_addr,
 166                                   const unsigned char *signature, int length)
 167 {
 168         int retval = 0;
 169         do {
 170                 if (readb(io_addr) != *signature)
 171                         goto out;
 172                 io_addr++;
 173                 signature++;
 174                 length--;
 175         } while (length);
 176         retval = 1;
 177 out:
 178         return retval;
 179 }
 180
 181 /*
 182  * Talk about misusing macros..
 183  */
 184
 185 #define __OUT1(s) \
 186 extern inline void __out##s(unsigned int value, unsigned int port) {
 187
 188 #define __OUT2(m) \
 189 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
 190
 191 #define __OUT(m,s) \
 192 __OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); } \
 193 __OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); } \
 194 __OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); \
 195         SLOW_DOWN_IO; } \
 196 __OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); \
 197         SLOW_DOWN_IO; }
 198
 199 #define __IN1(t,s) \
 200 extern __inline__ t __in##s(unsigned int port) { t _v;
 201
 202 /*
 203  * Required nops will be inserted by the assembler
 204  */
 205 #define __IN2(m) \
 206 __asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
 207
 208 #define __IN(t,m,s) \
 209 __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return _v; } \
 210 __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return _v; } \
 211 __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return _v; } \
 212 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return _v; }
 213
 214 #define __INS1(s) \
 215 extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
 216
 217 #define __INS2(m) \
 218 if (count) \
 219 __asm__ __volatile__ ( \
 220         ".set\tnoreorder\n\t" \
 221         ".set\tnoat\n" \
 222         "1:\tl" #m "\t$1,%4(%5)\n\t" \
 223         "subu\t%1,1\n\t" \
 224         "s" #m "\t$1,(%0)\n\t" \
 225         "bne\t$0,%1,1b\n\t" \
 226         "addiu\t%0,%6\n\t" \
 227         ".set\tat\n\t" \
 228         ".set\treorder"
 229
 230 #define __INS(m,s,i) \
 231 __INS1(s) __INS2(m) \
 232         : "=r" (addr), "=r" (count) \
 233         : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
 234         : "$1");} \
 235 __INS1(s##c) __INS2(m) \
 236         : "=r" (addr), "=r" (count) \
 237         : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
 238         : "$1");}
 239
 240 #define __OUTS1(s) \
 241 extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
 242
 243 #define __OUTS2(m) \
 244 if (count) \
 245 __asm__ __volatile__ ( \
 246         ".set\tnoreorder\n\t" \
 247         ".set\tnoat\n" \
 248         "1:\tl" #m "\t$1,(%0)\n\t" \
 249         "subu\t%1,1\n\t" \
 250         "s" #m "\t$1,%4(%5)\n\t" \
 251         "bne\t$0,%1,1b\n\t" \
 252         "addiu\t%0,%6\n\t" \
 253         ".set\tat\n\t" \
 254         ".set\treorder"
 255
 256 #define __OUTS(m,s,i) \
 257 __OUTS1(s) __OUTS2(m) \
 258         : "=r" (addr), "=r" (count) \
 259         : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
 260         : "$1");} \
 261 __OUTS1(s##c) __OUTS2(m) \
 262         : "=r" (addr), "=r" (count) \
 263         : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
 264         : "$1");}
 265
 266 __IN(unsigned char,b,b)
 267 __IN(unsigned short,h,w)
 268 __IN(unsigned int,w,l)
 269
 270 __OUT(b,b)
 271 __OUT(h,w)
 272 __OUT(w,l)
 273
 274 __INS(b,b,1)
 275 __INS(h,w,2)
 276 __INS(w,l,4)
 277
 278 __OUTS(b,b,1)
 279 __OUTS(h,w,2)
 280 __OUTS(w,l,4)
 281
 282 /*
 283  * Note that due to the way __builtin_constant_p() works, you
 284  *  - can't use it inside an inline function (it will never be true)
 285  *  - you don't have to worry about side effects within the __builtin..
 286  */
 287 #define outb(val,port) \
 288 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 289         __outbc((val),(port)) : \
 290         __outb((val),(port)))
 291
 292 #define inb(port) \
 293 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 294         __inbc(port) : \
 295         __inb(port))
 296
 297 #define outb_p(val,port) \
 298 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 299         __outbc_p((val),(port)) : \
 300         __outb_p((val),(port)))
 301
 302 #define inb_p(port) \
 303 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 304         __inbc_p(port) : \
 305         __inb_p(port))
 306
 307 #define outw(val,port) \
 308 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 309         __outwc((val),(port)) : \
 310         __outw((val),(port)))
 311
 312 #define inw(port) \
 313 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 314         __inwc(port) : \
 315         __inw(port))
 316
 317 #define outw_p(val,port) \
 318 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 319         __outwc_p((val),(port)) : \
 320         __outw_p((val),(port)))
 321
 322 #define inw_p(port) \
 323 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 324         __inwc_p(port) : \
 325         __inw_p(port))
 326
 327 #define outl(val,port) \
 328 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 329         __outlc((val),(port)) : \
 330         __outl((val),(port)))
 331
 332 #define inl(port) \
 333 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 334         __inlc(port) : \
 335         __inl(port))
 336
 337 #define outl_p(val,port) \
 338 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 339         __outlc_p((val),(port)) : \
 340         __outl_p((val),(port)))
 341
 342 #define inl_p(port) \
 343 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 344         __inlc_p(port) : \
 345         __inl_p(port))
 346
 347
 348 #define outsb(port,addr,count) \
 349 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 350         __outsbc((port),(addr),(count)) : \
 351         __outsb ((port),(addr),(count)))
 352
 353 #define insb(port,addr,count) \
 354 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 355         __insbc((port),(addr),(count)) : \
 356         __insb((port),(addr),(count)))
 357
 358 #define outsw(port,addr,count) \
 359 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 360         __outswc((port),(addr),(count)) : \
 361         __outsw ((port),(addr),(count)))
 362
 363 #define insw(port,addr,count) \
 364 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 365         __inswc((port),(addr),(count)) : \
 366         __insw((port),(addr),(count)))
 367
 368 #define outsl(port,addr,count) \
 369 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 370         __outslc((port),(addr),(count)) : \
 371         __outsl ((port),(addr),(count)))
 372
 373 #define insl(port,addr,count) \
 374 ((__builtin_constant_p((port)) && (port) < 32768) ? \
 375         __inslc((port),(addr),(count)) : \
 376         __insl((port),(addr),(count)))
 377
 378 /*
 379  * The caches on some architectures aren't dma-coherent and have need to
 380  * handle this in software.  There are three types of operations that
 381  * can be applied to dma buffers.
 382  *
 383  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 384  *    writing the content of the caches back to memory, if necessary.
 385  *    The function also invalidates the affected part of the caches as
 386  *    necessary before DMA transfers from outside to memory.
 387  *  - dma_cache_wback(start, size) makes caches and coherent by
 388  *    writing the content of the caches back to memory, if necessary.
 389  *    The function also invalidates the affected part of the caches as
 390  *    necessary before DMA transfers from outside to memory.
 391  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 392  *    caches.  Dirty lines of the caches may be written back or simply
 393  *    be discarded.  This operation is necessary before dma operations
 394  *    to the memory.
 395  */
 396 extern void (*dma_cache_wback_inv)(unsigned long start, unsigned long size);
 397 extern void (*dma_cache_wback)(unsigned long start, unsigned long size);
 398 extern void (*dma_cache_inv)(unsigned long start, unsigned long size);
 399
 400 #endif /* __ASM_MIPS_IO_H */