include/asm-alpha/mmu_context.h

   1 #ifndef __ALPHA_MMU_CONTEXT_H
   2 #define __ALPHA_MMU_CONTEXT_H
   3
   4 /*
   5  * get a new mmu context..
   6  *
   7  * Copyright (C) 1996, Linus Torvalds
   8  */
   9
  10 #include <linux/config.h>
  11 #include <asm/system.h>
  12 #include <asm/machvec.h>
  13
  14
  15 /*
  16  * Force a context reload. This is needed when we change the page
  17  * table pointer or when we update the ASN of the current process.
  18  */
  19
  20 /* Don't get into trouble with dueling __EXTERN_INLINEs.  */
  21 #ifndef __EXTERN_INLINE
  22 #include <asm/io.h>
  23 #endif
  24
  25 extern inline unsigned long
  26 __reload_thread(struct thread_struct *pcb)
  27 {
  28         register unsigned long a0 __asm__("$16");
  29         register unsigned long v0 __asm__("$0");
  30
  31         a0 = virt_to_phys(pcb);
  32         __asm__ __volatile__(
  33                 "call_pal %2 #__reload_thread"
  34                 : "=r"(v0), "=r"(a0)
  35                 : "i"(PAL_swpctx), "r"(a0)
  36                 : "$1", "$16", "$22", "$23", "$24", "$25");
  37
  38         return v0;
  39 }
  40
  41
  42 /*
  43  * The maximum ASN's the processor supports.  On the EV4 this is 63
  44  * but the PAL-code doesn't actually use this information.  On the
  45  * EV5 this is 127, and EV6 has 255.
  46  *
  47  * On the EV4, the ASNs are more-or-less useless anyway, as they are
  48  * only used as an icache tag, not for TB entries.  On the EV5 and EV6,
  49  * ASN's also validate the TB entries, and thus make a lot more sense.
  50  *
  51  * The EV4 ASN's don't even match the architecture manual, ugh.  And
  52  * I quote: "If a processor implements address space numbers (ASNs),
  53  * and the old PTE has the Address Space Match (ASM) bit clear (ASNs
  54  * in use) and the Valid bit set, then entries can also effectively be
  55  * made coherent by assigning a new, unused ASN to the currently
  56  * running process and not reusing the previous ASN before calling the
  57  * appropriate PALcode routine to invalidate the translation buffer
  58  * (TB)".
  59  *
  60  * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually
  61  * work correctly and can thus not be used (explaining the lack of PAL-code
  62  * support).
  63  */
  64 #define EV4_MAX_ASN 63
  65 #define EV5_MAX_ASN 127
  66 #define EV6_MAX_ASN 255
  67
  68 #ifdef CONFIG_ALPHA_GENERIC
  69 # define MAX_ASN        (alpha_mv.max_asn)
  70 #else
  71 # ifdef CONFIG_ALPHA_EV4
  72 #  define MAX_ASN       EV4_MAX_ASN
  73 # elif defined(CONFIG_ALPHA_EV5)
  74 #  define MAX_ASN       EV5_MAX_ASN
  75 # else
  76 #  define MAX_ASN       EV6_MAX_ASN
  77 # endif
  78 #endif
  79
  80 /*
  81  * cpu_last_asn(processor):
  82  * 63                                            0
  83  * +-------------+----------------+--------------+
  84  * | asn version | this processor | hardware asn |
  85  * +-------------+----------------+--------------+
  86  */
  87
  88 #ifdef __SMP__
  89 #include <asm/smp.h>
  90 #define cpu_last_asn(cpuid)     (cpu_data[cpuid].last_asn)
  91 #else
  92 extern unsigned long last_asn;
  93 #define cpu_last_asn(cpuid)     last_asn
  94 #endif /* __SMP__ */
  95
  96 #define WIDTH_HARDWARE_ASN      8
  97 #ifdef __SMP__
  98 #define WIDTH_THIS_PROCESSOR    5
  99 #else
 100 #define WIDTH_THIS_PROCESSOR    0
 101 #endif
 102 #define ASN_FIRST_VERSION (1UL << (WIDTH_THIS_PROCESSOR + WIDTH_HARDWARE_ASN))
 103 #define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1)
 104
 105 /*
 106  * NOTE! The way this is set up, the high bits of the "asn_cache" (and
 107  * the "mm->context") are the ASN _version_ code. A version of 0 is
 108  * always considered invalid, so to invalidate another process you only
 109  * need to do "p->mm->context = 0".
 110  *
 111  * If we need more ASN's than the processor has, we invalidate the old
 112  * user TLB's (tbiap()) and start a new ASN version. That will automatically
 113  * force a new asn for any other processes the next time they want to
 114  * run.
 115  */
 116
 117 #ifndef __EXTERN_INLINE
 118 #define __EXTERN_INLINE extern inline
 119 #define __MMU_EXTERN_INLINE
 120 #endif
 121
 122 extern void get_new_mm_context(struct task_struct *p, struct mm_struct *mm);
 123
 124 static inline unsigned long
 125 __get_new_mm_context(struct mm_struct *mm, long cpu)
 126 {
 127         unsigned long asn = cpu_last_asn(cpu);
 128         unsigned long next = asn + 1;
 129
 130         if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) {
 131                 tbiap();
 132                 next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION;
 133         }
 134         cpu_last_asn(cpu) = next;
 135         return next;
 136 }
 137
 138 __EXTERN_INLINE void
 139 ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
 140               struct task_struct *next, long cpu)
 141 {
 142         /* As described, ASN's are broken.  But we can optimize for
 143            switching between threads -- if the mm is unchanged from
 144            current we needn't flush.  */
 145         /* ??? May not be needed because EV4 PALcode recognizes that
 146            ASN's are broken and does a tbiap itself on swpctx, under
 147            the "Must set ASN or flush" rule.  At least this is true
 148            for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com).
 149            I'm going to leave this here anyway, just to Be Sure.  -- r~  */
 150
 151         if (prev_mm != next_mm)
 152                 tbiap();
 153 }
 154
 155 __EXTERN_INLINE void
 156 ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, long cpu)
 157 {
 158         /* This is only called after changing mm on current.  */
 159         tbiap();
 160
 161         current->thread.ptbr
 162           = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
 163 }
 164
 165 __EXTERN_INLINE void
 166 ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
 167               struct task_struct *next, long cpu)
 168 {
 169         /* Check if our ASN is of an older version, or on a different CPU,
 170            and thus invalid.  */
 171         /* ??? If we have two threads on different cpus, we'll continually
 172            fight over the context.  Find a way to record a per-mm, per-cpu
 173            value for the asn.  */
 174
 175         unsigned long asn = cpu_last_asn(cpu);
 176         unsigned long mmc = next_mm->context;
 177
 178         if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) {
 179                 mmc = __get_new_mm_context(next_mm, cpu);
 180                 next_mm->context = mmc;
 181         }
 182
 183         /* Always update the PCB ASN.  Another thread may have allocated
 184            a new mm->context (via flush_tlb_mm) without the ASN serial
 185            number wrapping.  We have no way to detect when this is needed.  */
 186         next->thread.asn = mmc & HARDWARE_ASN_MASK;
 187 }
 188
 189 __EXTERN_INLINE void
 190 ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, long cpu)
 191 {
 192         unsigned long mmc = __get_new_mm_context(next_mm, cpu);
 193         next_mm->context = mmc;
 194         current->thread.asn = mmc & HARDWARE_ASN_MASK;
 195         current->thread.ptbr
 196           = ((unsigned long) next_mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
 197
 198         __reload_thread(&current->thread);
 199 }
 200
 201
 202 #ifdef CONFIG_ALPHA_GENERIC
 203 # define switch_mm                      alpha_mv.mv_switch_mm
 204 # define activate_mm(x,y)               alpha_mv.mv_activate_mm((x),(y),smp_processor_id())
 205 #else
 206 # ifdef CONFIG_ALPHA_EV4
 207 #  define switch_mm                     ev4_switch_mm
 208 #  define activate_mm(x,y)              ev4_activate_mm((x),(y),smp_processor_id())
 209 # else
 210 #  define switch_mm                     ev5_switch_mm
 211 #  define activate_mm(x,y)              ev5_activate_mm((x),(y),smp_processor_id())
 212 # endif
 213 #endif
 214
 215 extern inline void
 216 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 217 {
 218         mm->context = 0;
 219         tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
 220 }
 221
 222 extern inline void
 223 destroy_context(struct mm_struct *mm)
 224 {
 225         /* Nothing to do.  */
 226 }
 227
 228 #ifdef __MMU_EXTERN_INLINE
 229 #undef __EXTERN_INLINE
 230 #undef __MMU_EXTERN_INLINE
 231 #endif
 232
 233 #endif /* __ALPHA_MMU_CONTEXT_H */