include/asm-alpha/dma.h

   1 /*
   2  * include/asm-alpha/dma.h
   3  *
   4  * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
   5  * use ISA-compatible dma.  The only extension is support for high-page
   6  * registers that allow to set the top 8 bits of a 32-bit DMA address.
   7  * This register should be written last when setting up a DMA address
   8  * as this will also enable DMA across 64 KB boundaries.
   9  */
  10
  11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
  12  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  13  * Written by Hennus Bergman, 1992.
  14  * High DMA channel support & info by Hannu Savolainen
  15  * and John Boyd, Nov. 1992.
  16  */
  17
  18 #ifndef _ASM_DMA_H
  19 #define _ASM_DMA_H
  20
  21 #include <linux/config.h>
  22 #include <linux/spinlock.h>
  23 #include <asm/io.h>
  24
  25 #define dma_outb        outb
  26 #define dma_inb         inb
  27
  28 /*
  29  * NOTES about DMA transfers:
  30  *
  31  *  controller 1: channels 0-3, byte operations, ports 00-1F
  32  *  controller 2: channels 4-7, word operations, ports C0-DF
  33  *
  34  *  - ALL registers are 8 bits only, regardless of transfer size
  35  *  - channel 4 is not used - cascades 1 into 2.
  36  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  37  *  - channels 5-7 are word - addresses/counts are for physical words
  38  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  39  *  - transfer count loaded to registers is 1 less than actual count
  40  *  - controller 2 offsets are all even (2x offsets for controller 1)
  41  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  42  *  - page registers for 0-3 use bit 0, represent 64K pages
  43  *
  44  * DMA transfers are limited to the lower 16MB of _physical_ memory.
  45  * Note that addresses loaded into registers must be _physical_ addresses,
  46  * not logical addresses (which may differ if paging is active).
  47  *
  48  *  Address mapping for channels 0-3:
  49  *
  50  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  51  *    |  ...  |   |  ... |   |  ... |
  52  *    |  ...  |   |  ... |   |  ... |
  53  *    |  ...  |   |  ... |   |  ... |
  54  *   P7  ...  P0  A7 ... A0  A7 ... A0
  55  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  56  *
  57  *  Address mapping for channels 5-7:
  58  *
  59  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  60  *    |  ...  |   \   \   ... \  \  \  ... \  \
  61  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  62  *    |  ...  |     \   \   ... \  \  \  ... \
  63  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  64  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  65  *
  66  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  67  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  68  * the hardware level, so odd-byte transfers aren't possible).
  69  *
  70  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  71  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  72  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  73  *
  74  */
  75
  76 #define MAX_DMA_CHANNELS        8
  77
  78 /* The maximum address that we can perform a DMA transfer to on Alpha XL,
  79    due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 64MB.
  80    See <asm/apecs.h> for more info.
  81 */
  82 /* The maximum address that we can perform a DMA transfer to on RUFFIAN,
  83    due to a hardware SIO (PCI<->ISA bus bridge) chip limitation, is 16MB.
  84    See <asm/pyxis.h> for more info.
  85 */
  86 /* NOTE: we must define the maximum as something less than 64Mb, to prevent
  87    virt_to_bus() from returning an address in the first window, for a
  88    data area that goes beyond the 64Mb first DMA window. Sigh...
  89    We MUST coordinate the maximum with <asm/apecs.h> for consistency.
  90    For now, this limit is set to 48Mb...
  91 */
  92 #define ALPHA_XL_MAX_DMA_ADDRESS        (IDENT_ADDR+0x3000000UL)
  93 #define ALPHA_RUFFIAN_MAX_DMA_ADDRESS   (IDENT_ADDR+0x1000000UL)
  94 #define ALPHA_MAX_DMA_ADDRESS           (~0UL)
  95
  96 #ifdef CONFIG_ALPHA_GENERIC
  97 # define MAX_DMA_ADDRESS                (alpha_mv.max_dma_address)
  98 #else
  99 # ifdef CONFIG_ALPHA_XL
 100 #  define MAX_DMA_ADDRESS               ALPHA_XL_MAX_DMA_ADDRESS
 101 # elif defined(CONFIG_ALPHA_RUFFIAN)
 102 #  define MAX_DMA_ADDRESS               ALPHA_RUFFIAN_MAX_DMA_ADDRESS
 103 # else
 104 #  define MAX_DMA_ADDRESS               ALPHA_MAX_DMA_ADDRESS
 105 # endif
 106 #endif
 107
 108 /* 8237 DMA controllers */
 109 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 110 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 111
 112 /* DMA controller registers */
 113 #define DMA1_CMD_REG            0x08    /* command register (w) */
 114 #define DMA1_STAT_REG           0x08    /* status register (r) */
 115 #define DMA1_REQ_REG            0x09    /* request register (w) */
 116 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 117 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
 118 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 119 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 120 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 121 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 122 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 123 #define DMA1_EXT_MODE_REG       (0x400 | DMA1_MODE_REG)
 124
 125 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 126 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 127 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 128 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 129 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 130 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 131 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 132 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 133 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 134 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 135 #define DMA2_EXT_MODE_REG       (0x400 | DMA2_MODE_REG)
 136
 137 #define DMA_ADDR_0              0x00    /* DMA address registers */
 138 #define DMA_ADDR_1              0x02
 139 #define DMA_ADDR_2              0x04
 140 #define DMA_ADDR_3              0x06
 141 #define DMA_ADDR_4              0xC0
 142 #define DMA_ADDR_5              0xC4
 143 #define DMA_ADDR_6              0xC8
 144 #define DMA_ADDR_7              0xCC
 145
 146 #define DMA_CNT_0               0x01    /* DMA count registers */
 147 #define DMA_CNT_1               0x03
 148 #define DMA_CNT_2               0x05
 149 #define DMA_CNT_3               0x07
 150 #define DMA_CNT_4               0xC2
 151 #define DMA_CNT_5               0xC6
 152 #define DMA_CNT_6               0xCA
 153 #define DMA_CNT_7               0xCE
 154
 155 #define DMA_PAGE_0              0x87    /* DMA page registers */
 156 #define DMA_PAGE_1              0x83
 157 #define DMA_PAGE_2              0x81
 158 #define DMA_PAGE_3              0x82
 159 #define DMA_PAGE_5              0x8B
 160 #define DMA_PAGE_6              0x89
 161 #define DMA_PAGE_7              0x8A
 162
 163 #define DMA_HIPAGE_0            (0x400 | DMA_PAGE_0)
 164 #define DMA_HIPAGE_1            (0x400 | DMA_PAGE_1)
 165 #define DMA_HIPAGE_2            (0x400 | DMA_PAGE_2)
 166 #define DMA_HIPAGE_3            (0x400 | DMA_PAGE_3)
 167 #define DMA_HIPAGE_4            (0x400 | DMA_PAGE_4)
 168 #define DMA_HIPAGE_5            (0x400 | DMA_PAGE_5)
 169 #define DMA_HIPAGE_6            (0x400 | DMA_PAGE_6)
 170 #define DMA_HIPAGE_7            (0x400 | DMA_PAGE_7)
 171
 172 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 173 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 174 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 175
 176 #define DMA_AUTOINIT    0x10
 177
 178 extern spinlock_t  dma_spin_lock;
 179
 180 static __inline__ unsigned long claim_dma_lock(void)
 181 {
 182         unsigned long flags;
 183         spin_lock_irqsave(&dma_spin_lock, flags);
 184         return flags;
 185 }
 186
 187 static __inline__ void release_dma_lock(unsigned long flags)
 188 {
 189         spin_unlock_irqrestore(&dma_spin_lock, flags);
 190 }
 191
 192 /* enable/disable a specific DMA channel */
 193 static __inline__ void enable_dma(unsigned int dmanr)
 194 {
 195         if (dmanr<=3)
 196                 dma_outb(dmanr,  DMA1_MASK_REG);
 197         else
 198                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 199 }
 200
 201 static __inline__ void disable_dma(unsigned int dmanr)
 202 {
 203         if (dmanr<=3)
 204                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 205         else
 206                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 207 }
 208
 209 /* Clear the 'DMA Pointer Flip Flop'.
 210  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 211  * Use this once to initialize the FF to a known state.
 212  * After that, keep track of it. :-)
 213  * --- In order to do that, the DMA routines below should ---
 214  * --- only be used while interrupts are disabled! ---
 215  */
 216 static __inline__ void clear_dma_ff(unsigned int dmanr)
 217 {
 218         if (dmanr<=3)
 219                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 220         else
 221                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 222 }
 223
 224 /* set mode (above) for a specific DMA channel */
 225 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 226 {
 227         if (dmanr<=3)
 228                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 229         else
 230                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 231 }
 232
 233 /* set extended mode for a specific DMA channel */
 234 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
 235 {
 236         if (dmanr<=3)
 237                 dma_outb(ext_mode | dmanr,  DMA1_EXT_MODE_REG);
 238         else
 239                 dma_outb(ext_mode | (dmanr&3),  DMA2_EXT_MODE_REG);
 240 }
 241
 242 /* Set only the page register bits of the transfer address.
 243  * This is used for successive transfers when we know the contents of
 244  * the lower 16 bits of the DMA current address register.
 245  */
 246 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
 247 {
 248         switch(dmanr) {
 249                 case 0:
 250                         dma_outb(pagenr, DMA_PAGE_0);
 251                         dma_outb((pagenr >> 8), DMA_HIPAGE_0);
 252                         break;
 253                 case 1:
 254                         dma_outb(pagenr, DMA_PAGE_1);
 255                         dma_outb((pagenr >> 8), DMA_HIPAGE_1);
 256                         break;
 257                 case 2:
 258                         dma_outb(pagenr, DMA_PAGE_2);
 259                         dma_outb((pagenr >> 8), DMA_HIPAGE_2);
 260                         break;
 261                 case 3:
 262                         dma_outb(pagenr, DMA_PAGE_3);
 263                         dma_outb((pagenr >> 8), DMA_HIPAGE_3);
 264                         break;
 265                 case 5:
 266                         dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 267                         dma_outb((pagenr >> 8), DMA_HIPAGE_5);
 268                         break;
 269                 case 6:
 270                         dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 271                         dma_outb((pagenr >> 8), DMA_HIPAGE_6);
 272                         break;
 273                 case 7:
 274                         dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 275                         dma_outb((pagenr >> 8), DMA_HIPAGE_7);
 276                         break;
 277         }
 278 }
 279
 280
 281 /* Set transfer address & page bits for specific DMA channel.
 282  * Assumes dma flipflop is clear.
 283  */
 284 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 285 {
 286         if (dmanr <= 3)  {
 287             dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 288             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 289         }  else  {
 290             dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 291             dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 292         }
 293         set_dma_page(dmanr, a>>16);     /* set hipage last to enable 32-bit mode */
 294 }
 295
 296
 297 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 298  * a specific DMA channel.
 299  * You must ensure the parameters are valid.
 300  * NOTE: from a manual: "the number of transfers is one more
 301  * than the initial word count"! This is taken into account.
 302  * Assumes dma flip-flop is clear.
 303  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 304  */
 305 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 306 {
 307         count--;
 308         if (dmanr <= 3)  {
 309             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 310             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 311         } else {
 312             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 313             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 314         }
 315 }
 316
 317
 318 /* Get DMA residue count. After a DMA transfer, this
 319  * should return zero. Reading this while a DMA transfer is
 320  * still in progress will return unpredictable results.
 321  * If called before the channel has been used, it may return 1.
 322  * Otherwise, it returns the number of _bytes_ left to transfer.
 323  *
 324  * Assumes DMA flip-flop is clear.
 325  */
 326 static __inline__ int get_dma_residue(unsigned int dmanr)
 327 {
 328         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 329                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 330
 331         /* using short to get 16-bit wrap around */
 332         unsigned short count;
 333
 334         count = 1 + dma_inb(io_port);
 335         count += dma_inb(io_port) << 8;
 336
 337         return (dmanr<=3)? count : (count<<1);
 338 }
 339
 340
 341 /* These are in kernel/dma.c: */
 342 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 343 extern void free_dma(unsigned int dmanr);       /* release it again */
 344 #define KERNEL_HAVE_CHECK_DMA
 345 extern int check_dma(unsigned int dmanr);
 346
 347 /* From PCI */
 348
 349 #ifdef CONFIG_PCI
 350 extern int isa_dma_bridge_buggy;
 351 #else
 352 #define isa_dma_bridge_buggy    (0)
 353 #endif
 354
 355
 356 #endif /* _ASM_DMA_H */