include/asm-alpha/core_mcpcia.h

   1 #ifndef __ALPHA_MCPCIA__H__
   2 #define __ALPHA_MCPCIA__H__
   3
   4 /* Define to experiment with fitting everything into one 128MB HAE window.
   5    One window per bus, that is.  */
   6 #define MCPCIA_ONE_HAE_WINDOW 1
   7
   8 #include <linux/types.h>
   9 #include <linux/pci.h>
  10 #include <asm/compiler.h>
  11
  12 /*
  13  * MCPCIA is the internal name for a core logic chipset which provides
  14  * PCI access for the RAWHIDE family of systems.
  15  *
  16  * This file is based on:
  17  *
  18  * RAWHIDE System Programmer's Manual
  19  * 16-May-96
  20  * Rev. 1.4
  21  *
  22  */
  23
  24 /*------------------------------------------------------------------------**
  25 **                                                                        **
  26 **  I/O procedures                                                        **
  27 **                                                                        **
  28 **      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
  29 **      inportbxt: 8 bits only                                            **
  30 **      inport:    alias of inportw                                       **
  31 **      outport:   alias of outportw                                      **
  32 **                                                                        **
  33 **      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
  34 **      inmembxt: 8 bits only                                             **
  35 **      inmem:    alias of inmemw                                         **
  36 **      outmem:   alias of outmemw                                        **
  37 **                                                                        **
  38 **------------------------------------------------------------------------*/
  39
  40
  41 /* MCPCIA ADDRESS BIT DEFINITIONS
  42  *
  43  *  3333 3333 3322 2222 2222 1111 1111 11
  44  *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
  45  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
  46  *  1                                             000
  47  *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
  48  *  |                                             |\|
  49  *  |                               Byte Enable --+ |
  50  *  |                             Transfer Length --+
  51  *  +-- IO space, not cached
  52  *
  53  *   Byte      Transfer
  54  *   Enable    Length    Transfer  Byte    Address
  55  *   adr<6:5>  adr<4:3>  Length    Enable  Adder
  56  *   ---------------------------------------------
  57  *      00        00      Byte      1110   0x000
  58  *      01        00      Byte      1101   0x020
  59  *      10        00      Byte      1011   0x040
  60  *      11        00      Byte      0111   0x060
  61  *
  62  *      00        01      Word      1100   0x008
  63  *      01        01      Word      1001   0x028 <= Not supported in this code.
  64  *      10        01      Word      0011   0x048
  65  *
  66  *      00        10      Tribyte   1000   0x010
  67  *      01        10      Tribyte   0001   0x030
  68  *
  69  *      10        11      Longword  0000   0x058
  70  *
  71  *      Note that byte enables are asserted low.
  72  *
  73  */
  74
  75 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
  76
  77 #define MCPCIA_DMA_WIN_BASE             (2UL*1024*1024*1024)
  78 #define MCPCIA_DMA_WIN_SIZE             (2UL*1024*1024*1024)
  79
  80 #define MCPCIA_MID(m)           ((unsigned long)(m) << 33)
  81
  82 /*
  83  * Memory spaces:
  84  */
  85 #define MCPCIA_SPARSE(m)        (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
  86 #define MCPCIA_DENSE(m)         (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
  87 #define MCPCIA_IO(m)            (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
  88 #define MCPCIA_CONF(m)          (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
  89 #define MCPCIA_CSR(m)           (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
  90 #define MCPCIA_IO_IACK(m)       (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
  91 #define MCPCIA_DENSE_IO(m)      (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
  92 #define MCPCIA_DENSE_CONF(m)    (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
  93
  94 /*
  95  *  General Registers
  96  */
  97 #define MCPCIA_REV(m)           (MCPCIA_CSR(m) + 0x000)
  98 #define MCPCIA_WHOAMI(m)        (MCPCIA_CSR(m) + 0x040)
  99 #define MCPCIA_PCI_LAT(m)       (MCPCIA_CSR(m) + 0x080)
 100 #define MCPCIA_CAP_CTRL(m)      (MCPCIA_CSR(m) + 0x100)
 101 #define MCPCIA_HAE_MEM(m)       (MCPCIA_CSR(m) + 0x400)
 102 #define MCPCIA_HAE_IO(m)        (MCPCIA_CSR(m) + 0x440)
 103 #define _MCPCIA_IACK_SC(m)      (MCPCIA_CSR(m) + 0x480)
 104 #define MCPCIA_HAE_DENSE(m)     (MCPCIA_CSR(m) + 0x4C0)
 105
 106 /*
 107  * Interrupt Control registers
 108  */
 109 #define MCPCIA_INT_CTL(m)       (MCPCIA_CSR(m) + 0x500)
 110 #define MCPCIA_INT_REQ(m)       (MCPCIA_CSR(m) + 0x540)
 111 #define MCPCIA_INT_TARG(m)      (MCPCIA_CSR(m) + 0x580)
 112 #define MCPCIA_INT_ADR(m)       (MCPCIA_CSR(m) + 0x5C0)
 113 #define MCPCIA_INT_ADR_EXT(m)   (MCPCIA_CSR(m) + 0x600)
 114 #define MCPCIA_INT_MASK0(m)     (MCPCIA_CSR(m) + 0x640)
 115 #define MCPCIA_INT_MASK1(m)     (MCPCIA_CSR(m) + 0x680)
 116 #define MCPCIA_INT_ACK0(m)      (MCPCIA_CSR(m) + 0x10003f00)
 117 #define MCPCIA_INT_ACK1(m)      (MCPCIA_CSR(m) + 0x10003f40)
 118
 119 /*
 120  * Performance Monitor registers
 121  */
 122 #define MCPCIA_PERF_MON(m)      (MCPCIA_CSR(m) + 0x300)
 123 #define MCPCIA_PERF_CONT(m)     (MCPCIA_CSR(m) + 0x340)
 124
 125 /*
 126  * Diagnostic Registers
 127  */
 128 #define MCPCIA_CAP_DIAG(m)      (MCPCIA_CSR(m) + 0x700)
 129 #define MCPCIA_TOP_OF_MEM(m)    (MCPCIA_CSR(m) + 0x7C0)
 130
 131 /*
 132  * Error registers
 133  */
 134 #define MCPCIA_MC_ERR0(m)       (MCPCIA_CSR(m) + 0x800)
 135 #define MCPCIA_MC_ERR1(m)       (MCPCIA_CSR(m) + 0x840)
 136 #define MCPCIA_CAP_ERR(m)       (MCPCIA_CSR(m) + 0x880)
 137 #define MCPCIA_PCI_ERR1(m)      (MCPCIA_CSR(m) + 0x1040)
 138 #define MCPCIA_MDPA_STAT(m)     (MCPCIA_CSR(m) + 0x4000)
 139 #define MCPCIA_MDPA_SYN(m)      (MCPCIA_CSR(m) + 0x4040)
 140 #define MCPCIA_MDPA_DIAG(m)     (MCPCIA_CSR(m) + 0x4080)
 141 #define MCPCIA_MDPB_STAT(m)     (MCPCIA_CSR(m) + 0x8000)
 142 #define MCPCIA_MDPB_SYN(m)      (MCPCIA_CSR(m) + 0x8040)
 143 #define MCPCIA_MDPB_DIAG(m)     (MCPCIA_CSR(m) + 0x8080)
 144
 145 /*
 146  * PCI Address Translation Registers.
 147  */
 148 #define MCPCIA_SG_TBIA(m)       (MCPCIA_CSR(m) + 0x1300)
 149 #define MCPCIA_HBASE(m)         (MCPCIA_CSR(m) + 0x1340)
 150
 151 #define MCPCIA_W0_BASE(m)       (MCPCIA_CSR(m) + 0x1400)
 152 #define MCPCIA_W0_MASK(m)       (MCPCIA_CSR(m) + 0x1440)
 153 #define MCPCIA_T0_BASE(m)       (MCPCIA_CSR(m) + 0x1480)
 154
 155 #define MCPCIA_W1_BASE(m)       (MCPCIA_CSR(m) + 0x1500)
 156 #define MCPCIA_W1_MASK(m)       (MCPCIA_CSR(m) + 0x1540)
 157 #define MCPCIA_T1_BASE(m)       (MCPCIA_CSR(m) + 0x1580)
 158
 159 #define MCPCIA_W2_BASE(m)       (MCPCIA_CSR(m) + 0x1600)
 160 #define MCPCIA_W2_MASK(m)       (MCPCIA_CSR(m) + 0x1640)
 161 #define MCPCIA_T2_BASE(m)       (MCPCIA_CSR(m) + 0x1680)
 162
 163 #define MCPCIA_W3_BASE(m)       (MCPCIA_CSR(m) + 0x1700)
 164 #define MCPCIA_W3_MASK(m)       (MCPCIA_CSR(m) + 0x1740)
 165 #define MCPCIA_T3_BASE(m)       (MCPCIA_CSR(m) + 0x1780)
 166
 167 /* Hack!  Only words for bus 0.  */
 168
 169 #if !MCPCIA_ONE_HAE_WINDOW
 170 #define MCPCIA_HAE_ADDRESS      MCPCIA_HAE_MEM(4)
 171 #endif
 172 #define MCPCIA_IACK_SC          _MCPCIA_IACK_SC(4)
 173
 174 /*
 175  * The canonical non-remaped I/O and MEM addresses have these values
 176  * subtracted out.  This is arranged so that folks manipulating ISA
 177  * devices can use their familiar numbers and have them map to bus 0.
 178  */
 179
 180 #define MCPCIA_IO_BIAS          MCPCIA_IO(4)
 181 #define MCPCIA_MEM_BIAS         MCPCIA_DENSE(4)
 182
 183
 184 /*
 185  * Data structure for handling MCPCIA machine checks:
 186  */
 187 struct el_MCPCIA_uncorrected_frame_mcheck {
 188         struct el_common header;
 189         struct el_common_EV5_uncorrectable_mcheck procdata;
 190 };
 191
 192
 193 #ifdef __KERNEL__
 194
 195 #ifndef __EXTERN_INLINE
 196 #define __EXTERN_INLINE extern inline
 197 #define __IO_EXTERN_INLINE
 198 #endif
 199
 200 /*
 201  * Translate physical memory address as seen on (PCI) bus into
 202  * a kernel virtual address and vv.
 203  */
 204
 205 __EXTERN_INLINE unsigned long mcpcia_virt_to_bus(void * address)
 206 {
 207         return virt_to_phys(address) + MCPCIA_DMA_WIN_BASE;
 208 }
 209
 210 __EXTERN_INLINE void * mcpcia_bus_to_virt(unsigned long address)
 211 {
 212         return phys_to_virt(address - MCPCIA_DMA_WIN_BASE);
 213 }
 214
 215 /*
 216  * I/O functions:
 217  *
 218  * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
 219  * and EV56 (21164a) processors, can use either a sparse address mapping
 220  * scheme, or the so-called byte-word PCI address space, to get at PCI memory
 221  * and I/O.
 222  *
 223  * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
 224  */
 225
 226 #define vucp    volatile unsigned char *
 227 #define vusp    volatile unsigned short *
 228 #define vip     volatile int *
 229 #define vuip    volatile unsigned int *
 230 #define vulp    volatile unsigned long *
 231
 232 __EXTERN_INLINE unsigned int mcpcia_inb(unsigned long in_addr)
 233 {
 234         unsigned long addr, hose, result;
 235
 236         addr = in_addr & 0xffffUL;
 237         hose = in_addr & ~0xffffUL;
 238
 239         /* ??? I wish I could get rid of this.  But there's no ioremap
 240            equivalent for I/O space.  PCI I/O can be forced into the
 241            correct hose's I/O region, but that doesn't take care of
 242            legacy ISA crap.  */
 243         hose += MCPCIA_IO_BIAS;
 244
 245         result = *(vip) ((addr << 5) + hose + 0x00);
 246         return __kernel_extbl(result, addr & 3);
 247 }
 248
 249 __EXTERN_INLINE void mcpcia_outb(unsigned char b, unsigned long in_addr)
 250 {
 251         unsigned long addr, hose, w;
 252
 253         addr = in_addr & 0xffffUL;
 254         hose = in_addr & ~0xffffUL;
 255         hose += MCPCIA_IO_BIAS;
 256
 257         w = __kernel_insbl(b, addr & 3);
 258         *(vuip) ((addr << 5) + hose + 0x00) = w;
 259         mb();
 260 }
 261
 262 __EXTERN_INLINE unsigned int mcpcia_inw(unsigned long in_addr)
 263 {
 264         unsigned long addr, hose, result;
 265
 266         addr = in_addr & 0xffffUL;
 267         hose = in_addr & ~0xffffUL;
 268         hose += MCPCIA_IO_BIAS;
 269
 270         result = *(vip) ((addr << 5) + hose + 0x08);
 271         return __kernel_extwl(result, addr & 3);
 272 }
 273
 274 __EXTERN_INLINE void mcpcia_outw(unsigned short b, unsigned long in_addr)
 275 {
 276         unsigned long addr, hose, w;
 277
 278         addr = in_addr & 0xffffUL;
 279         hose = in_addr & ~0xffffUL;
 280         hose += MCPCIA_IO_BIAS;
 281
 282         w = __kernel_inswl(b, addr & 3);
 283         *(vuip) ((addr << 5) + hose + 0x08) = w;
 284         mb();
 285 }
 286
 287 __EXTERN_INLINE unsigned int mcpcia_inl(unsigned long in_addr)
 288 {
 289         unsigned long addr, hose;
 290
 291         addr = in_addr & 0xffffUL;
 292         hose = in_addr & ~0xffffUL;
 293         hose += MCPCIA_IO_BIAS;
 294
 295         return *(vuip) ((addr << 5) + hose + 0x18);
 296 }
 297
 298 __EXTERN_INLINE void mcpcia_outl(unsigned int b, unsigned long in_addr)
 299 {
 300         unsigned long addr, hose;
 301
 302         addr = in_addr & 0xffffUL;
 303         hose = in_addr & ~0xffffUL;
 304         hose += MCPCIA_IO_BIAS;
 305
 306         *(vuip) ((addr << 5) + hose + 0x18) = b;
 307         mb();
 308 }
 309
 310
 311 /*
 312  * Memory functions.  64-bit and 32-bit accesses are done through
 313  * dense memory space, everything else through sparse space.
 314  *
 315  * For reading and writing 8 and 16 bit quantities we need to
 316  * go through one of the three sparse address mapping regions
 317  * and use the HAE_MEM CSR to provide some bits of the address.
 318  * The following few routines use only sparse address region 1
 319  * which gives 1Gbyte of accessible space which relates exactly
 320  * to the amount of PCI memory mapping *into* system address space.
 321  * See p 6-17 of the specification but it looks something like this:
 322  *
 323  * 21164 Address:
 324  *
 325  *          3         2         1
 326  * 9876543210987654321098765432109876543210
 327  * 1ZZZZ0.PCI.QW.Address............BBLL
 328  *
 329  * ZZ = SBZ
 330  * BB = Byte offset
 331  * LL = Transfer length
 332  *
 333  * PCI Address:
 334  *
 335  * 3         2         1
 336  * 10987654321098765432109876543210
 337  * HHH....PCI.QW.Address........ 00
 338  *
 339  * HHH = 31:29 HAE_MEM CSR
 340  *
 341  */
 342
 343 __EXTERN_INLINE unsigned long mcpcia_ioremap(unsigned long addr)
 344 {
 345         return addr + MCPCIA_MEM_BIAS;
 346 }
 347
 348 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
 349 {
 350         return addr >= MCPCIA_SPARSE(0);
 351 }
 352
 353 __EXTERN_INLINE unsigned long mcpcia_readb(unsigned long in_addr)
 354 {
 355         unsigned long addr = in_addr & 0xffffffffUL;
 356         unsigned long hose = in_addr & ~0xffffffffUL;
 357         unsigned long result, work;
 358
 359 #if !MCPCIA_ONE_HAE_WINDOW
 360         unsigned long msb;
 361         msb = addr & ~MCPCIA_MEM_MASK;
 362         set_hae(msb);
 363 #endif
 364         addr = addr & MCPCIA_MEM_MASK;
 365
 366         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
 367         work = ((addr << 5) + hose + 0x00);
 368         result = *(vip) work;
 369         return __kernel_extbl(result, addr & 3);
 370 }
 371
 372 __EXTERN_INLINE unsigned long mcpcia_readw(unsigned long in_addr)
 373 {
 374         unsigned long addr = in_addr & 0xffffffffUL;
 375         unsigned long hose = in_addr & ~0xffffffffUL;
 376         unsigned long result, work;
 377
 378 #if !MCPCIA_ONE_HAE_WINDOW
 379         unsigned long msb;
 380         msb = addr & ~MCPCIA_MEM_MASK;
 381         set_hae(msb);
 382 #endif
 383         addr = addr & MCPCIA_MEM_MASK;
 384
 385         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
 386         work = ((addr << 5) + hose + 0x08);
 387         result = *(vip) work;
 388         return __kernel_extwl(result, addr & 3);
 389 }
 390
 391 __EXTERN_INLINE void mcpcia_writeb(unsigned char b, unsigned long in_addr)
 392 {
 393         unsigned long addr = in_addr & 0xffffffffUL;
 394         unsigned long hose = in_addr & ~0xffffffffUL;
 395         unsigned long w;
 396
 397 #if !MCPCIA_ONE_HAE_WINDOW
 398         unsigned long msb;
 399         msb = addr & ~MCPCIA_MEM_MASK;
 400         set_hae(msb);
 401 #endif
 402         addr = addr & MCPCIA_MEM_MASK;
 403
 404         w = __kernel_insbl(b, in_addr & 3);
 405         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
 406         *(vuip) ((addr << 5) + hose + 0x00) = w;
 407 }
 408
 409 __EXTERN_INLINE void mcpcia_writew(unsigned short b, unsigned long in_addr)
 410 {
 411         unsigned long addr = in_addr & 0xffffffffUL;
 412         unsigned long hose = in_addr & ~0xffffffffUL;
 413         unsigned long w;
 414
 415 #if !MCPCIA_ONE_HAE_WINDOW
 416         unsigned long msb;
 417         msb = addr & ~MCPCIA_MEM_MASK;
 418         set_hae(msb);
 419 #endif
 420         addr = addr & MCPCIA_MEM_MASK;
 421
 422         w = __kernel_inswl(b, in_addr & 3);
 423         hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);
 424         *(vuip) ((addr << 5) + hose + 0x08) = w;
 425 }
 426
 427 __EXTERN_INLINE unsigned long mcpcia_readl(unsigned long addr)
 428 {
 429         return *(vuip)addr;
 430 }
 431
 432 __EXTERN_INLINE unsigned long mcpcia_readq(unsigned long addr)
 433 {
 434         return *(vulp)addr;
 435 }
 436
 437 __EXTERN_INLINE void mcpcia_writel(unsigned int b, unsigned long addr)
 438 {
 439         *(vuip)addr = b;
 440 }
 441
 442 __EXTERN_INLINE void mcpcia_writeq(unsigned long b, unsigned long addr)
 443 {
 444         *(vulp)addr = b;
 445 }
 446
 447 #undef vucp
 448 #undef vusp
 449 #undef vip
 450 #undef vuip
 451 #undef vulp
 452
 453 #ifdef __WANT_IO_DEF
 454
 455 #define virt_to_bus     mcpcia_virt_to_bus
 456 #define bus_to_virt     mcpcia_bus_to_virt
 457
 458 #define __inb           mcpcia_inb
 459 #define __inw           mcpcia_inw
 460 #define __inl           mcpcia_inl
 461 #define __outb          mcpcia_outb
 462 #define __outw          mcpcia_outw
 463 #define __outl          mcpcia_outl
 464 #define __readb         mcpcia_readb
 465 #define __readw         mcpcia_readw
 466 #define __writeb        mcpcia_writeb
 467 #define __writew        mcpcia_writew
 468 #define __readl         mcpcia_readl
 469 #define __readq         mcpcia_readq
 470 #define __writel        mcpcia_writel
 471 #define __writeq        mcpcia_writeq
 472 #define __ioremap       mcpcia_ioremap
 473 #define __is_ioaddr     mcpcia_is_ioaddr
 474
 475 # define inb(port) \
 476   (__builtin_constant_p((port))?__inb(port):_inb(port))
 477 # define outb(x, port) \
 478   (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
 479
 480 #define __raw_readl(a)          __readl((unsigned long)(a))
 481 #define __raw_readq(a)          __readq((unsigned long)(a))
 482 #define __raw_writel(v,a)       __writel((v),(unsigned long)(a))
 483 #define __raw_writeq(v,a)       __writeq((v),(unsigned long)(a))
 484
 485 #endif /* __WANT_IO_DEF */
 486
 487 #ifdef __IO_EXTERN_INLINE
 488 #undef __EXTERN_INLINE
 489 #undef __IO_EXTERN_INLINE
 490 #endif
 491
 492 #endif /* __KERNEL__ */
 493
 494 #endif /* __ALPHA_MCPCIA__H__ */