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Import 2.3.18pre1
[davej-history.git] / include / asm-alpha / core_cia.h
blobb549029d16985c64a3e37e1c0c34f18c501ada5f
1 #ifndef __ALPHA_CIA__H__
2 #define __ALPHA_CIA__H__
3
4 /* Define to experiment with fitting everything into one 512MB HAE window. */
5 #define CIA_ONE_HAE_WINDOW 1
6
7 #include <linux/types.h>
8 #include <asm/compiler.h>
9
10 /*
11 * CIA is the internal name for the 2117x chipset which provides
12 * memory controller and PCI access for the 21164 chip based systems.
13 *
14 * This file is based on:
15 *
16 * DECchip 21171 Core Logic Chipset
17 * Technical Reference Manual
18 *
19 * EC-QE18B-TE
20 *
21 * david.rusling@reo.mts.dec.com Initial Version.
22 *
23 */
24
25 /*------------------------------------------------------------------------**
26 ** **
27 ** EB164 I/O procedures **
28 ** **
29 ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
30 ** inportbxt: 8 bits only **
31 ** inport: alias of inportw **
32 ** outport: alias of outportw **
33 ** **
34 ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
35 ** inmembxt: 8 bits only **
36 ** inmem: alias of inmemw **
37 ** outmem: alias of outmemw **
38 ** **
39 **------------------------------------------------------------------------*/
40
41
42 /* CIA ADDRESS BIT DEFINITIONS
43 *
44 * 3333 3333 3322 2222 2222 1111 1111 11
45 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
46 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
47 * 1 000
48 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
49 * | |\|
50 * | Byte Enable --+ |
51 * | Transfer Length --+
52 * +-- IO space, not cached
53 *
54 * Byte Transfer
55 * Enable Length Transfer Byte Address
56 * adr<6:5> adr<4:3> Length Enable Adder
57 * ---------------------------------------------
58 * 00 00 Byte 1110 0x000
59 * 01 00 Byte 1101 0x020
60 * 10 00 Byte 1011 0x040
61 * 11 00 Byte 0111 0x060
62 *
63 * 00 01 Word 1100 0x008
64 * 01 01 Word 1001 0x028 <= Not supported in this code.
65 * 10 01 Word 0011 0x048
66 *
67 * 00 10 Tribyte 1000 0x010
68 * 01 10 Tribyte 0001 0x030
69 *
70 * 10 11 Longword 0000 0x058
71 *
72 * Note that byte enables are asserted low.
73 *
74 */
75
76 #define CIA_MEM_R1_MASK 0x1fffffff /* SPARSE Mem region 1 mask is 29 bits */
77 #define CIA_MEM_R2_MASK 0x07ffffff /* SPARSE Mem region 2 mask is 27 bits */
78 #define CIA_MEM_R3_MASK 0x03ffffff /* SPARSE Mem region 3 mask is 26 bits */
79
80 #define CIA_DMA_WIN_BASE (1UL*1024*1024*1024)
81 #define CIA_DMA_WIN_SIZE (2UL*1024*1024*1024)
82
83 /* Window 0 at 1GB size 1GB mapping to 0. */
84 #define CIA_DMA_WIN0_BASE_DEFAULT (1UL*1024*1024*1024)
85 #define CIA_DMA_WIN0_SIZE_DEFAULT (1UL*1024*1024*1024)
86 #define CIA_DMA_WIN0_TRAN_DEFAULT (0UL)
87
88 /* Window 1 at 2GB size 1GB mapping to 1GB. */
89 #define CIA_DMA_WIN1_BASE_DEFAULT (2UL*1024*1024*1024)
90 #define CIA_DMA_WIN1_SIZE_DEFAULT (1UL*1024*1024*1024)
91 #define CIA_DMA_WIN1_TRAN_DEFAULT (1UL*1024*1024*1024)
92
93
94 /*
95 * 21171-CA Control and Status Registers (p4-1)
96 */
97 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
98 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
99 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
100 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
101 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
102 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
103 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
104 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
105
106 /*
107 * 21171-CA Diagnostic Registers (p4-2)
108 */
109 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
110 #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
111
112 /*
113 * 21171-CA Performance Monitor registers (p4-3)
114 */
115 #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
116 #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
117
118 /*
119 * 21171-CA Error registers (p4-3)
120 */
121 #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
122 #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
123 #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
124 #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
125 #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
126 #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
127 #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
128 #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
129 #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
130 #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
131 #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
132
133 /*
134 * 2117A-CA PCI Address Translation Registers.
135 */
136 #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
137
138 #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
139 #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
140 #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
141
142 #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
143 #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
144 #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
145
146 #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
147 #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
148 #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
149
150 #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
151 #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
152 #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
153
154 /*
155 * 21171-CA System configuration registers (p4-3)
156 */
157 #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
158 #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
159 #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
160 #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
161 #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
162 #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
163 #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
164 #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
165 #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
166 #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
167 #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
168 #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
169
170 /*
171 * Memory spaces:
172 */
173 #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
174 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
175 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
176 #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
177 #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
178 #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
179 #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
180
181 /*
182 * ALCOR's GRU ASIC registers
183 */
184 #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
185 #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
186 #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
187 #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
188 #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
189
190 #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
191 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
192 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
193 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
194
195 #define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
196 #define XLT_GRU_INT_REQ_BITS 0x80003fffUL
197 #define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
198
199
200 /*
201 * Bit definitions for I/O Controller status register 0:
202 */
203 #define CIA_IOC_STAT0_CMD 0xf
204 #define CIA_IOC_STAT0_ERR (1<<4)
205 #define CIA_IOC_STAT0_LOST (1<<5)
206 #define CIA_IOC_STAT0_THIT (1<<6)
207 #define CIA_IOC_STAT0_TREF (1<<7)
208 #define CIA_IOC_STAT0_CODE_SHIFT 8
209 #define CIA_IOC_STAT0_CODE_MASK 0x7
210 #define CIA_IOC_STAT0_P_NBR_SHIFT 13
211 #define CIA_IOC_STAT0_P_NBR_MASK 0x7ffff
212
213 #if !CIA_ONE_HAE_WINDOW
214 #define CIA_HAE_ADDRESS CIA_IOC_HAE_MEM
215 #endif
216
217 /*
218 * Data structure for handling CIA machine checks.
219 */
220
221 /* EV5-specific info. */
222 struct el_CIA_procdata {
223 unsigned long shadow[8]; /* PALmode shadow registers */
224 unsigned long paltemp[24]; /* PAL temporary registers */
225 /* EV5-specific fields */
226 unsigned long exc_addr; /* Address of excepting instruction. */
227 unsigned long exc_sum; /* Summary of arithmetic traps. */
228 unsigned long exc_mask; /* Exception mask (from exc_sum). */
229 unsigned long exc_base; /* PALbase at time of exception. */
230 unsigned long isr; /* Interrupt summary register. */
231 unsigned long icsr; /* Ibox control register. */
232 unsigned long ic_perr_stat;
233 unsigned long dc_perr_stat;
234 unsigned long va; /* Effective VA of fault or miss. */
235 unsigned long mm_stat;
236 unsigned long sc_addr;
237 unsigned long sc_stat;
238 unsigned long bc_tag_addr;
239 unsigned long ei_addr;
240 unsigned long fill_syn;
241 unsigned long ei_stat;
242 unsigned long ld_lock;
243 };
244
245 /* System-specific info. */
246 struct el_CIA_sysdata_mcheck {
247 unsigned long coma_gcr;
248 unsigned long coma_edsr;
249 unsigned long coma_ter;
250 unsigned long coma_elar;
251 unsigned long coma_ehar;
252 unsigned long coma_ldlr;
253 unsigned long coma_ldhr;
254 unsigned long coma_base0;
255 unsigned long coma_base1;
256 unsigned long coma_base2;
257 unsigned long coma_cnfg0;
258 unsigned long coma_cnfg1;
259 unsigned long coma_cnfg2;
260 unsigned long epic_dcsr;
261 unsigned long epic_pear;
262 unsigned long epic_sear;
263 unsigned long epic_tbr1;
264 unsigned long epic_tbr2;
265 unsigned long epic_pbr1;
266 unsigned long epic_pbr2;
267 unsigned long epic_pmr1;
268 unsigned long epic_pmr2;
269 unsigned long epic_harx1;
270 unsigned long epic_harx2;
271 unsigned long epic_pmlt;
272 unsigned long epic_tag0;
273 unsigned long epic_tag1;
274 unsigned long epic_tag2;
275 unsigned long epic_tag3;
276 unsigned long epic_tag4;
277 unsigned long epic_tag5;
278 unsigned long epic_tag6;
279 unsigned long epic_tag7;
280 unsigned long epic_data0;
281 unsigned long epic_data1;
282 unsigned long epic_data2;
283 unsigned long epic_data3;
284 unsigned long epic_data4;
285 unsigned long epic_data5;
286 unsigned long epic_data6;
287 unsigned long epic_data7;
288 };
289
290
291 #ifdef __KERNEL__
292
293 #ifndef __EXTERN_INLINE
294 #define __EXTERN_INLINE extern inline
295 #define __IO_EXTERN_INLINE
296 #endif
297
298 /*
299 * Translate physical memory address as seen on (PCI) bus into
300 * a kernel virtual address and vv.
301 */
302
303 __EXTERN_INLINE unsigned long cia_virt_to_bus(void * address)
304 {
305 return virt_to_phys(address) + CIA_DMA_WIN_BASE;
306 }
307
308 __EXTERN_INLINE void * cia_bus_to_virt(unsigned long address)
309 {
310 return phys_to_virt(address - CIA_DMA_WIN_BASE);
311 }
312
313 /*
314 * I/O functions:
315 *
316 * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
317 * series of processors uses a sparse address mapping scheme to
318 * get at PCI memory and I/O.
319 */
320
321 #define vip volatile int *
322 #define vuip volatile unsigned int *
323 #define vulp volatile unsigned long *
324
325 __EXTERN_INLINE unsigned int cia_inb(unsigned long addr)
326 {
327 long result;
328 result = *(vip) ((addr << 5) + CIA_IO + 0x00);
329 return __kernel_extbl(result, addr & 3);
330 }
331
332 __EXTERN_INLINE void cia_outb(unsigned char b, unsigned long addr)
333 {
334 unsigned long w = __kernel_insbl(b, addr & 3);
335 *(vuip) ((addr << 5) + CIA_IO + 0x00) = w;
336 mb();
337 }
338
339 __EXTERN_INLINE unsigned int cia_inw(unsigned long addr)
340 {
341 long result;
342 result = *(vip) ((addr << 5) + CIA_IO + 0x08);
343 return __kernel_extwl(result, addr & 3);
344 }
345
346 __EXTERN_INLINE void cia_outw(unsigned short b, unsigned long addr)
347 {
348 unsigned long w = __kernel_inswl(b, addr & 3);
349 *(vuip) ((addr << 5) + CIA_IO + 0x08) = w;
350 mb();
351 }
352
353 __EXTERN_INLINE unsigned int cia_inl(unsigned long addr)
354 {
355 return *(vuip) ((addr << 5) + CIA_IO + 0x18);
356 }
357
358 __EXTERN_INLINE void cia_outl(unsigned int b, unsigned long addr)
359 {
360 *(vuip) ((addr << 5) + CIA_IO + 0x18) = b;
361 mb();
362 }
363
364
365 /*
366 * Memory functions. 64-bit and 32-bit accesses are done through
367 * dense memory space, everything else through sparse space.
368 *
369 * For reading and writing 8 and 16 bit quantities we need to
370 * go through one of the three sparse address mapping regions
371 * and use the HAE_MEM CSR to provide some bits of the address.
372 * The following few routines use only sparse address region 1
373 * which gives 1Gbyte of accessible space which relates exactly
374 * to the amount of PCI memory mapping *into* system address space.
375 * See p 6-17 of the specification but it looks something like this:
376 *
377 * 21164 Address:
378 *
379 * 3 2 1
380 * 9876543210987654321098765432109876543210
381 * 1ZZZZ0.PCI.QW.Address............BBLL
382 *
383 * ZZ = SBZ
384 * BB = Byte offset
385 * LL = Transfer length
386 *
387 * PCI Address:
388 *
389 * 3 2 1
390 * 10987654321098765432109876543210
391 * HHH....PCI.QW.Address........ 00
392 *
393 * HHH = 31:29 HAE_MEM CSR
394 *
395 */
396
397 __EXTERN_INLINE unsigned long cia_readb(unsigned long addr)
398 {
399 unsigned long result;
400
401 #if !CIA_ONE_HAE_WINDOW
402 unsigned long msb;
403 /* Note that CIA_DENSE_MEM has no bits not masked in these
404 operations, so we don't have to subtract it back out. */
405 msb = addr & 0xE0000000;
406 set_hae(msb);
407 #endif
408 addr &= CIA_MEM_R1_MASK;
409
410 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x00);
411 return __kernel_extbl(result, addr & 3);
412 }
413
414 __EXTERN_INLINE unsigned long cia_readw(unsigned long addr)
415 {
416 unsigned long result;
417
418 #if !CIA_ONE_HAE_WINDOW
419 unsigned long msb;
420 /* Note that CIA_DENSE_MEM has no bits not masked in these
421 operations, so we don't have to subtract it back out. */
422 msb = addr & 0xE0000000;
423 set_hae(msb);
424 #endif
425 addr &= CIA_MEM_R1_MASK;
426
427 result = *(vip) ((addr << 5) + CIA_SPARSE_MEM + 0x08);
428 return __kernel_extwl(result, addr & 3);
429 }
430
431 __EXTERN_INLINE void cia_writeb(unsigned char b, unsigned long addr)
432 {
433 unsigned long w;
434
435 #if !CIA_ONE_HAE_WINDOW
436 unsigned long msb;
437 /* Note that CIA_DENSE_MEM has no bits not masked in these
438 operations, so we don't have to subtract it back out. */
439 msb = addr & 0xE0000000;
440 set_hae(msb);
441 #endif
442 addr &= CIA_MEM_R1_MASK;
443
444 w = __kernel_insbl(b, addr & 3);
445 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x00) = w;
446 }
447
448 __EXTERN_INLINE void cia_writew(unsigned short b, unsigned long addr)
449 {
450 unsigned long w;
451
452 #if !CIA_ONE_HAE_WINDOW
453 unsigned long msb;
454 /* Note that CIA_DENSE_MEM has no bits not masked in these
455 operations, so we don't have to subtract it back out. */
456 msb = addr & 0xE0000000;
457 set_hae(msb);
458 #endif
459 addr &= CIA_MEM_R1_MASK;
460
461 w = __kernel_inswl(b, addr & 3);
462 *(vuip) ((addr << 5) + CIA_SPARSE_MEM + 0x08) = w;
463 }
464
465 __EXTERN_INLINE unsigned long cia_readl(unsigned long addr)
466 {
467 return *(vuip)addr;
468 }
469
470 __EXTERN_INLINE unsigned long cia_readq(unsigned long addr)
471 {
472 return *(vulp)addr;
473 }
474
475 __EXTERN_INLINE void cia_writel(unsigned int b, unsigned long addr)
476 {
477 *(vuip)addr = b;
478 }
479
480 __EXTERN_INLINE void cia_writeq(unsigned long b, unsigned long addr)
481 {
482 *(vulp)addr = b;
483 }
484
485 __EXTERN_INLINE unsigned long cia_ioremap(unsigned long addr)
486 {
487 return addr + CIA_DENSE_MEM;
488 }
489
490 __EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
491 {
492 return addr >= IDENT_ADDR + 0x8000000000UL;
493 }
494
495 #undef vip
496 #undef vuip
497 #undef vulp
498
499 #ifdef __WANT_IO_DEF
500
501 #define virt_to_bus cia_virt_to_bus
502 #define bus_to_virt cia_bus_to_virt
503 #define __inb cia_inb
504 #define __inw cia_inw
505 #define __inl cia_inl
506 #define __outb cia_outb
507 #define __outw cia_outw
508 #define __outl cia_outl
509
510 #define __readb cia_readb
511 #define __readw cia_readw
512 #define __writeb cia_writeb
513 #define __writew cia_writew
514 #define __readl cia_readl
515 #define __readq cia_readq
516 #define __writel cia_writel
517 #define __writeq cia_writeq
518 #define __ioremap cia_ioremap
519 #define __is_ioaddr cia_is_ioaddr
520
521 #define inb(port) \
522 (__builtin_constant_p((port))?__inb(port):_inb(port))
523 #define outb(x, port) \
524 (__builtin_constant_p((port))?__outb((x),(port)):_outb((x),(port)))
525
526 #define __raw_readl(a) __readl((unsigned long)(a))
527 #define __raw_readq(a) __readq((unsigned long)(a))
528 #define __raw_writel(v,a) __writel((v),(unsigned long)(a))
529 #define __raw_writeq(v,a) __writeq((v),(unsigned long)(a))
530
531 #endif /* __WANT_IO_DEF */
532
533 #ifdef __IO_EXTERN_INLINE
534 #undef __EXTERN_INLINE
535 #undef __IO_EXTERN_INLINE
536 #endif
537
538 #endif /* __KERNEL__ */
539
540 #endif /* __ALPHA_CIA__H__ */
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