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Import 2.3.18pre1
[davej-history.git] / drivers / sound / maestro.c
blob3f9250bcbe9a3784a8466b56a7bc9cfe4c52c21c
1 /*****************************************************************************
2 *
3 * ESS Maestro/Maestro-2/Maestro-2E driver for Linux 2.2.x
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * (c) Copyright 1999 Alan Cox <alan.cox@linux.org>
20 *
21 * Based heavily on SonicVibes.c:
22 * Copyright (C) 1998-1999 Thomas Sailer (sailer@ife.ee.ethz.ch)
23 *
24 * Heavily modified by Zach Brown <zab@redhat.com> based on lunch
25 * with ESS engineers. Many thanks to Howard Kim for providing
26 * contacts and hardware. Honorable mention goes to Eric
27 * Brombaugh for the BOB routines and nice hacking in general.
28 *
29 * Supported devices:
30 * /dev/dsp0-7 standard /dev/dsp device, (mostly) OSS compatible
31 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
32 *
33 * Hardware Description
34 *
35 * A working Maestro setup contains the Maestro chip wired to a
36 * codec or 2. In the Maestro we have the APUs, the ASP, and the
37 * Wavecache. The APUs can be though of as virtual audio routing
38 * channels. They can take data from a number of sources and perform
39 * basic encodings of the data. The wavecache is a storehouse for
40 * PCM data. Typically it deals with PCI and interracts with the
41 * APUs. The ASP is a wacky DSP like device that ESS is loathe
42 * to release docs on. Thankfully it isn't required on the Maestro
43 * until you start doing insane things like FM emulation and surround
44 * encoding. The codecs are almost always AC-97 compliant codecs,
45 * but it appears that early Maestros may have had PT101 (an ESS
46 * part?) wired to them. The only real difference in the Maestro
47 * families is external goop like docking capability, memory for
48 * the ASP, and trivial initialization differences.
49 *
50 * Driver Operation
51 *
52 * We only drive the APU/Wavecache as typical DACs and drive the
53 * mixers in the codecs. There are 64 APUs. We assign 4 to each
54 * /dev/dsp? device. 2 channels for both in and out.
55 *
56 * For output we maintain a ring buffer of data that we are dmaing
57 * to the card. In mono operation this is nice and easy. When
58 * we receive data we tack it onto the ring buffer and make sure
59 * the APU assigned to it is playing over the data. When we fill
60 * the ring buffer we put the client to sleep until there is
61 * room again. Easy.
62 *
63 * However, this starts to stink when we use stereo. The APUs
64 * supposedly can decode LRLR packed stereo data, but it
65 * doesn't work. So we're forced to use dual mono APUs walking over
66 * mono encoded data. This requires us to split the input from
67 * the client and complicates the buffer maths tremendously. Ick.
68 *
69 * Once input is actually written, it will be worth pointing out
70 * that only 44/16 input actually works.
71 *
72 * History
73 * v0.04 - Sep 01 1999 - Zach Brown <zab@redhat.com>
74 * copied memory leak fix from sonicvibes driver
75 * different ac97 reset, play with 2.0 ac97, simplify ring bus setup
76 * bob freq code, region sanity, jitter sync fix; all from eric
77 *
78 * TODO
79 * recording is horribly broken
80 * codec timeouts (we're way under the example source's 20ms(!?))
81 * some people get indir reg timeouts?
82 * mixer interface broken?
83 * anyone have a pt101 codec?
84 * ess's ac97 codec (es1921) doesn't work
85 * mmap(), but beware stereo encoding nastiness.
86 * actually post pci writes
87 * check for bogon bios set irq/io windows
88 * compare our pci setup to the dos one, explains register timeouts?
89 * look really hard at the apu/bob/dma buffer code paths.
90 *
91 * the entire issue of smp safety needs to be looked at. cli() needs
92 * to be replaced with spinlock_irqsave, being very careful of call
93 * paths avoiding deadlock. if lock hold times are quick just
94 * use one big ass per device spinlock..
95 */
96
97 /*****************************************************************************/
98
99
100 #ifdef MODULE
101 #include <linux/module.h>
102 #ifdef MODVERSIONS
103 #include <linux/modversions.h>
104 #endif
105 #endif
106
107 #include <linux/version.h>
108 #include <linux/string.h>
109 #include <linux/ctype.h>
110 #include <linux/ioport.h>
111 #include <linux/sched.h>
112 #include <linux/delay.h>
113 #include <linux/sound.h>
114 #include <linux/malloc.h>
115 #include <linux/soundcard.h>
116 #include <linux/pci.h>
117 #include <asm/io.h>
118 #include <asm/dma.h>
119 #include <linux/init.h>
120 #include <linux/poll.h>
121 #include <linux/spinlock.h>
122 #include <asm/uaccess.h>
123 #include <asm/hardirq.h>
124
125 #include "maestro.h"
126 #include "maestro_tables.h"
127
128 /* --------------------------------------------------------------------- */
129
130 #define M_DEBUG 1
131
132 #ifdef M_DEBUG
133 static int debug=0;
134 #define M_printk(args...) {if (debug) printk(args);}
135 #else
136 #define M_printk(x)
137 #endif
138
139 /* --------------------------------------------------------------------- */
140
141 #define DRIVER_VERSION "0.04"
142
143 #ifndef PCI_VENDOR_ESS
144 #define PCI_VENDOR_ESS 0x125D
145 #define PCI_DEVICE_ID_ESS_ESS1968 0x1968 /* Maestro 2 */
146 #define PCI_DEVICE_ID_ESS_ESS1978 0x1978 /* Maestro 2E */
147
148 #define PCI_VENDOR_ESS_OLD 0x1285 /* vendor id for maestro 1 */
149 #define PCI_DEVICE_ID_ESS_ESS0100 0x0100 /* maestro 1 */
150 #endif /* PCI_VENDOR_ESS */
151
152 #define ESS_CHAN_HARD 0x100
153
154 #define ESS_CFMT_STEREO 0x01
155 #define ESS_CFMT_16BIT 0x02
156 #define ESS_CFMT_MASK 0x03
157 #define ESS_CFMT_ASHIFT 0
158 #define ESS_CFMT_CSHIFT 4
159
160 #define ESS_ENABLE_PE 1
161 #define ESS_ENABLE_RE 2
162
163 #define ESS_STATE_MAGIC 0x125D1968
164 #define ESS_CARD_MAGIC 0x19283746
165
166 #define DAC_RUNNING 1
167 #define ADC_RUNNING 2
168
169 static const unsigned sample_size[] = { 1, 2, 2, 4 };
170 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
171
172 enum card_types_t {
173 TYPE_MAESTRO,
174 TYPE_MAESTRO2,
175 TYPE_MAESTRO2E
176 };
177
178 static const char *card_names[]={
179 [TYPE_MAESTRO] = "ESS Maestro",
180 [TYPE_MAESTRO2] = "ESS Maestro 2",
181 [TYPE_MAESTRO2E] = "ESS Maestro 2E"
182 };
183
184 #define SND_DEV_DSP16 5
185
186 /* --------------------------------------------------------------------- */
187
188 struct ess_state {
189 unsigned int magic;
190 /* FIXME: we probably want submixers in here, but only one record pair */
191 u8 apu[4]; /* Left, Right, Left In, Right In */
192 u8 apu_mode[4]; /* Running mode for this APU */
193 u8 apu_pan[4]; /* Panning setup for this APU */
194 struct ess_card *card; /* Card info */
195 /* wave stuff */
196 unsigned int rateadc, ratedac;
197 unsigned char fmt, enable;
198
199 spinlock_t lock;
200 struct semaphore open_sem;
201 mode_t open_mode;
202 wait_queue_head_t open_wait;
203
204 /* soundcore stuff */
205 int dev_audio;
206
207 struct dmabuf {
208 void *rawbuf;
209 unsigned buforder;
210 unsigned numfrag;
211 unsigned fragshift;
212 unsigned hwptr, swptr;
213 unsigned total_bytes;
214 int count;
215 unsigned error; /* over/underrun */
216 wait_queue_head_t wait;
217 /* redundant, but makes calculations easier */
218 unsigned fragsize;
219 unsigned dmasize;
220 unsigned fragsamples;
221 /* OSS stuff */
222 unsigned mapped:1;
223 unsigned ready:1;
224 unsigned endcleared:1;
225 unsigned ossfragshift;
226 int ossmaxfrags;
227 unsigned subdivision;
228 u16 base; /* Offset for ptr */
229 } dma_dac, dma_adc;
230 };
231
232 struct ess_card {
233 unsigned int magic;
234
235 /* We keep maestro cards in a linked list */
236 struct ess_card *next;
237
238 int dev_mixer;
239
240 int card_type;
241
242 /* as most of this is static,
243 perhaps it should be a pointer to a global struct */
244 struct mixer_goo {
245 int modcnt;
246 int supported_mixers;
247 int stereo_mixers;
248 int record_sources;
249 /* the caller must guarantee arg sanity before calling these */
250 int (*read_mixer)(struct ess_card *card, int index);
251 void (*write_mixer)(struct ess_card *card,int mixer, int vol);
252 int (*recmask_io)(struct ess_card *card,int rw,int mask);
253 } mix;
254
255 struct ess_state channels[8];
256 u16 maestro_map[32]; /* Register map */
257
258 /* hardware resources */
259 u32 iobase;
260 u32 irq;
261
262 };
263
264 extern __inline__ unsigned ld2(unsigned int x)
265 {
266 unsigned r = 0;
267
268 if (x >= 0x10000) {
269 x >>= 16;
270 r += 16;
271 }
272 if (x >= 0x100) {
273 x >>= 8;
274 r += 8;
275 }
276 if (x >= 0x10) {
277 x >>= 4;
278 r += 4;
279 }
280 if (x >= 4) {
281 x >>= 2;
282 r += 2;
283 }
284 if (x >= 2)
285 r++;
286 return r;
287 }
288
289
290 /* --------------------------------------------------------------------- */
291
292 static struct ess_card *devs = NULL;
293
294 /* --------------------------------------------------------------------- */
295
296
297 /*
298 * ESS Maestro AC97 codec programming interface.
299 */
300
301 static void maestro_ac97_set(int io, u8 cmd, u16 val)
302 {
303 int i;
304 /*
305 * Wait for the codec bus to be free
306 */
307
308 for(i=0;i<10000;i++)
309 {
310 if(!(inb(io+ESS_AC97_INDEX)&1))
311 break;
312 }
313 /*
314 * Write the bus
315 */
316 outw(val, io+ESS_AC97_DATA);
317 mdelay(1);
318 outb(cmd, io+ESS_AC97_INDEX);
319 mdelay(1);
320 }
321
322 static u16 maestro_ac97_get(int io, u8 cmd)
323 {
324 int sanity=10000;
325 u16 data;
326 int i;
327
328 /*
329 * Wait for the codec bus to be free
330 */
331
332 for(i=0;i<10000;i++)
333 {
334 if(!(inb(io+ESS_AC97_INDEX)&1))
335 break;
336 }
337
338 outb(cmd|0x80, io+ESS_AC97_INDEX);
339 mdelay(1);
340
341 while(inb(io+ESS_AC97_INDEX)&1)
342 {
343 sanity--;
344 if(!sanity)
345 {
346 printk(KERN_ERR "maestro: ac97 codec read timeout.\n");
347 return 0;
348 }
349 }
350 data=inw(io+ESS_AC97_DATA);
351 mdelay(1);
352 return data;
353 }
354
355 /*
356 * The Maestro can be wired to a standard AC97 compliant codec
357 * (see www.intel.com for the pdf's on this), or to a PT101 codec
358 * which appears to be the ES1918 (data sheet on the esstech.com.tw site)
359 *
360 * The PT101 setup is untested.
361 */
362
363 static u16 maestro_ac97_init(int iobase)
364 {
365 int val, seid, caps;
366 u16 vend1, vend2;
367
368 #if 0 /* this needs to be thought about harder */
369 /* aim at the second codec */
370 outw(0x21, iobase+0x38);
371 outw(0x5555, iobase+0x3a);
372 outw(0x5555, iobase+0x3c);
373 udelay(1);
374 vend1 = maestro_ac97_get(iobase, 0x7c);
375 vend2 = maestro_ac97_get(iobase, 0x7e);
376 if(vend1 != 0xffff || vend2 != 0xffff) {
377 printk("maestro: second codec 0x%4x%4x found, enabling both. please report this.\n",
378 vend1,vend2);
379 /* enable them both */
380 outw(0x00, iobase+0x38);
381 outw(0xFFFC, iobase+0x3a);
382 outw(0x000C, iobase+0x3c);
383 } else {
384 /* back to the first only */
385 outw(0x0, iobase+0x38);
386 outw(0x0, iobase+0x3a);
387 outw(0x0, iobase+0x3c);
388 }
389 udelay(1);
390 #endif
391
392 /* perform codec reset */
393 maestro_ac97_set(iobase, 0x00, 0x0000);
394
395 /* should make sure we're ac97 2.1? */
396 vend1 = maestro_ac97_get(iobase, 0x7c);
397 vend2 = maestro_ac97_get(iobase, 0x7e);
398
399 val = maestro_ac97_get(iobase, 0x00);
400 seid = val >> 8;
401 caps = val & 255;
402
403 printk(KERN_INFO "maestro: AC97 Codec detected: v: 0x%2x%2x 3d: 0x%x caps: 0x%x\n",
404 vend1,vend2,seid, caps);
405
406 /* XXX endianness, dork head. */
407 /* magic vendor specifc init code, _no_ idea what these do */
408 switch ((long)(vend1 << 16) | vend2) {
409 case 0x545200ff: /* TriTech */
410
411 maestro_ac97_set(iobase,0x2a,0x0001);
412 maestro_ac97_set(iobase,0x2c,0x0000);
413 maestro_ac97_set(iobase,0x2c,0xffff);
414 break;
415 case 0x83847609: /* ESS 1921 */
416 maestro_ac97_set(iobase,0x76,0xABBA); /* o/~ Take a chance on me o/~ */
417 udelay(20);
418 maestro_ac97_set(iobase,0x78,0x3002);
419 udelay(20);
420 maestro_ac97_set(iobase,0x78,0x3802);
421 udelay(20);
422 break;
423 default: break;
424 }
425
426 /* set master, headphone, master mono */
427 maestro_ac97_set(iobase, 0x02, 0x0000);
428 /* always set headphones to max unmuted, OSS won't
429 let us change it :( */
430 maestro_ac97_set(iobase, 0x04, 0x0000);
431 maestro_ac97_set(iobase, 0x06, 0x0000);
432 maestro_ac97_set(iobase, 0x08, 0x0606);
433 /* beep, phone, mic, line, cd video, aux */
434 maestro_ac97_set(iobase, 0x0A, 0x1F1F);
435 maestro_ac97_set(iobase, 0x0C, 0x1F1F);
436 maestro_ac97_set(iobase, 0x0E, 0x1F1F);
437 maestro_ac97_set(iobase, 0x10, 0x1F1F);
438 maestro_ac97_set(iobase, 0x12, 0x1F1F);
439 maestro_ac97_set(iobase, 0x14, 0x1F1F);
440 maestro_ac97_set(iobase, 0x16, 0x1F1F);
441 /* unmute, but set pcm out to 1/2 */
442 maestro_ac97_set(iobase, 0x18, 0x0808);
443 /* null record select */
444 maestro_ac97_set(iobase, 0x1A, 0x0000);
445 /* record gain, record gain mic.. */
446 maestro_ac97_set(iobase, 0x1C, 0x0404);
447 maestro_ac97_set(iobase, 0x1E, 0x0404);
448 /* null misc stuff */
449 maestro_ac97_set(iobase, 0x20, 0x0000);
450 /* power up various units? */
451 maestro_ac97_set(iobase, 0x26, 0x000F);
452
453 /* lets see if they actually default to the spec :) */
454 if(maestro_ac97_get(iobase,0x36) ==0x8080) {
455 int reg;
456 printk("maestro: your ac97 might be 2.0, see if this makes sense:\n");
457 for(reg = 0x28; reg <= 0x58 ; reg += 2) {
458 printk(" 0x%2x: %4x\n",reg,maestro_ac97_get(iobase,reg));
459 }
460 }
461
462 return 0;
463 }
464
465 static u16 maestro_pt101_init(int iobase)
466 {
467 printk(KERN_INFO "maestro: PT101 Codec detected, initializing but _not_ installing mixer device.\n");
468 /* who knows.. */
469 maestro_ac97_set(iobase, 0x2A, 0x0001);
470 maestro_ac97_set(iobase, 0x2C, 0x0000);
471 maestro_ac97_set(iobase, 0x2C, 0xFFFF);
472 maestro_ac97_set(iobase, 0x10, 0x9F1F);
473 maestro_ac97_set(iobase, 0x12, 0x0808);
474 maestro_ac97_set(iobase, 0x14, 0x9F1F);
475 maestro_ac97_set(iobase, 0x16, 0x9F1F);
476 maestro_ac97_set(iobase, 0x18, 0x0404);
477 maestro_ac97_set(iobase, 0x1A, 0x0000);
478 maestro_ac97_set(iobase, 0x1C, 0x0000);
479 maestro_ac97_set(iobase, 0x02, 0x0404);
480 maestro_ac97_set(iobase, 0x04, 0x0808);
481 maestro_ac97_set(iobase, 0x0C, 0x801F);
482 maestro_ac97_set(iobase, 0x0E, 0x801F);
483 return 0;
484 }
485
486 static void maestro_ac97_reset(int ioaddr)
487 {
488 /* outw(0x2000, ioaddr+0x36);
489 inb(ioaddr);
490 mdelay(1);
491 outw(0x0000, ioaddr+0x36);
492 inb(ioaddr);
493 mdelay(1);*/
494
495 /* well this seems to work a little
496 better on the 2e */
497 /* this screws around with the gpio
498 mask/input/direction.. */
499 outw(0x0000, ioaddr+0x36);
500 udelay(20);
501 outw(0xFFFE, ioaddr+0x64);
502 outw(0x1, ioaddr+0x68);
503 outw(0x0, ioaddr+0x60);
504 udelay(20);
505 outw(0x1, ioaddr+0x60);
506 udelay(20); /* other source says 500ms.. INSANE */
507 outw(0x2000, ioaddr+0x36);
508 udelay(20);
509 outw(0x3000, ioaddr+0x36);
510 udelay(200);
511 outw(0x0001, ioaddr+0x68);
512 outw(0xFFFF, ioaddr+0x64);
513
514 /* strange strange reset tickling the ring bus */
515 outw(0x0, ioaddr+0x36);
516 udelay(20);
517 outw(0x200, ioaddr+0x36); /* first codec only */
518 udelay(20);
519 outw(0x0, ioaddr+0x36);
520 udelay(20);
521 outw(0x2000, ioaddr+0x36);
522 udelay(20);
523 outw(0x3000, ioaddr+0x36);
524 udelay(20);
525 }
526
527 /*
528 * Indirect register access. Not all registers are readable so we
529 * need to keep register state ourselves
530 */
531
532 #define WRITEABLE_MAP 0xEFFFFF
533 #define READABLE_MAP 0x64003F
534
535 /*
536 * The Maestro engineers were a little indirection happy. These indirected
537 * registers themselves include indirect registers at another layer
538 */
539
540 static void maestro_write(struct ess_state *ess, u16 reg, u16 data)
541 {
542 long ioaddr = ess->card->iobase;
543 unsigned long flags;
544 save_flags(flags);
545 cli();
546 outw(reg, ioaddr+0x02);
547 outw(data, ioaddr+0x00);
548 ess->card->maestro_map[reg]=data;
549 restore_flags(flags);
550 }
551
552 static u16 maestro_read(struct ess_state *ess, u16 reg)
553 {
554 long ioaddr = ess->card->iobase;
555 if(READABLE_MAP & (1<<reg))
556 {
557 unsigned long flags;
558 save_flags(flags);
559 cli();
560 outw(reg, ioaddr+0x02);
561 ess->card->maestro_map[reg]=inw(ioaddr+0x00);
562 restore_flags(flags);
563 }
564 return ess->card->maestro_map[reg];
565 }
566
567 /*
568 * These routines handle accessing the second level indirections to the
569 * wave ram.
570 */
571
572 /*
573 * The register names are the ones ESS uses (see 104T31.ZIP)
574 */
575
576 #define IDR0_DATA_PORT 0x00
577 #define IDR1_CRAM_POINTER 0x01
578 #define IDR2_CRAM_DATA 0x02
579 #define IDR3_WAVE_DATA 0x03
580 #define IDR4_WAVE_PTR_LOW 0x04
581 #define IDR5_WAVE_PTR_HI 0x05
582 #define IDR6_TIMER_CTRL 0x06
583 #define IDR7_WAVE_ROMRAM 0x07
584
585 static void apu_index_set(struct ess_state *ess, u16 index)
586 {
587 int i;
588 maestro_write(ess, IDR1_CRAM_POINTER, index);
589 for(i=0;i<1000;i++)
590 if(maestro_read(ess, IDR1_CRAM_POINTER)==index)
591 return;
592 printk(KERN_WARNING "maestro: APU register select failed.\n");
593 }
594
595 static void apu_data_set(struct ess_state *ess, u16 data)
596 {
597 int i;
598 for(i=0;i<1000;i++)
599 {
600 if(maestro_read(ess, IDR0_DATA_PORT)==data)
601 return;
602 maestro_write(ess, IDR0_DATA_PORT, data);
603 }
604 }
605
606 /*
607 * This is the public interface for APU manipulation. It handles the
608 * interlock to avoid two APU writes in parallel etc. Don't diddle
609 * directly with the stuff above.
610 */
611
612 static void apu_set_register(struct ess_state *ess, u16 channel, u8 reg, u16 data)
613 {
614 unsigned long flags;
615
616 if(channel&ESS_CHAN_HARD)
617 channel&=~ESS_CHAN_HARD;
618 else
619 {
620 if(channel>3)
621 printk("BAD CHANNEL %d.\n",channel);
622 else
623 channel = ess->apu[channel];
624 }
625
626 reg|=(channel<<4);
627
628 save_flags(flags);
629 cli();
630 apu_index_set(ess, reg);
631 apu_data_set(ess, data);
632 restore_flags(flags);
633 }
634
635 static u16 apu_get_register(struct ess_state *ess, u16 channel, u8 reg)
636 {
637 unsigned long flags;
638 u16 v;
639
640 if(channel&ESS_CHAN_HARD)
641 channel&=~ESS_CHAN_HARD;
642 else
643 channel = ess->apu[channel];
644
645 reg|=(channel<<4);
646
647 save_flags(flags);
648 cli();
649 apu_index_set(ess, reg);
650 v=maestro_read(ess, IDR0_DATA_PORT);
651 restore_flags(flags);
652 return v;
653 }
654
655
656 /*
657 * The wavecache does pci fetches for us and feeds
658 * them to the APUs..
659 * XXX describe interface
660 */
661
662 static void wave_set_register(struct ess_state *ess, u16 reg, u16 value)
663 {
664 long ioaddr = ess->card->iobase;
665 unsigned long flags;
666
667 save_flags(flags);
668 cli();
669 outw(reg, ioaddr+0x10);
670 outw(value, ioaddr+0x12);
671 restore_flags(flags);
672 }
673
674 static u16 wave_get_register(struct ess_state *ess, u16 reg)
675 {
676 long ioaddr = ess->card->iobase;
677 unsigned long flags;
678 u16 value;
679
680 save_flags(flags);
681 cli();
682 outw(reg, ioaddr+0x10);
683 value=inw(ioaddr+0x12);
684 restore_flags(flags);
685
686 return value;
687 }
688
689 static void sound_reset(int ioaddr)
690 {
691 outw(0x2000, 0x18+ioaddr);
692 udelay(1);
693 outw(0x0000, 0x18+ioaddr);
694 udelay(1);
695 }
696
697 static void set_apu_fmt(struct ess_state *s, int apu, int mode)
698 {
699 if(mode&ESS_CFMT_16BIT) {
700 s->apu_mode[apu] = 0x10;
701 s->apu_mode[apu+1] = 0x10;
702 } else {
703 s->apu_mode[apu] = 0x30;
704 s->apu_mode[apu+1] = 0x30;
705 }
706 }
707
708 static void set_fmt(struct ess_state *s, unsigned char mask, unsigned char data)
709 {
710 s->fmt = (s->fmt & mask) | data;
711 set_apu_fmt(s, 0, s->fmt & ESS_CFMT_MASK);
712 set_apu_fmt(s, 2, (s->fmt >> ESS_CFMT_CSHIFT) & ESS_CFMT_MASK);
713 }
714
715 static u16 compute_rate(u32 freq)
716 {
717 if(freq==48000)
718 return 0xFFFF;
719 freq<<=16;
720 freq/=48000;
721 return freq;
722 }
723
724 static void set_dac_rate(struct ess_state *s, unsigned rate)
725 {
726 u32 freq;
727
728 if (rate > 48000)
729 rate = 48000;
730 if (rate < 4000)
731 rate = 4000;
732
733 s->ratedac = rate;
734
735 if(!(s->fmt & ESS_CFMT_16BIT))
736 rate >>= 1; /* who knows */
737
738 /* M_printk("computing dac rate %d with mode %d\n",rate,s->fmt);*/
739
740 freq = compute_rate(rate);
741
742 /* Load the frequency, turn on 6dB, turn off the effects */
743 apu_set_register(s, 0, 2, (freq&0xFF)<<8|0x10);
744 apu_set_register(s, 0, 3, freq>>8);
745 apu_set_register(s, 1, 2, (freq&0xFF)<<8|0x10);
746 apu_set_register(s, 1, 3, freq>>8);
747 }
748
749 static void set_adc_rate(struct ess_state *s, unsigned rate)
750 {
751 u32 freq;
752
753 if (rate > 48000)
754 rate = 48000;
755 if (rate < 4000)
756 rate = 4000;
757
758 s->rateadc = rate;
759
760 freq = compute_rate(rate);
761
762 /* Load the frequency, turn on 6dB, turn off the effects */
763 apu_set_register(s, 2, 2, (freq&0xFF)<<8|0x10);
764 apu_set_register(s, 2, 3, freq>>8);
765 apu_set_register(s, 3, 2, (freq&0xFF)<<8|0x10);
766 apu_set_register(s, 3, 3, freq>>8);
767 }
768
769
770 /*
771 * Native play back driver
772 */
773
774 static void ess_play_setup(struct ess_state *ess, int mode, u32 rate, void *buffer, int size)
775 {
776 u32 pa;
777 u32 tmpval;
778 int high_apu = 0;
779 int channel;
780
781 M_printk("mode=%d rate=%d buf=%p len=%d.\n",
782 mode, rate, buffer, size);
783
784 /* all maestro sizes are in 16bit words */
785 size >>=1;
786
787 /* we're given the full size of the buffer, but
788 in stereo each channel will only play its half */
789 if(mode&ESS_CFMT_STEREO) {
790 size >>=1;
791 high_apu++;
792 }
793
794 for(channel=0; channel <= high_apu; channel++)
795 {
796 int i;
797
798 /*
799 * To understand this it helps to know how the
800 * wave cache works. There are 4 DSP wavecache
801 * blocks which are 0x1FC->0x1FF. They are selected
802 * by setting bits 22,21,20 of the address to
803 * 1 X Y where X Y select the block.
804 *
805 * In addition stereo pairing is supported. This is
806 * set in the wave cache control for the channel as is
807 * 8bit unsigned.
808 *
809 * Note that this causes a problem. With our limit of
810 * about 12 full duplex pairs (48 channels active) we
811 * will need to do a lot of juggling to get all the
812 * memory we want sufficiently close together.
813 *
814 * Even with 64K blocks that means
815 * 24 channel pairs
816 * 6 pairs/block
817 *
818 * 10K per channel pair = 5000 samples.
819 */
820
821 if(!channel)
822 pa = virt_to_bus(buffer);
823 else
824 /* right channel plays its split half.
825 *2 accomodates for rampant shifting earlier */
826 pa = virt_to_bus(buffer + size*2);
827
828 M_printk("sending pa %x to %d\n",pa,channel);
829
830 wave_set_register(ess, 0x01FC, (pa&0xFFE00000)>>12);
831
832 /* set the wavecache control reg */
833 tmpval = (pa - 0x10) & 0xFFF8;
834 #if 0
835 if(mode & 1) tmpval |= 2; /* stereo */
836 #endif
837 if(!(mode & 2)) tmpval |= 4; /* 8bit */
838 wave_set_register(ess, ess->apu[channel]<<3, tmpval);
839
840 pa&=0x1FFFFF; /* Low 21 bits */
841 pa>>=1; /* words */
842
843 /* base offset of dma calcs when reading the pointer
844 on this left one */
845 if(!channel) ess->dma_dac.base = pa&0xFFFF;
846
847 #if 0
848 if(mode&ESS_CFMT_STEREO) /* Enable stereo */
849 pa|=0x00800000;
850 #endif
851 pa|=0x00400000; /* System RAM */
852
853 /* Begin loading the APU */
854 for(i=0;i<15;i++) /* clear all PBRs */
855 apu_set_register(ess, channel, i, 0x0000);
856
857 /* Load the frequency, turn on 6dB, turn off the effects */
858 /* apu_set_register(ess, channel, 2, (rate&0xFF)<<8|0x10);
859 apu_set_register(ess, channel, 3, rate>>8);*/
860
861 /* XXX think about endianess when writing these registers */
862 /* Load the buffer into the wave engine */
863 apu_set_register(ess, channel, 4, ((pa>>16)&0xFF)<<8);
864 apu_set_register(ess, channel, 5, pa&0xFFFF);
865 apu_set_register(ess, channel, 6, (pa+size)&0xFFFF);
866 /* setting loop == sample len */
867 apu_set_register(ess, channel, 7, size);
868
869 /* clear effects/env.. */
870 apu_set_register(ess, channel, 8, 0x0000);
871 /* aplitudeNow to 0xd0? */
872 apu_set_register(ess, channel, 9, 0xD000);
873
874 /* set the panning reg of the apu to left/right/mid.. */
875
876 /* clear routing stuff */
877 apu_set_register(ess, channel, 11, 0x0000);
878 /* mark dma and turn on filter stuff? */
879 apu_set_register(ess, channel, 0, 0x400F);
880
881 if(mode&ESS_CFMT_STEREO)
882 /* set panning: left or right */
883 apu_set_register(ess, channel, 10, 0x8F00 | (channel ? 0x10 : 0));
884 else
885 apu_set_register(ess, channel, 10, 0x8F08);
886
887 }
888
889 /* clear WP interupts */
890 outw(1, ess->card->iobase+0x04);
891 /* enable WP ints */
892 outw(inw(ess->card->iobase+0x18)|4, ess->card->iobase+0x18);
893
894 set_dac_rate(ess,rate);
895
896 for(channel=0; channel<=high_apu; channel++)
897 {
898 /* Turn on the DMA */
899 if(mode&ESS_CFMT_16BIT)
900 {
901 apu_set_register(ess, channel, 0,
902 (apu_get_register(ess, channel, 0)&0xFF0F)|0x10);
903 ess->apu_mode[channel]=0x10;
904 }
905 else
906 {
907 apu_set_register(ess, channel, 0,
908 (apu_get_register(ess, channel, 0)&0xFF0F)|0x30);
909 ess->apu_mode[channel]=0x30;
910 }
911 }
912 }
913
914 /* --------------------------------------------------------------------- */
915
916 static void set_dmaa(struct ess_state *s, unsigned int addr, unsigned int count)
917 {
918 }
919
920 static void set_dmac(struct ess_state *s, unsigned int addr, unsigned int count)
921 {
922 }
923
924 /* Playback pointer */
925 extern __inline__ unsigned get_dmaa(struct ess_state *s)
926 {
927 long ioport = s->card->iobase;
928 int offset;
929
930 outw(1, ioport+2);
931 outw(s->apu[0]<<4|5, ioport);
932 outw(0, ioport+2);
933 offset=inw(ioport);
934
935 /* M_printk("dmaa: offset: %d, base: %d\n",offset,s->dma_dac.base);*/
936
937 offset-=s->dma_dac.base;
938
939 return (offset&0xFFFE)/*<<1*/; /* XXX printk didn't have it */
940 }
941
942 /* Record pointer */
943 extern __inline__ unsigned get_dmac(struct ess_state *s)
944 {
945 long ioport = s->card->iobase;
946 int offset;
947
948 outw(1, ioport+2);
949 outw(s->apu[2]<<4|5, ioport);
950 outw(0, ioport+2);
951 offset=inw(ioport);
952
953 /* The offset is an address not a position relative to base */
954
955 return (offset&0xFFFE)<<1; /* hardware is in words */
956 }
957
958 /*
959 * Meet Bob, the timer...
960 */
961
962 static void ess_interrupt(int irq, void *dev_id, struct pt_regs *regs);
963
964 #define ESS_HW_TIMER
965
966 #ifndef ESS_HW_TIMER
967
968 /* old kernel timer based timer ints, should BOB prove flakey */
969
970 static struct timer_list tmp_timer;
971
972 static int bob_stopped;
973
974 static void ess_interrupt_fake(unsigned long v)
975 {
976 ess_interrupt(5, (void *)v, NULL);
977 del_timer(&tmp_timer);
978 if(!bob_stopped)
979 {
980 tmp_timer.expires=jiffies+1;
981 add_timer(&tmp_timer);
982 }
983 else
984 M_printk("Stopping bob (SW)\n");
985 }
986
987 static void stop_bob(struct ess_state *s)
988 {
989 bob_stopped=1;
990 }
991
992 static void kill_bob(struct ess_state *s)
993 {
994 del_timer(&tmp_timer);
995 M_printk("Killing bob (SW)\n");
996 }
997
998 static void start_bob(struct ess_state *s)
999 {
1000 static int init=1;
1001 if(init)
1002 {
1003 init=0;
1004 init_timer(&tmp_timer);
1005 tmp_timer.function = ess_interrupt_fake;
1006 }
1007 bob_stopped = 0;
1008 if(!timer_pending(&tmp_timer))
1009 {
1010 del_timer(&tmp_timer);
1011 tmp_timer.expires = jiffies+1;
1012 tmp_timer.data = (unsigned long)s->card;
1013 add_timer(&tmp_timer);
1014 M_printk("Starting bob (SW)\n");
1015 }
1016 }
1017
1018 #else
1019
1020 /* nice HW BOB implementation. */
1021
1022 static void stop_bob(struct ess_state *s)
1023 {
1024 /* Mask IDR 11,17 */
1025 maestro_write(s, 0x11, maestro_read(s, 0x11)&~1);
1026 maestro_write(s, 0x17, maestro_read(s, 0x17)&~1);
1027 }
1028
1029 /* eventually we could be clever and limit bob ints
1030 to the frequency at which our smallest duration
1031 chunks may expire */
1032 #define ESS_SYSCLK 50000000
1033 static void start_bob(struct ess_state *s)
1034 {
1035 int prescale;
1036 int divide;
1037
1038 int freq = 200; /* requested frequency - calculate what we want here. */
1039
1040 stop_bob(s); /* make sure bob's not already running */
1041
1042 /* compute ideal interrupt frequency for buffer size & play rate */
1043 /* first, find best prescaler value to match freq */
1044 for(prescale=5;prescale<12;prescale++)
1045 if(freq > (ESS_SYSCLK>>(prescale+9)))
1046 break;
1047
1048 /* next, back off prescaler whilst getting divider into optimum range */
1049 divide=1;
1050 while((prescale > 5) && (divide<32))
1051 {
1052 prescale--;
1053 divide <<=1;
1054 }
1055 divide>>=1;
1056
1057 /* now fine-tune the divider for best match */
1058 for(;divide<31;divide++)
1059 if(freq >= ((ESS_SYSCLK>>(prescale+9))/(divide+1)))
1060 break;
1061
1062 /* divide = 0 is illegal, but don't let prescale = 4! */
1063 if(divide == 0)
1064 {
1065 divide++;
1066 if(prescale>5)
1067 prescale--;
1068 }
1069
1070 maestro_write(s, 6, 0x9000 | (prescale<<5) | divide); /* set reg */
1071
1072 /* Now set IDR 11/17 */
1073 maestro_write(s, 0x11, maestro_read(s, 0x11)|1);
1074 maestro_write(s, 0x17, maestro_read(s, 0x17)|1);
1075 }
1076 #endif /* ESS_HW_TIMER */
1077 /* --------------------------------------------------------------------- */
1078
1079 static int adc_active = 0;
1080
1081 extern inline void stop_adc(struct ess_state *s)
1082 {
1083 unsigned long flags;
1084
1085 spin_lock_irqsave(&s->lock, flags);
1086 /* Stop left and right recording APU */
1087 s->enable &= ~ADC_RUNNING;
1088 apu_set_register(s, 2, 0, apu_get_register(s, 2, 0)&0xFF0F);
1089 apu_set_register(s, 3, 0, apu_get_register(s, 3, 0)&0xFF0F);
1090 adc_active&=~1;
1091 /* if(!adc_active)
1092 stop_bob(s); */
1093 spin_unlock_irqrestore(&s->lock, flags);
1094 }
1095
1096 extern inline void stop_dac(struct ess_state *s)
1097 {
1098 unsigned long flags;
1099
1100 spin_lock_irqsave(&s->lock, flags);
1101 s->enable &= ~DAC_RUNNING;
1102 apu_set_register(s, 0, 0, apu_get_register(s, 0, 0)&0xFF0F);
1103 apu_set_register(s, 1, 0, apu_get_register(s, 1, 0)&0xFF0F);
1104 adc_active&=~2;
1105 /* if(!adc_active)
1106 stop_bob(s); */
1107 spin_unlock_irqrestore(&s->lock, flags);
1108 }
1109
1110 static void start_dac(struct ess_state *s)
1111 {
1112 unsigned long flags;
1113
1114 spin_lock_irqsave(&s->lock, flags);
1115 if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
1116 s->enable |= DAC_RUNNING;
1117
1118 apu_set_register(s, 0, 0,
1119 (apu_get_register(s, 0, 0)&0xFF0F)|s->apu_mode[0]);
1120
1121 if(s->fmt & ESS_CFMT_STEREO)
1122 apu_set_register(s, 1, 0,
1123 (apu_get_register(s, 1, 0)&0xFF0F)|s->apu_mode[1]);
1124 }
1125 /* if(!adc_active)
1126 start_bob(s);*/
1127 adc_active|=2;
1128 spin_unlock_irqrestore(&s->lock, flags);
1129 }
1130
1131 static void start_adc(struct ess_state *s)
1132 {
1133 unsigned long flags;
1134
1135 spin_lock_irqsave(&s->lock, flags);
1136 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
1137 && s->dma_adc.ready) {
1138 s->enable |= ADC_RUNNING;
1139 apu_set_register(s, 2, 0,
1140 (apu_get_register(s, 2, 0)&0xFF0F)|s->apu_mode[2]);
1141 apu_set_register(s, 3, 0,
1142 (apu_get_register(s, 3, 0)&0xFF0F)|s->apu_mode[3]);
1143 }
1144 /* if(!adc_active)
1145 start_bob(s); */
1146 adc_active|=1;
1147 spin_unlock_irqrestore(&s->lock, flags);
1148 }
1149
1150 /* --------------------------------------------------------------------- */
1151
1152 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
1153 #define DMABUF_MINORDER 1
1154
1155 static void dealloc_dmabuf(struct dmabuf *db)
1156 {
1157 unsigned long map, mapend;
1158
1159 if (db->rawbuf) {
1160 /* undo marking the pages as reserved */
1161 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1162 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
1163 clear_bit(PG_reserved, &mem_map[map].flags);
1164 free_pages((unsigned long)db->rawbuf, db->buforder);
1165 }
1166 db->rawbuf = NULL;
1167 db->mapped = db->ready = 0;
1168 }
1169
1170
1171 static int prog_dmabuf(struct ess_state *s, unsigned rec)
1172 {
1173 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
1174 unsigned rate = rec ? s->rateadc : s->ratedac;
1175 int order;
1176 unsigned bytepersec;
1177 unsigned bufs;
1178 unsigned long map, mapend;
1179 unsigned char fmt;
1180 unsigned long flags;
1181
1182 spin_lock_irqsave(&s->lock, flags);
1183 fmt = s->fmt;
1184 if (rec) {
1185 s->enable &= ~ESS_ENABLE_RE;
1186 fmt >>= ESS_CFMT_CSHIFT;
1187 } else {
1188 s->enable &= ~ESS_ENABLE_PE;
1189 fmt >>= ESS_CFMT_ASHIFT;
1190 }
1191 spin_unlock_irqrestore(&s->lock, flags);
1192
1193 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
1194
1195 if (!db->rawbuf) {
1196 db->ready = db->mapped = 0;
1197
1198 /* alloc as big a chunk as we can */
1199 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
1200 if((db->rawbuf = (void *)__get_free_pages(GFP_KERNEL|GFP_DMA, order)))
1201 break;
1202
1203 if (!db->rawbuf)
1204 return -ENOMEM;
1205
1206 db->buforder = order;
1207
1208 if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
1209 printk(KERN_DEBUG "maestro: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
1210 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
1211
1212 if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
1213 printk(KERN_DEBUG "maestro: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
1214 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
1215
1216 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
1217 mapend = MAP_NR(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
1218 for (map = MAP_NR(db->rawbuf); map <= mapend; map++)
1219 set_bit(PG_reserved, &mem_map[map].flags);
1220 }
1221 bytepersec = rate << sample_shift[fmt];
1222 bufs = PAGE_SIZE << db->buforder;
1223 if (db->ossfragshift) {
1224 if ((1000 << db->ossfragshift) < bytepersec)
1225 db->fragshift = ld2(bytepersec/1000);
1226 else
1227 db->fragshift = db->ossfragshift;
1228 } else {
1229 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
1230 if (db->fragshift < 3)
1231 db->fragshift = 3;
1232 }
1233 db->numfrag = bufs >> db->fragshift;
1234 while (db->numfrag < 4 && db->fragshift > 3) {
1235 db->fragshift--;
1236 db->numfrag = bufs >> db->fragshift;
1237 }
1238 db->fragsize = 1 << db->fragshift;
1239 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
1240 db->numfrag = db->ossmaxfrags;
1241 db->fragsamples = db->fragsize >> sample_shift[fmt];
1242 db->dmasize = db->numfrag << db->fragshift;
1243 memset(db->rawbuf, (fmt & ESS_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
1244 spin_lock_irqsave(&s->lock, flags);
1245 if (rec) {
1246 set_dmac(s, virt_to_bus(db->rawbuf), db->numfrag << db->fragshift);
1247 /* program enhanced mode registers */
1248 /* FILL */
1249 } else {
1250 /* set_dmaa(s, virt_to_bus(db->rawbuf), db->numfrag << db->fragshift); */
1251 /* program enhanced mode registers */
1252 /* FILL */
1253 /*set_dac_rate(s, s->ratedac); redundant */
1254 ess_play_setup(s, fmt, s->ratedac,
1255 db->rawbuf, db->numfrag << db->fragshift);
1256 }
1257 spin_unlock_irqrestore(&s->lock, flags);
1258 db->ready = 1;
1259 return 0;
1260 }
1261
1262 /* XXX haha, way broken with our split stereo setup. giggle. */
1263 extern __inline__ void clear_advance(struct ess_state *s)
1264 {
1265 unsigned char c = (s->fmt & (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT)) ? 0 : 0x80;
1266 unsigned char *buf = s->dma_dac.rawbuf;
1267 unsigned bsize = s->dma_dac.dmasize;
1268 unsigned bptr = s->dma_dac.swptr;
1269 unsigned len = s->dma_dac.fragsize;
1270
1271 if (bptr + len > bsize) {
1272 unsigned x = bsize - bptr;
1273 memset(buf + bptr, c, x);
1274 /* account for wrapping? */
1275 bptr = 0;
1276 len -= x;
1277 }
1278 memset(buf + bptr, c, len);
1279 }
1280
1281 /* call with spinlock held! */
1282 static void ess_update_ptr(struct ess_state *s)
1283 {
1284 unsigned hwptr;
1285 int diff;
1286
1287 /* ADC is way broken. compare to DAC.. */
1288 /* update ADC pointer */
1289 if (s->dma_adc.ready) {
1290 hwptr = (/*s->dma_adc.dmasize - */get_dmac(s)) % s->dma_adc.dmasize;
1291 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
1292 s->dma_adc.hwptr = hwptr;
1293 s->dma_adc.total_bytes += diff;
1294 s->dma_adc.count += diff;
1295 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1296 wake_up(&s->dma_adc.wait);
1297 if (!s->dma_adc.mapped) {
1298 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
1299 s->enable &= ~ESS_ENABLE_RE;
1300 /* FILL ME
1301 wrindir(s, SV_CIENABLE, s->enable); */
1302 stop_adc(s);
1303 s->dma_adc.error++;
1304 }
1305 }
1306 }
1307 /* update DAC pointer */
1308 if (s->dma_dac.ready) {
1309 /* this is so gross. */
1310 hwptr = (/*s->dma_dac.dmasize -*/ get_dmaa(s)) % s->dma_dac.dmasize;
1311 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
1312 /* M_printk("updating dac: hwptr: %d diff: %d\n",hwptr,diff);*/
1313 s->dma_dac.hwptr = hwptr;
1314 s->dma_dac.total_bytes += diff;
1315 if (s->dma_dac.mapped) {
1316 s->dma_dac.count += diff;
1317 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1318 wake_up(&s->dma_dac.wait);
1319 } else {
1320 s->dma_dac.count -= diff;
1321 /* M_printk("maestro: ess_update_ptr: diff: %d, count: %d\n", diff, s->dma_dac.count); */
1322 if (s->dma_dac.count <= 0) {
1323 s->enable &= ~ESS_ENABLE_PE;
1324 /* FILL ME
1325 wrindir(s, SV_CIENABLE, s->enable); */
1326 /* XXX how on earth can calling this with the lock held work.. */
1327 stop_dac(s);
1328 /* brute force everyone back in sync, sigh */
1329 s->dma_dac.count = 0;
1330 s->dma_dac.swptr = 0;
1331 s->dma_dac.hwptr = 0;
1332 s->dma_dac.error++;
1333 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
1334 clear_advance(s);
1335 s->dma_dac.endcleared = 1;
1336 }
1337 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
1338 wake_up(&s->dma_dac.wait);
1339 }
1340 }
1341 }
1342
1343 static void ess_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1344 {
1345 struct ess_state *s;
1346 struct ess_card *c = (struct ess_card *)dev_id;
1347 int i;
1348 u32 event;
1349
1350 event = inb(c->iobase+0x1A);
1351
1352 outw(inw(c->iobase+4)&1, c->iobase+4);
1353
1354 /* M_printk("maestro int: %x\n",event);*/
1355
1356 if(event&(1<<6))
1357 {
1358 /* XXX if we have a hw volume control int enable
1359 all the ints? doesn't make sense.. */
1360 event = inw(c->iobase+0x18);
1361 outb(0xFF, c->iobase+0x1A);
1362 }
1363 else
1364 {
1365 /* else ack 'em all, i imagine */
1366 outb(0xFF, c->iobase+0x1A);
1367 }
1368
1369 /*
1370 * Update the pointers for all APU's we are running.
1371 */
1372 for(i=0;i<8;i++)
1373 {
1374 s=&c->channels[i];
1375 if(s->dev_audio == -1)
1376 break;
1377 spin_lock(&s->lock);
1378 ess_update_ptr(s);
1379 spin_unlock(&s->lock);
1380 }
1381 }
1382
1383
1384 /* --------------------------------------------------------------------- */
1385
1386 static const char invalid_magic[] = KERN_CRIT "maestro: invalid magic value in %s\n";
1387
1388 #define VALIDATE_MAGIC(FOO,MAG) \
1389 ({ \
1390 if (!(FOO) || (FOO)->magic != MAG) { \
1391 printk(invalid_magic,__FUNCTION__); \
1392 return -ENXIO; \
1393 } \
1394 })
1395
1396 #define VALIDATE_STATE(a) VALIDATE_MAGIC(a,ESS_STATE_MAGIC)
1397 #define VALIDATE_CARD(a) VALIDATE_MAGIC(a,ESS_CARD_MAGIC)
1398
1399 /* --------------------------------------------------------------------- */
1400
1401 /* ac97 mixer routines. */
1402
1403 #define AC97_STEREO_MASK (SOUND_MASK_VOLUME|\
1404 SOUND_MASK_PCM|SOUND_MASK_LINE|SOUND_MASK_CD|\
1405 SOUND_MASK_VIDEO|SOUND_MASK_LINE1|SOUND_MASK_IGAIN)
1406
1407 #define AC97_SUPPORTED_MASK (AC97_STEREO_MASK | \
1408 SOUND_MASK_BASS|SOUND_MASK_TREBLE|SOUND_MASK_MIC|\
1409 SOUND_MASK_SPEAKER)
1410
1411 #define AC97_RECORD_MASK (SOUND_MASK_MIC|\
1412 SOUND_MASK_CD| SOUND_MASK_VIDEO| SOUND_MASK_LINE1| SOUND_MASK_LINE|\
1413 SOUND_MASK_PHONEIN)
1414
1415 #define supported_mixer(CARD,FOO) ( CARD->mix.supported_mixers & (1<<FOO) )
1416
1417 static struct ac97_mixer_hw {
1418 unsigned char offset;
1419 int scale;
1420 } ac97_hw[SOUND_MIXER_NRDEVICES]= {
1421 [SOUND_MIXER_VOLUME] = {0x02,63},
1422 [SOUND_MIXER_BASS] = {0x08,15},
1423 [SOUND_MIXER_TREBLE] = {0x08,15},
1424 [SOUND_MIXER_SPEAKER] = {0x0a,15},
1425 [SOUND_MIXER_MIC] = {0x0e,31},
1426 [SOUND_MIXER_LINE] = {0x10,31},
1427 [SOUND_MIXER_CD] = {0x12,31},
1428 [SOUND_MIXER_VIDEO] = {0x14,31},
1429 [SOUND_MIXER_LINE1] = {0x16,31},
1430 [SOUND_MIXER_PCM] = {0x18,31},
1431 [SOUND_MIXER_IGAIN] = {0x1c,31}
1432 };
1433
1434 /* reads the given OSS mixer from the ac97
1435 the caller must have insured that the ac97 knows
1436 about that given mixer, and should be holding a
1437 spinlock for the card */
1438 static int ac97_read_mixer(struct ess_card *card, int mixer)
1439 {
1440 u16 val;
1441 int ret=0;
1442 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
1443
1444 val = maestro_ac97_get(card->iobase , mh->offset);
1445
1446 if(AC97_STEREO_MASK & (1<<mixer)) {
1447 /* nice stereo mixers .. */
1448 int left,right;
1449
1450 left = (val >> 8) & 0x7f;
1451 right = val & 0x7f;
1452
1453 right = 100 - ((right * 100) / mh->scale);
1454 left = 100 - ((left * 100) / mh->scale);
1455 ret = left | (right << 8);
1456 } else if (mixer == SOUND_MIXER_SPEAKER) {
1457 ret = 100 - ((((val & 0x1e)>>1) * 100) / mh->scale);
1458 } else if (mixer == SOUND_MIXER_MIC) {
1459 ret = 100 - (((val & 0x1f) * 100) / mh->scale);
1460 /* the low bit is optional in the tone sliders and masking
1461 it lets is avoid the 0xf 'bypass'.. */
1462 } else if (mixer == SOUND_MIXER_BASS) {
1463 ret = 100 - ((((val >> 8) & 0xe) * 100) / mh->scale);
1464 } else if (mixer == SOUND_MIXER_TREBLE) {
1465 ret = 100 - (((val & 0xe) * 100) / mh->scale);
1466 }
1467
1468 M_printk("read mixer %d (0x%x) %x -> %x\n",mixer,mh->offset,val,ret);
1469
1470 return ret;
1471 }
1472
1473 /* write the OSS encoded volume to the given OSS encoded mixer,
1474 again caller's job to make sure all is well in arg land,
1475 call with spinlock held */
1476 static void ac97_write_mixer(struct ess_card *card,int mixer, int vol)
1477 {
1478 u16 val=0;
1479 unsigned left, right;
1480 struct ac97_mixer_hw *mh = &ac97_hw[mixer];
1481
1482 /* cleanse input a little */
1483 right = ((vol >> 8) & 0x7f) ;
1484 left = (vol & 0x7f) ;
1485
1486 if(right > 100) right = 100;
1487 if(left > 100) left = 100;
1488
1489 M_printk("wrote mixer %d (0x%x) %d,%d",mixer,mh->offset,left,right);
1490
1491 if(AC97_STEREO_MASK & (1<<mixer)) {
1492 /* stereo mixers */
1493
1494 right = ((100 - right) * mh->scale) / 100;
1495 left = ((100 - left) * mh->scale) / 100;
1496
1497 val = (left << 8) | right;
1498 } else if (mixer == SOUND_MIXER_SPEAKER) {
1499 val = (((100 - left) * mh->scale) / 100) << 1;
1500 } else if (mixer == SOUND_MIXER_MIC) {
1501 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x001f;
1502 val |= (((100 - left) * mh->scale) / 100);
1503 /* the low bit is optional in the tone sliders and masking
1504 it lets is avoid the 0xf 'bypass'.. */
1505 } else if (mixer == SOUND_MIXER_BASS) {
1506 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x0f00;
1507 val |= ((((100 - left) * mh->scale) / 100) << 8) & 0xe0;
1508 } else if (mixer == SOUND_MIXER_TREBLE) {
1509 val = maestro_ac97_get(card->iobase , mh->offset) & ~0x000f;
1510 val |= (((100 - left) * mh->scale) / 100) & 0xe;
1511 }
1512
1513 maestro_ac97_set(card->iobase , mh->offset, val);
1514
1515 M_printk(" -> %x\n",val);
1516 }
1517
1518 enum ac97_recsettings {
1519 AC97_REC_MIC=0,
1520 AC97_REC_CD,
1521 AC97_REC_VIDEO,
1522 AC97_REC_AUX,
1523 AC97_REC_LINE,
1524 AC97_REC_STEREO, /* combination of all enabled outputs.. */
1525 AC97_REC_MONO, /*.. or the mono equivalent */
1526 AC97_REC_PHONE
1527 };
1528 static unsigned int ac97_rm2oss[] = {
1529 [AC97_REC_MIC] = SOUND_MASK_MIC,
1530 [AC97_REC_CD] = SOUND_MASK_CD,
1531 [AC97_REC_VIDEO] = SOUND_MASK_VIDEO,
1532 [AC97_REC_AUX] = SOUND_MASK_LINE1,
1533 [AC97_REC_LINE] = SOUND_MASK_LINE,
1534 [AC97_REC_PHONE] = SOUND_MASK_PHONEIN
1535 };
1536
1537 /* indexed by bit position, XXX dependant on OSS header internals */
1538 static unsigned int ac97_oss_rm[] = {
1539 [SOUND_MIXER_MIC] = AC97_REC_MIC,
1540 [SOUND_MIXER_CD] = AC97_REC_CD,
1541 [SOUND_MIXER_VIDEO] = AC97_REC_VIDEO,
1542 [SOUND_MIXER_LINE1] = AC97_REC_AUX,
1543 [SOUND_MIXER_LINE] = AC97_REC_LINE,
1544 [SOUND_MIXER_PHONEIN] = AC97_REC_PHONE
1545 };
1546
1547 /* read or write the recmask
1548 the ac97 can really have left and right recording
1549 inputs independantly set, but OSS doesn't seem to
1550 want us to express that to the user.
1551 the caller guarantees that we have a supported bit set,
1552 and they must be holding the card's spinlock */
1553 static int ac97_recmask_io(struct ess_card *card, int rw, int mask)
1554 {
1555 unsigned int val;
1556
1557 if (rw) {
1558 /* read it from the card */
1559 val = maestro_ac97_get(card->iobase, 0x1a) & 0x7;
1560 return ac97_rm2oss[val];
1561 }
1562
1563 /* else, write the first set in the mask as the
1564 output */
1565
1566 val = ffs(mask);
1567 val = ac97_oss_rm[val-1];
1568 val |= val << 8; /* set both channels */
1569
1570 maestro_ac97_set(card->iobase,0x1a,val);
1571
1572 return 0;
1573 };
1574
1575 static int ac97_mixer_ioctl(struct ess_card *card, unsigned int cmd, unsigned long arg)
1576 {
1577 unsigned long flags;
1578 int i, val=0;
1579 struct ess_state *s = &card->channels[0];
1580
1581 VALIDATE_CARD(card);
1582 if (cmd == SOUND_MIXER_INFO) {
1583 mixer_info info;
1584 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1585 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1586 info.modify_counter = card->mix.modcnt;
1587 if (copy_to_user((void *)arg, &info, sizeof(info)))
1588 return -EFAULT;
1589 return 0;
1590 }
1591 if (cmd == SOUND_OLD_MIXER_INFO) {
1592 _old_mixer_info info;
1593 strncpy(info.id, card_names[card->card_type], sizeof(info.id));
1594 strncpy(info.name,card_names[card->card_type],sizeof(info.name));
1595 if (copy_to_user((void *)arg, &info, sizeof(info)))
1596 return -EFAULT;
1597 return 0;
1598 }
1599 if (cmd == OSS_GETVERSION)
1600 return put_user(SOUND_VERSION, (int *)arg);
1601
1602 if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
1603 return -EINVAL;
1604
1605 if (_IOC_DIR(cmd) == _IOC_READ) {
1606 switch (_IOC_NR(cmd)) {
1607 case SOUND_MIXER_RECSRC: /* give them the current record source */
1608 spin_lock_irqsave(&s->lock, flags);
1609 val = card->mix.recmask_io(card,1,0);
1610 spin_unlock_irqrestore(&s->lock, flags);
1611 break;
1612
1613 case SOUND_MIXER_DEVMASK: /* give them the supported mixers */
1614 val = card->mix.supported_mixers;
1615 break;
1616
1617 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1618 val = card->mix.record_sources;
1619 break;
1620
1621 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1622 val = card->mix.stereo_mixers;
1623 break;
1624
1625 case SOUND_MIXER_CAPS:
1626 val = SOUND_CAP_EXCL_INPUT;
1627 break;
1628
1629 default: /* read a specific mixer */
1630 i = _IOC_NR(cmd);
1631
1632 if ( ! supported_mixer(card,i))
1633 return -EINVAL;
1634
1635 spin_lock_irqsave(&s->lock, flags);
1636 val = card->mix.read_mixer(card,i);
1637 spin_unlock_irqrestore(&s->lock, flags);
1638
1639 break;
1640 }
1641 return put_user(val,(int *)arg);
1642 }
1643
1644 if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
1645 return -EINVAL;
1646
1647 card->mix.modcnt++;
1648
1649 get_user_ret(val, (int *)arg, -EFAULT);
1650
1651 switch (_IOC_NR(cmd)) {
1652 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1653
1654 if(! (val &= card->mix.record_sources)) return -EINVAL;
1655
1656 spin_lock_irqsave(&s->lock, flags);
1657 card->mix.recmask_io(card,0,val);
1658 spin_unlock_irqrestore(&s->lock, flags);
1659 return 0;
1660
1661 default:
1662 i = _IOC_NR(cmd);
1663
1664 if ( ! supported_mixer(card,i))
1665 return -EINVAL;
1666
1667 spin_lock_irqsave(&s->lock, flags);
1668 card->mix.write_mixer(card,i,val);
1669 spin_unlock_irqrestore(&s->lock, flags);
1670
1671 return 0;
1672 }
1673 }
1674
1675 /* --------------------------------------------------------------------- */
1676
1677 static loff_t ess_llseek(struct file *file, loff_t offset, int origin)
1678 {
1679 return -ESPIPE;
1680 }
1681
1682 /* --------------------------------------------------------------------- */
1683
1684 static int ess_open_mixdev(struct inode *inode, struct file *file)
1685 {
1686 int minor = MINOR(inode->i_rdev);
1687 struct ess_card *card = devs;
1688
1689 while (card && card->dev_mixer != minor)
1690 card = card->next;
1691 if (!card)
1692 return -ENODEV;
1693
1694 file->private_data = card;
1695 MOD_INC_USE_COUNT;
1696 return 0;
1697 }
1698
1699 static int ess_release_mixdev(struct inode *inode, struct file *file)
1700 {
1701 struct ess_card *card = (struct ess_card *)file->private_data;
1702
1703 VALIDATE_CARD(card);
1704
1705 MOD_DEC_USE_COUNT;
1706 return 0;
1707 }
1708
1709 static int ess_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1710 {
1711 struct ess_card *card = (struct ess_card *)file->private_data;
1712
1713 VALIDATE_CARD(card);
1714
1715 return ac97_mixer_ioctl(card, cmd, arg);
1716 }
1717
1718 static /*const*/ struct file_operations ess_mixer_fops = {
1719 &ess_llseek,
1720 NULL, /* read */
1721 NULL, /* write */
1722 NULL, /* readdir */
1723 NULL, /* poll */
1724 &ess_ioctl_mixdev,
1725 NULL, /* mmap */
1726 &ess_open_mixdev,
1727 NULL, /* flush */
1728 &ess_release_mixdev,
1729 NULL, /* fsync */
1730 NULL, /* fasync */
1731 NULL, /* check_media_change */
1732 NULL, /* revalidate */
1733 NULL, /* lock */
1734 };
1735
1736 /* --------------------------------------------------------------------- */
1737
1738 static int drain_dac(struct ess_state *s, int nonblock)
1739 {
1740 DECLARE_WAITQUEUE(wait,current);
1741 unsigned long flags;
1742 int count, tmo;
1743
1744 if (s->dma_dac.mapped || !s->dma_dac.ready)
1745 return 0;
1746 current->state = TASK_INTERRUPTIBLE;
1747 add_wait_queue(&s->dma_dac.wait, &wait);
1748 for (;;) {
1749 spin_lock_irqsave(&s->lock, flags);
1750 count = s->dma_dac.count;
1751 spin_unlock_irqrestore(&s->lock, flags);
1752 if (count <= 0)
1753 break;
1754 if (signal_pending(current))
1755 break;
1756 if (nonblock) {
1757 remove_wait_queue(&s->dma_dac.wait, &wait);
1758 current->state = TASK_RUNNING;
1759 return -EBUSY;
1760 }
1761 tmo = (count * HZ) / s->ratedac;
1762 tmo >>= sample_shift[(s->fmt >> ESS_CFMT_ASHIFT) & ESS_CFMT_MASK];
1763 if (!schedule_timeout(tmo ? : 1) && tmo)
1764 printk(KERN_DEBUG "maestro: dma timed out??\n");
1765 }
1766 remove_wait_queue(&s->dma_dac.wait, &wait);
1767 current->state = TASK_RUNNING;
1768 if (signal_pending(current))
1769 return -ERESTARTSYS;
1770 return 0;
1771 }
1772
1773 /* --------------------------------------------------------------------- */
1774
1775 static ssize_t ess_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1776 {
1777 struct ess_state *s = (struct ess_state *)file->private_data;
1778 ssize_t ret;
1779 unsigned long flags;
1780 unsigned swptr;
1781 /* for damned dual players */
1782 int cnt;
1783
1784 VALIDATE_STATE(s);
1785 if (ppos != &file->f_pos)
1786 return -ESPIPE;
1787 if (s->dma_adc.mapped)
1788 return -ENXIO;
1789 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1790 return ret;
1791 if (!access_ok(VERIFY_WRITE, buffer, count))
1792 return -EFAULT;
1793 ret = 0;
1794 #if 0
1795 spin_lock_irqsave(&s->lock, flags);
1796 ess_update_ptr(s);
1797 spin_unlock_irqrestore(&s->lock, flags);
1798 #endif
1799 while (count > 0) {
1800 spin_lock_irqsave(&s->lock, flags);
1801 swptr = s->dma_adc.swptr;
1802 cnt = s->dma_adc.dmasize-swptr;
1803 if (s->dma_adc.count < cnt)
1804 cnt = s->dma_adc.count;
1805 spin_unlock_irqrestore(&s->lock, flags);
1806 if (cnt > count)
1807 cnt = count;
1808 if (cnt <= 0) {
1809 start_adc(s);
1810 if (file->f_flags & O_NONBLOCK)
1811 return ret ? ret : -EAGAIN;
1812 if (!interruptible_sleep_on_timeout(&s->dma_adc.wait, HZ)) {
1813 printk(KERN_DEBUG "maestro: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1814 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1815 s->dma_adc.hwptr, s->dma_adc.swptr);
1816 stop_adc(s);
1817 spin_lock_irqsave(&s->lock, flags);
1818 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1819 /* program enhanced mode registers */
1820 /* FILL ME */
1821 /* wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
1822 wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1); */
1823 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1824 spin_unlock_irqrestore(&s->lock, flags);
1825 }
1826 if (signal_pending(current))
1827 return ret ? ret : -ERESTARTSYS;
1828 continue;
1829 }
1830 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt))
1831 return ret ? ret : -EFAULT;
1832 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1833 spin_lock_irqsave(&s->lock, flags);
1834 s->dma_adc.swptr = swptr;
1835 s->dma_adc.count -= cnt;
1836 spin_unlock_irqrestore(&s->lock, flags);
1837 count -= cnt;
1838 buffer += cnt;
1839 ret += cnt;
1840 start_adc(s);
1841 }
1842
1843 return ret;
1844 }
1845
1846 /* god this is gross..*/
1847 int split_stereo(unsigned char *real_buffer,unsigned char *tmp_buffer, int offset,
1848 int count, int bufsize, int mode)
1849 {
1850 /* oh, bother. stereo decoding APU's don't work in 16bit so we
1851 use dual linear decoders. which means we have to hack up stereo
1852 buffer's we're given. yuck. */
1853
1854 unsigned char *so,*left,*right;
1855 int i;
1856
1857 so = tmp_buffer;
1858 left = real_buffer + offset;
1859 right = real_buffer + bufsize/2 + offset;
1860
1861 M_printk("writing %d to %p and %p from %p:%d bufs: %d\n",count/2, left,right,real_buffer,offset,bufsize);
1862
1863 if(mode & ESS_CFMT_16BIT) {
1864 for(i=count/4; i ; i--) {
1865 *(right++) = (*(so+2));
1866 *(right++) = (*(so+3));
1867 *(left++) = (*so);
1868 *(left++) = (*(so+1));
1869 so+=4;
1870 }
1871 } else {
1872 for(i=count/2; i ; i--) {
1873 *(right++) = (*(so+1));
1874 *(left++) = (*so);
1875 so+=2;
1876 }
1877 }
1878
1879 return 0;
1880 }
1881
1882 static ssize_t ess_write(struct file *file, const char *buffer, size_t count, loff_t *ppos)
1883 {
1884 struct ess_state *s = (struct ess_state *)file->private_data;
1885 ssize_t ret;
1886 unsigned long flags;
1887 unsigned swptr;
1888 unsigned char *splitbuf = NULL;
1889 int cnt;
1890
1891 /* printk("maestro: ess_write: count %d\n", count);*/
1892
1893 VALIDATE_STATE(s);
1894 if (ppos != &file->f_pos)
1895 return -ESPIPE;
1896 if (s->dma_dac.mapped)
1897 return -ENXIO;
1898 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1899 return ret;
1900 if (!access_ok(VERIFY_READ, buffer, count))
1901 return -EFAULT;
1902 /* XXX be more clever than this.. */
1903 if (!(splitbuf = kmalloc(count,GFP_KERNEL)))
1904 return -ENOMEM;
1905 ret = 0;
1906 #if 0
1907 spin_lock_irqsave(&s->lock, flags);
1908 ess_update_ptr(s);
1909 spin_unlock_irqrestore(&s->lock, flags);
1910 #endif
1911 while (count > 0) {
1912 spin_lock_irqsave(&s->lock, flags);
1913
1914 if (s->dma_dac.count < 0) {
1915 s->dma_dac.count = 0;
1916 s->dma_dac.swptr = s->dma_dac.hwptr;
1917 }
1918 swptr = s->dma_dac.swptr;
1919
1920 if(s->fmt & ESS_CFMT_STEREO) {
1921 /* in stereo we have the 'dual' buffers.. */
1922 cnt = ((s->dma_dac.dmasize/2)-swptr)*2;
1923 } else {
1924 cnt = s->dma_dac.dmasize-swptr;
1925 }
1926 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1927 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1928
1929 spin_unlock_irqrestore(&s->lock, flags);
1930
1931 if (cnt > count)
1932 cnt = count;
1933
1934 /* our goofball stereo splitter can only deal in mults of 4 */
1935 if (cnt > 0)
1936 cnt &= ~3;
1937
1938 if (cnt <= 0) {
1939 /* buffer is full, wait for it to be played */
1940 start_dac(s);
1941 if (file->f_flags & O_NONBLOCK) {
1942 if(!ret) ret = -EAGAIN;
1943 goto return_free;
1944 }
1945 if (!interruptible_sleep_on_timeout(&s->dma_dac.wait, HZ)) {
1946 printk(KERN_DEBUG "maestro: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1947 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1948 s->dma_dac.hwptr, s->dma_dac.swptr);
1949 stop_dac(s);
1950 spin_lock_irqsave(&s->lock, flags);
1951 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1952 /* program enhanced mode registers */
1953 /* wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
1954 wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1); */
1955 /* FILL ME */
1956 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1957 spin_unlock_irqrestore(&s->lock, flags);
1958 }
1959 if (signal_pending(current)) {
1960 if (!ret) ret = -ERESTARTSYS;
1961 goto return_free;
1962 }
1963 continue;
1964 }
1965 if(s->fmt & ESS_CFMT_STEREO) {
1966 if (copy_from_user(splitbuf, buffer, cnt)) {
1967 if (!ret) ret = -EFAULT;
1968 goto return_free;
1969 }
1970 split_stereo(s->dma_dac.rawbuf,splitbuf,swptr,cnt,s->dma_dac.dmasize,s->fmt);
1971 } else {
1972 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1973 if (!ret) ret = -EFAULT;
1974 goto return_free;
1975 }
1976 }
1977
1978 if(s->fmt & ESS_CFMT_STEREO) {
1979 /* again with the weird pointer magic*/
1980 swptr = (swptr + (cnt/2)) % (s->dma_dac.dmasize/2);
1981 } else {
1982 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1983 }
1984 spin_lock_irqsave(&s->lock, flags);
1985 s->dma_dac.swptr = swptr;
1986 s->dma_dac.count += cnt;
1987 s->dma_dac.endcleared = 0;
1988 spin_unlock_irqrestore(&s->lock, flags);
1989 count -= cnt;
1990 buffer += cnt;
1991 ret += cnt;
1992 start_dac(s);
1993 }
1994 return_free:
1995 if (splitbuf) kfree(splitbuf);
1996 return ret;
1997 }
1998
1999 static unsigned int ess_poll(struct file *file, struct poll_table_struct *wait)
2000 {
2001 struct ess_state *s = (struct ess_state *)file->private_data;
2002 unsigned long flags;
2003 unsigned int mask = 0;
2004
2005 VALIDATE_STATE(s);
2006 if (file->f_mode & FMODE_WRITE)
2007 poll_wait(file, &s->dma_dac.wait, wait);
2008 if (file->f_mode & FMODE_READ)
2009 poll_wait(file, &s->dma_adc.wait, wait);
2010 spin_lock_irqsave(&s->lock, flags);
2011 ess_update_ptr(s);
2012 if (file->f_mode & FMODE_READ) {
2013 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
2014 mask |= POLLIN | POLLRDNORM;
2015 }
2016 if (file->f_mode & FMODE_WRITE) {
2017 if (s->dma_dac.mapped) {
2018 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
2019 mask |= POLLOUT | POLLWRNORM;
2020 } else {
2021 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
2022 mask |= POLLOUT | POLLWRNORM;
2023 }
2024 }
2025 spin_unlock_irqrestore(&s->lock, flags);
2026 return mask;
2027 }
2028
2029 /* this needs to be fixed to deal with the dualing apus/buffers */
2030 #if 0
2031 static int ess_mmap(struct file *file, struct vm_area_struct *vma)
2032 {
2033 struct ess_state *s = (struct ess_state *)file->private_data;
2034 struct dmabuf *db;
2035 int ret;
2036 unsigned long size;
2037
2038 VALIDATE_STATE(s);
2039 if (vma->vm_flags & VM_WRITE) {
2040 if ((ret = prog_dmabuf(s, 1)) != 0)
2041 return ret;
2042 db = &s->dma_dac;
2043 } else if (vma->vm_flags & VM_READ) {
2044 if ((ret = prog_dmabuf(s, 0)) != 0)
2045 return ret;
2046 db = &s->dma_adc;
2047 } else
2048 return -EINVAL;
2049 if (vma->vm_offset != 0)
2050 return -EINVAL;
2051 size = vma->vm_end - vma->vm_start;
2052 if (size > (PAGE_SIZE << db->buforder))
2053 return -EINVAL;
2054 if (remap_page_range(vma->vm_start, virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
2055 return -EAGAIN;
2056 db->mapped = 1;
2057 return 0;
2058 }
2059 #endif
2060
2061 static int ess_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2062 {
2063 struct ess_state *s = (struct ess_state *)file->private_data;
2064 unsigned long flags;
2065 audio_buf_info abinfo;
2066 count_info cinfo;
2067 int val, mapped, ret;
2068 unsigned char fmtm, fmtd;
2069
2070 /* printk("maestro: ess_ioctl: cmd %d\n", cmd);*/
2071
2072 VALIDATE_STATE(s);
2073 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2074 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2075 switch (cmd) {
2076 case OSS_GETVERSION:
2077 return put_user(SOUND_VERSION, (int *)arg);
2078
2079 case SNDCTL_DSP_SYNC:
2080 if (file->f_mode & FMODE_WRITE)
2081 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
2082 return 0;
2083
2084 case SNDCTL_DSP_SETDUPLEX:
2085 return 0;
2086
2087 case SNDCTL_DSP_GETCAPS:
2088 return put_user(0/*DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP*/, (int *)arg);
2089
2090 case SNDCTL_DSP_RESET:
2091 if (file->f_mode & FMODE_WRITE) {
2092 stop_dac(s);
2093 synchronize_irq();
2094 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
2095 }
2096 if (file->f_mode & FMODE_READ) {
2097 stop_adc(s);
2098 synchronize_irq();
2099 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
2100 }
2101 return 0;
2102
2103 case SNDCTL_DSP_SPEED:
2104 get_user_ret(val, (int *)arg, -EFAULT);
2105 if (val >= 0) {
2106 if (file->f_mode & FMODE_READ) {
2107 stop_adc(s);
2108 s->dma_adc.ready = 0;
2109 set_adc_rate(s, val);
2110 }
2111 if (file->f_mode & FMODE_WRITE) {
2112 stop_dac(s);
2113 s->dma_dac.ready = 0;
2114 set_dac_rate(s, val);
2115 }
2116 }
2117 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2118
2119 case SNDCTL_DSP_STEREO:
2120 get_user_ret(val, (int *)arg, -EFAULT);
2121 fmtd = 0;
2122 fmtm = ~0;
2123 if (file->f_mode & FMODE_READ) {
2124 stop_adc(s);
2125 s->dma_adc.ready = 0;
2126 if (val)
2127 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_CSHIFT;
2128 else
2129 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_CSHIFT);
2130 }
2131 if (file->f_mode & FMODE_WRITE) {
2132 stop_dac(s);
2133 s->dma_dac.ready = 0;
2134 if (val)
2135 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_ASHIFT;
2136 else
2137 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_ASHIFT);
2138 }
2139 set_fmt(s, fmtm, fmtd);
2140 return 0;
2141
2142 case SNDCTL_DSP_CHANNELS:
2143 get_user_ret(val, (int *)arg, -EFAULT);
2144 if (val != 0) {
2145 fmtd = 0;
2146 fmtm = ~0;
2147 if (file->f_mode & FMODE_READ) {
2148 stop_adc(s);
2149 s->dma_adc.ready = 0;
2150 if (val >= 2)
2151 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_CSHIFT;
2152 else
2153 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_CSHIFT);
2154 }
2155 if (file->f_mode & FMODE_WRITE) {
2156 stop_dac(s);
2157 s->dma_dac.ready = 0;
2158 if (val >= 2)
2159 fmtd |= ESS_CFMT_STEREO << ESS_CFMT_ASHIFT;
2160 else
2161 fmtm &= ~(ESS_CFMT_STEREO << ESS_CFMT_ASHIFT);
2162 }
2163 set_fmt(s, fmtm, fmtd);
2164 }
2165 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_STEREO << ESS_CFMT_CSHIFT)
2166 : (ESS_CFMT_STEREO << ESS_CFMT_ASHIFT))) ? 2 : 1, (int *)arg);
2167
2168 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
2169 return put_user(AFMT_S8|AFMT_S16_LE, (int *)arg);
2170
2171 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
2172 get_user_ret(val, (int *)arg, -EFAULT);
2173 if (val != AFMT_QUERY) {
2174 fmtd = 0;
2175 fmtm = ~0;
2176 if (file->f_mode & FMODE_READ) {
2177 stop_adc(s);
2178 s->dma_adc.ready = 0;
2179 if (val == AFMT_S16_LE)
2180 fmtd |= ESS_CFMT_16BIT << ESS_CFMT_CSHIFT;
2181 else
2182 fmtm &= ~(ESS_CFMT_16BIT << ESS_CFMT_CSHIFT);
2183 }
2184 if (file->f_mode & FMODE_WRITE) {
2185 stop_dac(s);
2186 s->dma_dac.ready = 0;
2187 if (val == AFMT_S16_LE)
2188 fmtd |= ESS_CFMT_16BIT << ESS_CFMT_ASHIFT;
2189 else
2190 fmtm &= ~(ESS_CFMT_16BIT << ESS_CFMT_ASHIFT);
2191 }
2192 set_fmt(s, fmtm, fmtd);
2193 }
2194 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ?
2195 (ESS_CFMT_16BIT << ESS_CFMT_CSHIFT)
2196 : (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT))) ?
2197 AFMT_S16_LE :
2198 AFMT_S8,
2199 (int *)arg);
2200
2201 case SNDCTL_DSP_POST:
2202 return 0;
2203
2204 case SNDCTL_DSP_GETTRIGGER:
2205 val = 0;
2206 if (file->f_mode & FMODE_READ && s->enable & ESS_ENABLE_RE)
2207 val |= PCM_ENABLE_INPUT;
2208 if (file->f_mode & FMODE_WRITE && s->enable & ESS_ENABLE_PE)
2209 val |= PCM_ENABLE_OUTPUT;
2210 return put_user(val, (int *)arg);
2211
2212 case SNDCTL_DSP_SETTRIGGER:
2213 get_user_ret(val, (int *)arg, -EFAULT);
2214 if (file->f_mode & FMODE_READ) {
2215 if (val & PCM_ENABLE_INPUT) {
2216 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
2217 return ret;
2218 start_adc(s);
2219 } else
2220 stop_adc(s);
2221 }
2222 if (file->f_mode & FMODE_WRITE) {
2223 if (val & PCM_ENABLE_OUTPUT) {
2224 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
2225 return ret;
2226 start_dac(s);
2227 } else
2228 stop_dac(s);
2229 }
2230 return 0;
2231
2232 case SNDCTL_DSP_GETOSPACE:
2233 if (!(file->f_mode & FMODE_WRITE))
2234 return -EINVAL;
2235 if (!(s->enable & ESS_ENABLE_PE) && (val = prog_dmabuf(s, 0)) != 0)
2236 return val;
2237 spin_lock_irqsave(&s->lock, flags);
2238 ess_update_ptr(s);
2239 abinfo.fragsize = s->dma_dac.fragsize;
2240 abinfo.bytes = s->dma_dac.dmasize - s->dma_dac.count;
2241 abinfo.fragstotal = s->dma_dac.numfrag;
2242 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2243 spin_unlock_irqrestore(&s->lock, flags);
2244 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2245
2246 case SNDCTL_DSP_GETISPACE:
2247 if (!(file->f_mode & FMODE_READ))
2248 return -EINVAL;
2249 if (!(s->enable & ESS_ENABLE_RE) && (val = prog_dmabuf(s, 1)) != 0)
2250 return val;
2251 spin_lock_irqsave(&s->lock, flags);
2252 ess_update_ptr(s);
2253 abinfo.fragsize = s->dma_adc.fragsize;
2254 abinfo.bytes = s->dma_adc.count;
2255 abinfo.fragstotal = s->dma_adc.numfrag;
2256 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
2257 spin_unlock_irqrestore(&s->lock, flags);
2258 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
2259
2260 case SNDCTL_DSP_NONBLOCK:
2261 file->f_flags |= O_NONBLOCK;
2262 return 0;
2263
2264 case SNDCTL_DSP_GETODELAY:
2265 if (!(file->f_mode & FMODE_WRITE))
2266 return -EINVAL;
2267 spin_lock_irqsave(&s->lock, flags);
2268 ess_update_ptr(s);
2269 val = s->dma_dac.count;
2270 spin_unlock_irqrestore(&s->lock, flags);
2271 return put_user(val, (int *)arg);
2272
2273 case SNDCTL_DSP_GETIPTR:
2274 if (!(file->f_mode & FMODE_READ))
2275 return -EINVAL;
2276 spin_lock_irqsave(&s->lock, flags);
2277 ess_update_ptr(s);
2278 cinfo.bytes = s->dma_adc.total_bytes;
2279 cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
2280 cinfo.ptr = s->dma_adc.hwptr;
2281 if (s->dma_adc.mapped)
2282 s->dma_adc.count &= s->dma_adc.fragsize-1;
2283 spin_unlock_irqrestore(&s->lock, flags);
2284 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2285
2286 case SNDCTL_DSP_GETOPTR:
2287 if (!(file->f_mode & FMODE_WRITE))
2288 return -EINVAL;
2289 spin_lock_irqsave(&s->lock, flags);
2290 ess_update_ptr(s);
2291 cinfo.bytes = s->dma_dac.total_bytes;
2292 cinfo.blocks = s->dma_dac.count >> s->dma_dac.fragshift;
2293 cinfo.ptr = s->dma_dac.hwptr;
2294 if (s->dma_dac.mapped)
2295 s->dma_dac.count &= s->dma_dac.fragsize-1;
2296 spin_unlock_irqrestore(&s->lock, flags);
2297 return copy_to_user((void *)arg, &cinfo, sizeof(cinfo));
2298
2299 case SNDCTL_DSP_GETBLKSIZE:
2300 if (file->f_mode & FMODE_WRITE) {
2301 if ((val = prog_dmabuf(s, 0)))
2302 return val;
2303 return put_user(s->dma_dac.fragsize, (int *)arg);
2304 }
2305 if ((val = prog_dmabuf(s, 1)))
2306 return val;
2307 return put_user(s->dma_adc.fragsize, (int *)arg);
2308
2309 case SNDCTL_DSP_SETFRAGMENT:
2310 get_user_ret(val, (int *)arg, -EFAULT);
2311 if (file->f_mode & FMODE_READ) {
2312 s->dma_adc.ossfragshift = val & 0xffff;
2313 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
2314 if (s->dma_adc.ossfragshift < 4)
2315 s->dma_adc.ossfragshift = 4;
2316 if (s->dma_adc.ossfragshift > 15)
2317 s->dma_adc.ossfragshift = 15;
2318 if (s->dma_adc.ossmaxfrags < 4)
2319 s->dma_adc.ossmaxfrags = 4;
2320 }
2321 if (file->f_mode & FMODE_WRITE) {
2322 s->dma_dac.ossfragshift = val & 0xffff;
2323 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
2324 if (s->dma_dac.ossfragshift < 4)
2325 s->dma_dac.ossfragshift = 4;
2326 if (s->dma_dac.ossfragshift > 15)
2327 s->dma_dac.ossfragshift = 15;
2328 if (s->dma_dac.ossmaxfrags < 4)
2329 s->dma_dac.ossmaxfrags = 4;
2330 }
2331 return 0;
2332
2333 case SNDCTL_DSP_SUBDIVIDE:
2334 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
2335 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
2336 return -EINVAL;
2337 get_user_ret(val, (int *)arg, -EFAULT);
2338 if (val != 1 && val != 2 && val != 4)
2339 return -EINVAL;
2340 if (file->f_mode & FMODE_READ)
2341 s->dma_adc.subdivision = val;
2342 if (file->f_mode & FMODE_WRITE)
2343 s->dma_dac.subdivision = val;
2344 return 0;
2345
2346 case SOUND_PCM_READ_RATE:
2347 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int *)arg);
2348
2349 case SOUND_PCM_READ_CHANNELS:
2350 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_STEREO << ESS_CFMT_CSHIFT)
2351 : (ESS_CFMT_STEREO << ESS_CFMT_ASHIFT))) ? 2 : 1, (int *)arg);
2352
2353 case SOUND_PCM_READ_BITS:
2354 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (ESS_CFMT_16BIT << ESS_CFMT_CSHIFT)
2355 : (ESS_CFMT_16BIT << ESS_CFMT_ASHIFT))) ? 16 : 8, (int *)arg);
2356
2357 case SOUND_PCM_WRITE_FILTER:
2358 case SNDCTL_DSP_SETSYNCRO:
2359 case SOUND_PCM_READ_FILTER:
2360 return -EINVAL;
2361
2362 }
2363 return -EINVAL;
2364 }
2365
2366 static int ess_open(struct inode *inode, struct file *file)
2367 {
2368 int minor = MINOR(inode->i_rdev);
2369 struct ess_card *c = devs;
2370 struct ess_state *s = NULL, *sp;
2371 int i;
2372 unsigned char fmtm = ~0, fmts = 0;
2373
2374 /*
2375 * Scan the cards and find the channel. We only
2376 * do this at open time so it is ok
2377 */
2378
2379 while (c!=NULL)
2380 {
2381 for(i=0;i<8;i++)
2382 {
2383 sp=&c->channels[i];
2384 if(sp->dev_audio < 0)
2385 continue;
2386 if((sp->dev_audio ^ minor) & ~0xf)
2387 continue;
2388 s=sp;
2389 }
2390 c=c->next;
2391 }
2392
2393 if (!s)
2394 return -ENODEV;
2395
2396 VALIDATE_STATE(s);
2397 file->private_data = s;
2398 /* wait for device to become free */
2399 down(&s->open_sem);
2400 while (s->open_mode & file->f_mode) {
2401 if (file->f_flags & O_NONBLOCK) {
2402 up(&s->open_sem);
2403 return -EWOULDBLOCK;
2404 }
2405 up(&s->open_sem);
2406 interruptible_sleep_on(&s->open_wait);
2407 if (signal_pending(current))
2408 return -ERESTARTSYS;
2409 down(&s->open_sem);
2410 }
2411 if (file->f_mode & FMODE_READ) {
2412 fmtm &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_CSHIFT);
2413 if ((minor & 0xf) == SND_DEV_DSP16)
2414 fmts |= ESS_CFMT_16BIT << ESS_CFMT_CSHIFT;
2415 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
2416 set_adc_rate(s, 8000);
2417 }
2418 if (file->f_mode & FMODE_WRITE) {
2419 fmtm &= ~((ESS_CFMT_STEREO | ESS_CFMT_16BIT) << ESS_CFMT_ASHIFT);
2420 if ((minor & 0xf) == SND_DEV_DSP16)
2421 fmts |= ESS_CFMT_16BIT << ESS_CFMT_ASHIFT;
2422 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
2423 set_dac_rate(s, 8000);
2424 }
2425 set_fmt(s, fmtm, fmts);
2426 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2427 start_bob(s);
2428 up(&s->open_sem);
2429 MOD_INC_USE_COUNT;
2430 return 0;
2431 }
2432
2433 static int ess_release(struct inode *inode, struct file *file)
2434 {
2435 struct ess_state *s = (struct ess_state *)file->private_data;
2436
2437 VALIDATE_STATE(s);
2438 if (file->f_mode & FMODE_WRITE)
2439 drain_dac(s, file->f_flags & O_NONBLOCK);
2440 down(&s->open_sem);
2441 if (file->f_mode & FMODE_WRITE) {
2442 stop_dac(s);
2443 dealloc_dmabuf(&s->dma_dac);
2444 }
2445 if (file->f_mode & FMODE_READ) {
2446 stop_adc(s);
2447 dealloc_dmabuf(&s->dma_adc);
2448 }
2449 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
2450 stop_bob(s);
2451 up(&s->open_sem);
2452 wake_up(&s->open_wait);
2453 MOD_DEC_USE_COUNT;
2454 return 0;
2455 }
2456
2457 static /*const*/ struct file_operations ess_audio_fops = {
2458 &ess_llseek,
2459 &ess_read,
2460 &ess_write,
2461 NULL, /* readdir */
2462 &ess_poll,
2463 &ess_ioctl,
2464 NULL, /* XXX &ess_mmap, */
2465 &ess_open,
2466 NULL, /* flush */
2467 &ess_release,
2468 NULL, /* fsync */
2469 NULL, /* fasync */
2470 NULL, /* check_media_change */
2471 NULL, /* revalidate */
2472 NULL, /* lock */
2473 };
2474
2475
2476 /* --------------------------------------------------------------------- */
2477
2478 /* XXX get rid of this
2479 * maximum number of devices
2480 */
2481 #define NR_DEVICE 4
2482
2483 /* --------------------------------------------------------------------- */
2484
2485 static int maestro_install(struct pci_dev *pcidev, int card_type, int index)
2486 {
2487 u16 w;
2488 /* u32 n;*/
2489 int iobase;
2490 int i;
2491 struct ess_card *card;
2492 struct ess_state *ess;
2493 int apu;
2494 int num = 0;
2495
2496 iobase = pcidev->resource[0].start;
2497
2498 if(check_region(iobase, 256))
2499 {
2500 printk(KERN_WARNING "maestro: can't allocate 256 bytes I/O at 0x%4.4x\n", iobase);
2501 return 0;
2502 }
2503
2504 card = kmalloc(sizeof(struct ess_card), GFP_KERNEL);
2505 if(card == NULL)
2506 {
2507 printk(KERN_WARNING "maestro: out of memory\n");
2508 return 0;
2509 }
2510
2511 memset(card, 0, sizeof(*card));
2512
2513 card->iobase = iobase;
2514 card->card_type = card_type;
2515 card->irq = pcidev->irq;
2516 card->next = devs;
2517 card->magic = ESS_CARD_MAGIC;
2518 devs = card;
2519
2520 /* init our 8 groups of 4 apus */
2521 for(i=0;i<8;i++)
2522 {
2523 struct ess_state *s=&card->channels[i];
2524
2525 s->card = card;
2526 init_waitqueue_head(&s->dma_adc.wait);
2527 init_waitqueue_head(&s->dma_dac.wait);
2528 init_waitqueue_head(&s->open_wait);
2529 init_MUTEX(&s->open_sem);
2530 s->magic = ESS_STATE_MAGIC;
2531
2532 s->apu[0] = 4*i;
2533 s->apu[1] = (4*i)+1;
2534 s->apu[2] = (4*i)+2;
2535 s->apu[3] = (4*i)+3;
2536
2537 if(s->dma_adc.ready || s->dma_dac.ready || s->dma_adc.rawbuf)
2538 printk("BOTCH!\n");
2539 /* register devices */
2540 if ((s->dev_audio = register_sound_dsp(&ess_audio_fops, -1)) < 0)
2541 break;
2542 }
2543
2544 num = i;
2545
2546 /* clear the rest if we ran out of slots to register */
2547 for(;i<8;i++)
2548 {
2549 struct ess_state *s=&card->channels[i];
2550 s->dev_audio = -1;
2551 }
2552
2553 ess = &card->channels[0];
2554
2555 /*
2556 * Ok card ready. Begin setup proper
2557 */
2558
2559 printk(KERN_INFO "maestro: Configuring %s at 0x%04X\n", card_names[card_type], iobase);
2560
2561 /*
2562 * Disable ACPI
2563 */
2564
2565 pci_write_config_dword(pcidev, 0x54, 0x00000000);
2566 pci_write_config_dword(pcidev, 0x56, 0x00000000);
2567
2568 /*
2569 * Use TDMA for now. TDMA works on all boards, so while its
2570 * not the most efficient its the simplest.
2571 */
2572
2573 pci_read_config_word(pcidev, 0x50, &w);
2574
2575 /* Clear DMA bits */
2576 w&=~(1<<10|1<<9|1<<8);
2577
2578 /* TDMA on */
2579 w|=(1<<8);
2580
2581 /* XXX do we care about these two ? */
2582 /*
2583 * MPU at 330
2584 */
2585
2586 w&=~((1<<4)|(1<<3));
2587
2588 /*
2589 * SB at 0x220
2590 */
2591
2592 w&=~(1<<2);
2593
2594 #if 0 /* huh? its sub decode.. */
2595
2596 /*
2597 * Reserved write as 0
2598 */
2599
2600 w&=~(1<<1);
2601 #endif
2602
2603 /*
2604 * Some of these are undocumented bits
2605 */
2606
2607 w&=~(1<<13)|(1<<14); /* PIC Snoop mode bits */
2608 w&=~(1<<11); /* Safeguard off */
2609 w|= (1<<7); /* Posted write */
2610 w|= (1<<6); /* ISA timing on */
2611 w&=~(1<<1); /* Subtractive decode off */
2612 /* XXX huh? claims to be reserved.. */
2613 w&=~(1<<5); /* Don't swap left/right */
2614
2615 pci_write_config_word(pcidev, 0x50, w);
2616
2617 pci_read_config_word(pcidev, 0x52, &w);
2618 w&=~(1<<15); /* Turn off internal clock multiplier */
2619 /* XXX how do we know which to use? */
2620 w&=~(1<<14); /* External clock */
2621
2622 w&=~(1<<7); /* HWV off */
2623 w&=~(1<<6); /* Debounce off */
2624 w&=~(1<<5); /* GPIO 4:5 */
2625 w&=~(1<<4); /* Disconnect from the CHI */
2626 w&=~(1<<3); /* IDMA off (undocumented) */
2627 w&=~(1<<2); /* MIDI fix off (undoc) */
2628 w&=~(1<<1); /* reserved, always write 0 */
2629 w&=~(1<<0); /* IRQ to ISA off (undoc) */
2630 pci_write_config_word(pcidev, 0x52, w);
2631
2632 /*
2633 * DDMA off
2634 */
2635
2636 pci_read_config_word(pcidev, 0x60, &w);
2637 w&=~(1<<0);
2638 pci_write_config_word(pcidev, 0x60, w);
2639
2640 /*
2641 * Legacy mode
2642 */
2643
2644 pci_read_config_word(pcidev, 0x40, &w);
2645 w|=(1<<15); /* legacy decode off */
2646 w&=~(1<<14); /* Disable SIRQ */
2647 w&=~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2648
2649 pci_write_config_word(pcidev, 0x40, w);
2650
2651 /* stake our claim on the iospace */
2652 request_region(iobase, 256, card_names[card_type]);
2653
2654 sound_reset(iobase);
2655 #if 0
2656
2657 /* reset the ring bus */
2658
2659 outw(inw(iobase + 0x36) & 0xdfff, iobase+0x36); /* disable */
2660 outw(0xC090, iobase+0x34);
2661 udelay(20);
2662 outw(inw(iobase + 0x36) |0x2000, iobase+0x36); /* enable */
2663 #endif
2664 /*
2665 * Ring Bus Setup
2666 */
2667
2668 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2669 outw(0xC090, iobase+0x34); /* direct sound, stereo */
2670 udelay(20);
2671 outw(0x3000, iobase+0x36); /* direct sound, stereo */
2672 udelay(20);
2673
2674
2675 /*
2676 * Reset the CODEC
2677 */
2678
2679 maestro_ac97_reset(iobase);
2680
2681 #if 0
2682 /*
2683 * Ring Bus Setup
2684 */
2685
2686 n=inl(iobase+0x34);
2687 n&=~0xF000;
2688 n|=12<<12; /* Direct Sound, Stereo */
2689 outl(n, iobase+0x34);
2690
2691 n=inl(iobase+0x34);
2692 n&=~0x0F00; /* Modem off */
2693 outl(n, iobase+0x34);
2694
2695 n=inl(iobase+0x34);
2696 n&=~0x00F0;
2697 n|=9<<4; /* DAC, Stereo */
2698 outl(n, iobase+0x34);
2699
2700 n=inl(iobase+0x34);
2701 n&=~0x000F; /* ASSP off */
2702 outl(n, iobase+0x34);
2703
2704
2705 n=inl(iobase+0x34);
2706 n|=(1<<29); /* Enable ring bus */
2707 outl(n, iobase+0x34);
2708
2709
2710 n=inl(iobase+0x34);
2711 n|=(1<<28); /* Enable serial bus */
2712 outl(n, iobase+0x34);
2713
2714 n=inl(iobase+0x34);
2715 n&=~0x00F00000; /* MIC off */
2716 outl(n, iobase+0x34);
2717
2718 n=inl(iobase+0x34);
2719 n&=~0x000F0000; /* I2S off */
2720 outl(n, iobase+0x34);
2721
2722 w=inw(iobase+0x18);
2723 w&=~(1<<7); /* ClkRun off */
2724 outw(w, iobase+0x18);
2725
2726 w=inw(iobase+0x18);
2727 w&=~(1<<6); /* Harpo off */
2728 outw(w, iobase+0x18);
2729
2730 w=inw(iobase+0x18);
2731 w&=~(1<<4); /* ASSP irq off */
2732 outw(w, iobase+0x18);
2733
2734 w=inw(iobase+0x18);
2735 w&=~(1<<3); /* ISDN irq off */
2736 outw(w, iobase+0x18);
2737
2738 w=inw(iobase+0x18);
2739 w|=(1<<2); /* Direct Sound IRQ on */
2740 outw(w, iobase+0x18);
2741
2742 w=inw(iobase+0x18);
2743 w&=~(1<<1); /* MPU401 IRQ off */
2744 outw(w, iobase+0x18);
2745
2746 w=inw(iobase+0x18);
2747 w|=(1<<0); /* SB IRQ on */
2748 outw(w, iobase+0x18);
2749 #endif
2750
2751
2752 #if 0
2753 /* asp crap */
2754 outb(0, iobase+0xA4);
2755 outb(3, iobase+0xA2);
2756 outb(0, iobase+0xA6);
2757 #endif
2758
2759 for(apu=0;apu<16;apu++)
2760 {
2761 /* Write 0 into the buffer area 0x1E0->1EF */
2762 outw(0x01E0+apu, 0x10+iobase);
2763 outw(0x0000, 0x12+iobase);
2764
2765 /*
2766 * The 1.10 test program seem to write 0 into the buffer area
2767 * 0x1D0-0x1DF too.
2768 */
2769 outw(0x01D0+apu, 0x10+iobase);
2770 outw(0x0000, 0x12+iobase);
2771 }
2772
2773 #if 1
2774 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2775 (wave_get_register(ess, IDR7_WAVE_ROMRAM)&0xFF00));
2776 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2777 wave_get_register(ess, IDR7_WAVE_ROMRAM)|0x100);
2778 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2779 wave_get_register(ess, IDR7_WAVE_ROMRAM)&~0x200);
2780 wave_set_register(ess, IDR7_WAVE_ROMRAM,
2781 wave_get_register(ess, IDR7_WAVE_ROMRAM)|~0x400);
2782 #else
2783 maestro_write(ess, IDR7_WAVE_ROMRAM,
2784 (maestro_read(ess, IDR7_WAVE_ROMRAM)&0xFF00));
2785 maestro_write(ess, IDR7_WAVE_ROMRAM,
2786 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x100);
2787 maestro_write(ess, IDR7_WAVE_ROMRAM,
2788 maestro_read(ess, IDR7_WAVE_ROMRAM)&~0x200);
2789 maestro_write(ess, IDR7_WAVE_ROMRAM,
2790 maestro_read(ess, IDR7_WAVE_ROMRAM)|0x400);
2791 #endif
2792
2793 maestro_write(ess, IDR2_CRAM_DATA, 0x0000);
2794 maestro_write(ess, 0x08, 0xB004);
2795 /* Now back to the DirectSound stuff */
2796 maestro_write(ess, 0x09, 0x001B);
2797 maestro_write(ess, 0x0A, 0x8000);
2798 maestro_write(ess, 0x0B, 0x3F37);
2799 maestro_write(ess, 0x0C, 0x0098);
2800
2801 maestro_write(ess, 0x0C,
2802 (maestro_read(ess, 0x0C)&~0xF000)|0x8000);
2803 maestro_write(ess, 0x0C,
2804 (maestro_read(ess, 0x0C)&~0x0F00)|0x0500);
2805
2806 maestro_write(ess, 0x0D, 0x7632);
2807
2808 /* Wave cache control on - test off, sg off,
2809 enable, enable extra chans 1Mb */
2810
2811 outw(inw(0x14+iobase)|(1<<8),0x14+iobase);
2812 outw(inw(0x14+iobase)&0xFE03,0x14+iobase);
2813 outw((inw(0x14+iobase)&0xFFFC), 0x14+iobase);
2814 outw(inw(0x14+iobase)|(1<<7),0x14+iobase);
2815
2816 outw(0xA1A0, 0x14+iobase); /* 0300 ? */
2817
2818 if(maestro_ac97_get(iobase, 0x00)==0x0080)
2819 {
2820 maestro_pt101_init(iobase);
2821 }
2822 else
2823 {
2824 maestro_ac97_init(iobase);
2825 card->mix.supported_mixers = AC97_SUPPORTED_MASK;
2826 card->mix.stereo_mixers = AC97_STEREO_MASK;
2827 card->mix.record_sources = AC97_RECORD_MASK;
2828 card->mix.read_mixer = ac97_read_mixer;
2829 card->mix.write_mixer = ac97_write_mixer;
2830 card->mix.recmask_io = ac97_recmask_io;
2831
2832 if ((card->dev_mixer = register_sound_mixer(&ess_mixer_fops, -1)) < 0)
2833 printk("maestro: couldn't register mixer!\n");
2834 }
2835
2836 /* Now clear the channel data */
2837 for(apu=0;apu<64;apu++)
2838 {
2839 for(w=0;w<0x0E;w++)
2840 apu_set_register(ess, apu|ESS_CHAN_HARD, w, 0);
2841 }
2842
2843 if(request_irq(card->irq, ess_interrupt, SA_SHIRQ, card_names[card_type], card))
2844 {
2845 printk(KERN_ERR "maestro: unable to allocate irq %d,\n", card->irq);
2846 unregister_sound_mixer(card->dev_mixer);
2847 for(i=0;i<8;i++)
2848 {
2849 struct ess_state *s = &card->channels[i];
2850 if(s->dev_audio != -1)
2851 unregister_sound_dsp(s->dev_audio);
2852 }
2853 release_region(card->iobase, 256);
2854 kfree(card);
2855 return 0;
2856 }
2857
2858 printk("maestro: %d channels configured.\n", num);
2859 return 1;
2860 }
2861
2862 #ifdef MODULE
2863
2864 int __init init_module(void)
2865 #else
2866 int __init init_maestro(void)
2867 #endif
2868 {
2869 struct pci_dev *pcidev = NULL;
2870 int index = 0;
2871
2872 if (!pci_present()) /* No PCI bus in this machine! */
2873 return -ENODEV;
2874 printk(KERN_INFO "maestro: version " DRIVER_VERSION " time " __TIME__ " " __DATE__ "\n");
2875
2876 pcidev = NULL;
2877
2878 /*
2879 * Find the ESS Maestro 2.
2880 */
2881
2882 while((pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1968, pcidev))!=NULL)
2883 {
2884 index+=maestro_install(pcidev, TYPE_MAESTRO2, index);
2885 if(index == NR_DEVICE)
2886 return index;
2887 }
2888
2889 /*
2890 * Find the ESS Maestro 2E
2891 */
2892
2893 while((pcidev = pci_find_device(PCI_VENDOR_ESS, PCI_DEVICE_ID_ESS_ESS1978, pcidev))!=NULL)
2894 {
2895 index+=maestro_install(pcidev, TYPE_MAESTRO2E, index);
2896 if(index == NR_DEVICE)
2897 return index;
2898 }
2899
2900 /*
2901 * ESS Maestro 1
2902 */
2903
2904 while((pcidev = pci_find_device(PCI_VENDOR_ESS_OLD, PCI_DEVICE_ID_ESS_ESS0100, pcidev))!=NULL)
2905 {
2906 index+=maestro_install(pcidev, TYPE_MAESTRO, index);
2907 if(index == NR_DEVICE)
2908 return index;
2909 }
2910 if(index==0)
2911 return -ENODEV;
2912 return 0;
2913 }
2914
2915 /* --------------------------------------------------------------------- */
2916
2917 #ifdef MODULE
2918
2919 MODULE_AUTHOR("Alan Cox <alan@redhat.com>");
2920 MODULE_DESCRIPTION("ESS Maestro Driver");
2921 #ifdef M_DEBUG
2922 MODULE_PARM(debug,"i");
2923 #endif
2924
2925 void cleanup_module(void)
2926 {
2927 struct ess_card *s;
2928
2929 while ((s = devs)) {
2930 int i;
2931 devs = devs->next;
2932 #ifndef ESS_HW_TIMER
2933 kill_bob(&s->channels[0]);
2934 #else
2935 stop_bob(&s->channels[0]);
2936 #endif
2937 free_irq(s->irq, s);
2938 unregister_sound_mixer(s->dev_mixer);
2939 for(i=0;i<8;i++)
2940 {
2941 struct ess_state *ess = &s->channels[i];
2942 if(ess->dev_audio != -1)
2943 unregister_sound_dsp(ess->dev_audio);
2944 }
2945 release_region(s->iobase, 256);
2946 kfree(s);
2947 }
2948 M_printk("maestro: unloading\n");
2949 }
2950
2951 #endif /* MODULE */
2952
2953 #if 0
2954 /*============================================================================
2955 * ex-code that we're not using anymore..
2956 *============================================================================
2957 */
2958
2959 /*
2960 * The ASSP is fortunately not double indexed
2961 */
2962
2963 static void assp_set_register(int ioaddr, u32 reg, u32 value)
2964 {
2965 unsigned long flags;
2966
2967 save_flags(flags);
2968 cli();
2969 outl(reg, ioaddr+0x80);
2970 outl(value, ioaddr+0x84);
2971 restore_flags(flags);
2972 }
2973
2974 static u32 assp_get_register(int ioaddr, u32 reg)
2975 {
2976 unsigned long flags;
2977 u32 value;
2978
2979 save_flags(flags);
2980 cli();
2981 outl(reg, ioaddr+0x80);
2982 value=inl(ioaddr+0x84);
2983 restore_flags(flags);
2984
2985 return value;
2986 }
2987
2988 /* the ASP is basically a DSP that one can dma instructions
2989 into. it can do things like surround encoding or
2990 fm synth in sb emul mode. It is highly proprietary
2991 and the ESS dudes are none too excited about telling
2992 us about it. so screw it, we'll just turn it off and
2993 not bother with it. Its not needed for apu/dac work. */
2994
2995
2996 static void asp_load(int ioaddr, u16 l, u16 h, u16 *data, int len)
2997 {
2998 int i;
2999 outw(l, ioaddr+0x80);
3000 outw(h, ioaddr+0x82);
3001 for(i=0;i<len;i++)
3002 outw(*data++, ioaddr+0x84);
3003 }
3004
3005 static void asp_memset(int ioaddr, u16 l, u16 h, u16 v, int len)
3006 {
3007 int i;
3008 outw(l, ioaddr+0x80);
3009 outw(h, ioaddr+0x82);
3010 for(i=0;i<len;i++)
3011 outw(v, ioaddr+0x84);
3012 }
3013
3014 /*
3015 * Load a code table into the ASP.
3016 */
3017
3018 #define ASSP_LOAD_PROGRAM 0x02
3019 #define ASSP_LOAD_DATA 0x03
3020
3021 static void load_tables(int iobase)
3022 {
3023 outb(0x00, ESS_SETUP_A4+iobase); /* start ASSP programming */
3024
3025 asp_load(iobase, 0x0, ASSP_LOAD_PROGRAM, asp_block_0,
3026 sizeof(asp_block_0)/2);
3027
3028 asp_load(iobase, 0x0800, ASSP_LOAD_PROGRAM,
3029 asp_block_1, sizeof(asp_block_1)/2);
3030
3031 asp_memset(iobase, 0x1000, ASSP_LOAD_DATA, 0, 1024);
3032
3033 /*
3034 * At page 25 of the Maestro-2E data sheet, Table 7, there is a layout of the
3035 * ASSP memory mapping that describe the 0x2000-0x23FF as a data area.
3036 * The 1.10 version of the test code load 0x3B4 words of data into this area.
3037 * I have grabbed the data with hexdump and inserted them into this code.
3038 */
3039 asp_load(iobase, 0x2000, ASSP_LOAD_DATA, asp_block_4,
3040 sizeof(asp_block_4)/2);
3041
3042 asp_memset(iobase, 0x11BC, ASSP_LOAD_DATA, 0x18, 36);
3043
3044 asp_load(iobase, 0x13DC, ASSP_LOAD_DATA, asp_block_2,
3045 sizeof(asp_block_2)/2);
3046
3047 asp_load(iobase, 0x1300, ASSP_LOAD_DATA, asp_block_3,
3048 sizeof(asp_block_3)/2);
3049
3050 outb(0x41, ESS_SETUP_A4+iobase); /* stop programming and run ASSP */
3051 }
3052 /*
3053 * Do not use the main maestro_reset. it is known
3054 * to leave certain chips in an unstable state.
3055 * best to just reset the direct sound (apus) and
3056 * assp pieces seperately.
3057 */
3058
3059 static void maestro_reset(int ioaddr)
3060 {
3061 outw(0x8000, 0x18+ioaddr);
3062 udelay(10);
3063 outw(0x0000, 0x18+ioaddr);
3064 udelay(10);
3065 }
3066 #endif
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