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Import 2.3.18pre1
[davej-history.git] / drivers / sound / ad1848.c
blobbaa0907711a068f53e0bc4c602d8da6682b7e668
1 /*
2 * sound/ad1848.c
3 *
4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
6 *
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
9 *
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
12 *
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
15 *
16 *
17 *
18 * Copyright (C) by Hannu Savolainen 1993-1997
19 *
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
22 * for more info.
23 *
24 *
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 *
30 * Status:
31 * Tested. Believed fully functional.
32 */
33
34 #include <linux/config.h>
35 #include <linux/module.h>
36 #include <linux/stddef.h>
37
38 #include "soundmodule.h"
39
40 #define DEB(x)
41 #define DEB1(x)
42 #include "sound_config.h"
43
44 #ifdef CONFIG_AD1848
45
46 #include "ad1848_mixer.h"
47
48 typedef struct
49 {
50 int base;
51 int irq;
52 int dma1, dma2;
53 int dual_dma; /* 1, when two DMA channels allocated */
54 unsigned char MCE_bit;
55 unsigned char saved_regs[32];
56 int debug_flag;
57
58 int audio_flags;
59 int record_dev, playback_dev;
60
61 int xfer_count;
62 int audio_mode;
63 int open_mode;
64 int intr_active;
65 char *chip_name, *name;
66 int model;
67 #define MD_1848 1
68 #define MD_4231 2
69 #define MD_4231A 3
70 #define MD_1845 4
71 #define MD_4232 5
72 #define MD_C930 6
73 #define MD_IWAVE 7
74 #define MD_4235 8 /* Crystal Audio CS4235 */
75
76 /* Mixer parameters */
77 int recmask;
78 int supported_devices, orig_devices;
79 int supported_rec_devices, orig_rec_devices;
80 int *levels;
81 short mixer_reroute[32];
82 int dev_no;
83 volatile unsigned long timer_ticks;
84 int timer_running;
85 int irq_ok;
86 mixer_ents *mix_devices;
87 int mixer_output_port;
88 } ad1848_info;
89
90 typedef struct ad1848_port_info
91 {
92 int open_mode;
93 int speed;
94 unsigned char speed_bits;
95 int channels;
96 int audio_format;
97 unsigned char format_bits;
98 }
99 ad1848_port_info;
100
101 static int nr_ad1848_devs = 0;
102 int deskpro_xl = 0;
103 #ifdef CONFIG_SOUND_SPRO
104 int soundpro = 1;
105 #else
106 int soundpro = 0;
107 #endif
108
109 static volatile char irq2dev[17] = {
110 -1, -1, -1, -1, -1, -1, -1, -1,
111 -1, -1, -1, -1, -1, -1, -1, -1, -1
112 };
113
114 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS) || defined(MODULE)
115
116 static int timer_installed = -1;
117
118 #endif
119
120 static int ad_format_mask[9 /*devc->model */ ] =
121 {
122 0,
123 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
124 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
125 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
126 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
127 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
128 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
129 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
130 AFMT_U8 | AFMT_S16_LE /* CS4235 */
131 };
132
133 static ad1848_info adev_info[MAX_AUDIO_DEV];
134
135 #define io_Index_Addr(d) ((d)->base)
136 #define io_Indexed_Data(d) ((d)->base+1)
137 #define io_Status(d) ((d)->base+2)
138 #define io_Polled_IO(d) ((d)->base+3)
139
140 static struct {
141 unsigned char flags;
142 #define CAP_F_TIMER 0x01
143 } capabilities [9 /*devc->model */ ] = {
144 {0}
145 ,{0} /* MD_1848 */
146 ,{CAP_F_TIMER} /* MD_4231 */
147 ,{CAP_F_TIMER} /* MD_4231A */
148 ,{CAP_F_TIMER} /* MD_1845 */
149 ,{CAP_F_TIMER} /* MD_4232 */
150 ,{0} /* MD_C930 */
151 ,{CAP_F_TIMER} /* MD_IWAVE */
152 ,{0} /* MD_4235 */
153 };
154
155 static int ad1848_open(int dev, int mode);
156 static void ad1848_close(int dev);
157 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
158 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
159 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
160 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
161 static void ad1848_halt(int dev);
162 static void ad1848_halt_input(int dev);
163 static void ad1848_halt_output(int dev);
164 static void ad1848_trigger(int dev, int bits);
165
166 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
167 static int ad1848_tmr_install(int dev);
168 static void ad1848_tmr_reprogram(int dev);
169
170 #endif
171
172 static int ad_read(ad1848_info * devc, int reg)
173 {
174 unsigned long flags;
175 int x;
176 int timeout = 900000;
177
178 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
179 timeout--;
180
181 save_flags(flags);
182 cli();
183 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
184 x = inb(io_Indexed_Data(devc));
185 /* printk("(%02x<-%02x) ", reg|devc->MCE_bit, x); */
186 restore_flags(flags);
187
188 return x;
189 }
190
191 static void ad_write(ad1848_info * devc, int reg, int data)
192 {
193 unsigned long flags;
194 int timeout = 900000;
195
196 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
197 timeout--;
198
199 save_flags(flags);
200 cli();
201 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
202 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
203 /* printk("(%02x->%02x) ", reg|devc->MCE_bit, data); */
204 restore_flags(flags);
205 }
206
207 static void wait_for_calibration(ad1848_info * devc)
208 {
209 int timeout = 0;
210
211 /*
212 * Wait until the auto calibration process has finished.
213 *
214 * 1) Wait until the chip becomes ready (reads don't return 0x80).
215 * 2) Wait until the ACI bit of I11 gets on and then off.
216 */
217
218 timeout = 100000;
219 while (timeout > 0 && inb(devc->base) == 0x80)
220 timeout--;
221 if (inb(devc->base) & 0x80)
222 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
223
224 timeout = 100;
225 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
226 timeout--;
227 if (!(ad_read(devc, 11) & 0x20))
228 return;
229
230 timeout = 80000;
231 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
232 timeout--;
233 if (ad_read(devc, 11) & 0x20)
234 if (devc->model != MD_1845)
235 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
236 }
237
238 static void ad_mute(ad1848_info * devc)
239 {
240 int i;
241 unsigned char prev;
242
243 /*
244 * Save old register settings and mute output channels
245 */
246
247 for (i = 6; i < 8; i++)
248 {
249 prev = devc->saved_regs[i] = ad_read(devc, i);
250 }
251
252 }
253
254 static void ad_unmute(ad1848_info * devc)
255 {
256 }
257
258 static void ad_enter_MCE(ad1848_info * devc)
259 {
260 unsigned long flags;
261 int timeout = 1000;
262 unsigned short prev;
263
264 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
265 timeout--;
266
267 save_flags(flags);
268 cli();
269
270 devc->MCE_bit = 0x40;
271 prev = inb(io_Index_Addr(devc));
272 if (prev & 0x40)
273 {
274 restore_flags(flags);
275 return;
276 }
277 outb((devc->MCE_bit), io_Index_Addr(devc));
278 restore_flags(flags);
279 }
280
281 static void ad_leave_MCE(ad1848_info * devc)
282 {
283 unsigned long flags;
284 unsigned char prev, acal;
285 int timeout = 1000;
286
287 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
288 timeout--;
289
290 save_flags(flags);
291 cli();
292
293 acal = ad_read(devc, 9);
294
295 devc->MCE_bit = 0x00;
296 prev = inb(io_Index_Addr(devc));
297 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
298
299 if ((prev & 0x40) == 0) /* Not in MCE mode */
300 {
301 restore_flags(flags);
302 return;
303 }
304 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
305 if (acal & 0x08) /* Auto calibration is enabled */
306 wait_for_calibration(devc);
307 restore_flags(flags);
308 }
309
310 static int ad1848_set_recmask(ad1848_info * devc, int mask)
311 {
312 unsigned char recdev;
313 int i, n;
314
315 mask &= devc->supported_rec_devices;
316
317 /* Rename the mixer bits if necessary */
318 for (i = 0; i < 32; i++)
319 {
320 if (devc->mixer_reroute[i] != i)
321 {
322 if (mask & (1 << i))
323 {
324 mask &= ~(1 << i);
325 mask |= (1 << devc->mixer_reroute[i]);
326 }
327 }
328 }
329
330 n = 0;
331 for (i = 0; i < 32; i++) /* Count selected device bits */
332 if (mask & (1 << i))
333 n++;
334
335 if (!soundpro) {
336 if (n == 0)
337 mask = SOUND_MASK_MIC;
338 else if (n != 1) { /* Too many devices selected */
339 mask &= ~devc->recmask; /* Filter out active settings */
340
341 n = 0;
342 for (i = 0; i < 32; i++) /* Count selected device bits */
343 if (mask & (1 << i))
344 n++;
345
346 if (n != 1)
347 mask = SOUND_MASK_MIC;
348 }
349 switch (mask) {
350 case SOUND_MASK_MIC:
351 recdev = 2;
352 break;
353
354 case SOUND_MASK_LINE:
355 case SOUND_MASK_LINE3:
356 recdev = 0;
357 break;
358
359 case SOUND_MASK_CD:
360 case SOUND_MASK_LINE1:
361 recdev = 1;
362 break;
363
364 case SOUND_MASK_IMIX:
365 recdev = 3;
366 break;
367
368 default:
369 mask = SOUND_MASK_MIC;
370 recdev = 2;
371 }
372
373 recdev <<= 6;
374 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
375 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
376 } else { /* soundpro */
377 unsigned char val;
378 int set_rec_bit;
379 int j;
380
381 for (i = 0; i < 32; i++) { /* For each bit */
382 if ((devc->supported_rec_devices & (1 << i)) == 0)
383 continue; /* Device not supported */
384
385 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
386 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
387 continue;
388
389 /*
390 * This is tricky:
391 * set_rec_bit becomes 1 if the corresponding bit in mask is set
392 * then it gets flipped if the polarity is inverse
393 */
394 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
395
396 val = ad_read(devc, devc->mix_devices[i][j].recreg);
397 val &= ~(1 << devc->mix_devices[i][j].recpos);
398 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
399 ad_write(devc, devc->mix_devices[i][j].recreg, val);
400 }
401 }
402 }
403
404 /* Rename the mixer bits back if necessary */
405 for (i = 0; i < 32; i++)
406 {
407 if (devc->mixer_reroute[i] != i)
408 {
409 if (mask & (1 << devc->mixer_reroute[i]))
410 {
411 mask &= ~(1 << devc->mixer_reroute[i]);
412 mask |= (1 << i);
413 }
414 }
415 }
416 devc->recmask = mask;
417 return mask;
418 }
419
420 static void change_bits(ad1848_info * devc, unsigned char *regval,
421 unsigned char *muteval, int dev, int chn, int newval)
422 {
423 unsigned char mask;
424 int shift;
425 int mute;
426 int mutemask;
427 int set_mute_bit;
428
429 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
430
431 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
432 newval = 100 - newval;
433
434 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
435 shift = devc->mix_devices[dev][chn].bitpos;
436
437 if (devc->mix_devices[dev][chn].mutepos == 8)
438 { /* if there is no mute bit */
439 mute = 0; /* No mute bit; do nothing special */
440 mutemask = ~0; /* No mute bit; do nothing special */
441 }
442 else
443 {
444 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
445 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
446 }
447
448 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
449 *regval &= ~(mask << shift); /* Clear bits */
450 *regval |= (newval & mask) << shift; /* Set new value */
451
452 *muteval &= mutemask;
453 *muteval |= mute;
454 }
455
456 static int ad1848_mixer_get(ad1848_info * devc, int dev)
457 {
458 if (!((1 << dev) & devc->supported_devices))
459 return -EINVAL;
460
461 dev = devc->mixer_reroute[dev];
462
463 return devc->levels[dev];
464 }
465
466 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
467 {
468 int regoffs, muteregoffs;
469 unsigned char val, muteval;
470
471 regoffs = devc->mix_devices[dev][channel].regno;
472 muteregoffs = devc->mix_devices[dev][channel].mutereg;
473 val = ad_read(devc, regoffs);
474
475 if (muteregoffs != regoffs) {
476 muteval = ad_read(devc, muteregoffs);
477 change_bits(devc, &val, &muteval, dev, channel, value);
478 }
479 else
480 change_bits(devc, &val, &val, dev, channel, value);
481
482 ad_write(devc, regoffs, val);
483 devc->saved_regs[regoffs] = val;
484 if (muteregoffs != regoffs) {
485 ad_write(devc, muteregoffs, muteval);
486 devc->saved_regs[muteregoffs] = muteval;
487 }
488 }
489
490 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
491 {
492 int left = value & 0x000000ff;
493 int right = (value & 0x0000ff00) >> 8;
494 int retvol;
495
496 if (dev > 31)
497 return -EINVAL;
498
499 if (!(devc->supported_devices & (1 << dev)))
500 return -EINVAL;
501
502 dev = devc->mixer_reroute[dev];
503
504 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
505 return -EINVAL;
506
507 if (left > 100)
508 left = 100;
509 if (right > 100)
510 right = 100;
511
512 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
513 right = left;
514
515 retvol = left | (right << 8);
516
517 /* Scale volumes */
518 left = mix_cvt[left];
519 right = mix_cvt[right];
520
521 devc->levels[dev] = retvol;
522
523 /*
524 * Set the left channel
525 */
526 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
527
528 /*
529 * Set the right channel
530 */
531 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
532 goto out;
533 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
534
535 out:
536 return retvol;
537 }
538
539 static void ad1848_mixer_reset(ad1848_info * devc)
540 {
541 int i;
542 char name[32];
543
544 devc->mix_devices = &(ad1848_mix_devices[0]);
545
546 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
547
548 for (i = 0; i < 32; i++)
549 devc->mixer_reroute[i] = i;
550
551 devc->supported_rec_devices = MODE1_REC_DEVICES;
552
553 switch (devc->model)
554 {
555 case MD_4231:
556 case MD_4231A:
557 case MD_1845:
558 devc->supported_devices = MODE2_MIXER_DEVICES;
559 break;
560
561 case MD_C930:
562 devc->supported_devices = C930_MIXER_DEVICES;
563 devc->mix_devices = &(c930_mix_devices[0]);
564 break;
565
566 case MD_IWAVE:
567 devc->supported_devices = MODE3_MIXER_DEVICES;
568 devc->mix_devices = &(iwave_mix_devices[0]);
569 break;
570
571 case MD_4232:
572 devc->supported_devices = MODE3_MIXER_DEVICES;
573 break;
574
575 case MD_1848:
576 if (soundpro) {
577 devc->supported_devices = SPRO_MIXER_DEVICES;
578 devc->supported_rec_devices = SPRO_REC_DEVICES;
579 devc->mix_devices = &(spro_mix_devices[0]);
580 break;
581 }
582
583 default:
584 devc->supported_devices = MODE1_MIXER_DEVICES;
585 }
586
587 devc->orig_devices = devc->supported_devices;
588 devc->orig_rec_devices = devc->supported_rec_devices;
589
590 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
591
592 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
593 {
594 if (devc->supported_devices & (1 << i))
595 ad1848_mixer_set(devc, i, devc->levels[i]);
596 }
597
598 ad1848_set_recmask(devc, SOUND_MASK_MIC);
599
600 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
601
602 if (!soundpro) {
603 if (devc->mixer_output_port & AUDIO_SPEAKER)
604 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
605 else
606 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
607 } else {
608 /*
609 * From the "wouldn't it be nice if the mixer API had (better)
610 * support for custom stuff" category
611 */
612 /* Enable surround mode and SB16 mixer */
613 ad_write(devc, 16, 0x60);
614 }
615 }
616
617 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, caddr_t arg)
618 {
619 ad1848_info *devc = mixer_devs[dev]->devc;
620 int val;
621
622 if (cmd == SOUND_MIXER_PRIVATE1)
623 {
624 if (get_user(val, (int *)arg))
625 return -EFAULT;
626
627 if (val != 0xffff)
628 {
629 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
630 devc->mixer_output_port = val;
631 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
632 devc->mixer_output_port = val;
633 if (val & AUDIO_SPEAKER)
634 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
635 else
636 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
637 }
638 val = devc->mixer_output_port;
639 return put_user(val, (int *)arg);
640 }
641 if (cmd == SOUND_MIXER_PRIVATE2)
642 {
643 if (get_user(val, (int *)arg))
644 return -EFAULT;
645 return(ad1848_control(AD1848_MIXER_REROUTE, val));
646 }
647 if (((cmd >> 8) & 0xff) == 'M')
648 {
649 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
650 {
651 switch (cmd & 0xff)
652 {
653 case SOUND_MIXER_RECSRC:
654 if (get_user(val, (int *)arg))
655 return -EFAULT;
656 val = ad1848_set_recmask(devc, val);
657 break;
658
659 default:
660 if (get_user(val, (int *)arg))
661 return -EFAULT;
662 val = ad1848_mixer_set(devc, cmd & 0xff, val);
663 break;
664 }
665 return put_user(val, (int *)arg);
666 }
667 else
668 {
669 switch (cmd & 0xff)
670 {
671 /*
672 * Return parameters
673 */
674
675 case SOUND_MIXER_RECSRC:
676 val = devc->recmask;
677 break;
678
679 case SOUND_MIXER_DEVMASK:
680 val = devc->supported_devices;
681 break;
682
683 case SOUND_MIXER_STEREODEVS:
684 val = devc->supported_devices;
685 if (devc->model != MD_C930)
686 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
687 break;
688
689 case SOUND_MIXER_RECMASK:
690 val = devc->supported_rec_devices;
691 break;
692
693 case SOUND_MIXER_CAPS:
694 val=SOUND_CAP_EXCL_INPUT;
695 break;
696
697 default:
698 val = ad1848_mixer_get(devc, cmd & 0xff);
699 break;
700 }
701 return put_user(val, (int *)arg);
702 }
703 }
704 else
705 return -EINVAL;
706 }
707
708 static int ad1848_set_speed(int dev, int arg)
709 {
710 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
711 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
712
713 /*
714 * The sampling speed is encoded in the least significant nibble of I8. The
715 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
716 * three bits select the divisor (indirectly):
717 *
718 * The available speeds are in the following table. Keep the speeds in
719 * the increasing order.
720 */
721 typedef struct
722 {
723 int speed;
724 unsigned char bits;
725 }
726 speed_struct;
727
728 static speed_struct speed_table[] =
729 {
730 {5510, (0 << 1) | 1},
731 {5510, (0 << 1) | 1},
732 {6620, (7 << 1) | 1},
733 {8000, (0 << 1) | 0},
734 {9600, (7 << 1) | 0},
735 {11025, (1 << 1) | 1},
736 {16000, (1 << 1) | 0},
737 {18900, (2 << 1) | 1},
738 {22050, (3 << 1) | 1},
739 {27420, (2 << 1) | 0},
740 {32000, (3 << 1) | 0},
741 {33075, (6 << 1) | 1},
742 {37800, (4 << 1) | 1},
743 {44100, (5 << 1) | 1},
744 {48000, (6 << 1) | 0}
745 };
746
747 int i, n, selected = -1;
748
749 n = sizeof(speed_table) / sizeof(speed_struct);
750
751 if (arg <= 0)
752 return portc->speed;
753
754 if (devc->model == MD_1845) /* AD1845 has different timer than others */
755 {
756 if (arg < 4000)
757 arg = 4000;
758 if (arg > 50000)
759 arg = 50000;
760
761 portc->speed = arg;
762 portc->speed_bits = speed_table[3].bits;
763 return portc->speed;
764 }
765 if (arg < speed_table[0].speed)
766 selected = 0;
767 if (arg > speed_table[n - 1].speed)
768 selected = n - 1;
769
770 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
771 {
772 if (speed_table[i].speed == arg)
773 selected = i;
774 else if (speed_table[i].speed > arg)
775 {
776 int diff1, diff2;
777
778 diff1 = arg - speed_table[i - 1].speed;
779 diff2 = speed_table[i].speed - arg;
780
781 if (diff1 < diff2)
782 selected = i - 1;
783 else
784 selected = i;
785 }
786 }
787 if (selected == -1)
788 {
789 printk(KERN_WARNING "ad1848: Can't find speed???\n");
790 selected = 3;
791 }
792 portc->speed = speed_table[selected].speed;
793 portc->speed_bits = speed_table[selected].bits;
794 return portc->speed;
795 }
796
797 static short ad1848_set_channels(int dev, short arg)
798 {
799 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
800
801 if (arg != 1 && arg != 2)
802 return portc->channels;
803
804 portc->channels = arg;
805 return arg;
806 }
807
808 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
809 {
810 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
811 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
812
813 static struct format_tbl
814 {
815 int format;
816 unsigned char bits;
817 }
818 format2bits[] =
819 {
820 {
821 0, 0
822 }
823 ,
824 {
825 AFMT_MU_LAW, 1
826 }
827 ,
828 {
829 AFMT_A_LAW, 3
830 }
831 ,
832 {
833 AFMT_IMA_ADPCM, 5
834 }
835 ,
836 {
837 AFMT_U8, 0
838 }
839 ,
840 {
841 AFMT_S16_LE, 2
842 }
843 ,
844 {
845 AFMT_S16_BE, 6
846 }
847 ,
848 {
849 AFMT_S8, 0
850 }
851 ,
852 {
853 AFMT_U16_LE, 0
854 }
855 ,
856 {
857 AFMT_U16_BE, 0
858 }
859 };
860 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
861
862 if (arg == 0)
863 return portc->audio_format;
864
865 if (!(arg & ad_format_mask[devc->model]))
866 arg = AFMT_U8;
867
868 portc->audio_format = arg;
869
870 for (i = 0; i < n; i++)
871 if (format2bits[i].format == arg)
872 {
873 if ((portc->format_bits = format2bits[i].bits) == 0)
874 return portc->audio_format = AFMT_U8; /* Was not supported */
875
876 return arg;
877 }
878 /* Still hanging here. Something must be terribly wrong */
879 portc->format_bits = 0;
880 return portc->audio_format = AFMT_U8;
881 }
882
883 static struct audio_driver ad1848_audio_driver =
884 {
885 ad1848_open,
886 ad1848_close,
887 ad1848_output_block,
888 ad1848_start_input,
889 NULL,
890 ad1848_prepare_for_input,
891 ad1848_prepare_for_output,
892 ad1848_halt,
893 NULL,
894 NULL,
895 ad1848_halt_input,
896 ad1848_halt_output,
897 ad1848_trigger,
898 ad1848_set_speed,
899 ad1848_set_bits,
900 ad1848_set_channels
901 };
902
903 static struct mixer_operations ad1848_mixer_operations =
904 {
905 "SOUNDPORT",
906 "AD1848/CS4248/CS4231",
907 ad1848_mixer_ioctl
908 };
909
910 static int ad1848_open(int dev, int mode)
911 {
912 ad1848_info *devc = NULL;
913 ad1848_port_info *portc;
914 unsigned long flags;
915
916 if (dev < 0 || dev >= num_audiodevs)
917 return -ENXIO;
918
919 devc = (ad1848_info *) audio_devs[dev]->devc;
920 portc = (ad1848_port_info *) audio_devs[dev]->portc;
921
922 save_flags(flags);
923 cli();
924 if (portc->open_mode || (devc->open_mode & mode))
925 {
926 restore_flags(flags);
927 return -EBUSY;
928 }
929 devc->dual_dma = 0;
930
931 if (audio_devs[dev]->flags & DMA_DUPLEX)
932 {
933 devc->dual_dma = 1;
934 }
935 devc->intr_active = 0;
936 devc->audio_mode = 0;
937 devc->open_mode |= mode;
938 portc->open_mode = mode;
939 ad1848_trigger(dev, 0);
940
941 if (mode & OPEN_READ)
942 devc->record_dev = dev;
943 if (mode & OPEN_WRITE)
944 devc->playback_dev = dev;
945 restore_flags(flags);
946 /*
947 * Mute output until the playback really starts. This decreases clicking (hope so).
948 */
949 ad_mute(devc);
950
951 return 0;
952 }
953
954 static void ad1848_close(int dev)
955 {
956 unsigned long flags;
957 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
958 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
959
960 DEB(printk("ad1848_close(void)\n"));
961
962 save_flags(flags);
963 cli();
964
965 devc->intr_active = 0;
966 ad1848_halt(dev);
967
968 devc->audio_mode = 0;
969 devc->open_mode &= ~portc->open_mode;
970 portc->open_mode = 0;
971
972 ad_unmute(devc);
973 restore_flags(flags);
974 }
975
976 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
977 {
978 unsigned long flags, cnt;
979 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
980 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
981
982 cnt = count;
983
984 if (portc->audio_format == AFMT_IMA_ADPCM)
985 {
986 cnt /= 4;
987 }
988 else
989 {
990 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
991 cnt >>= 1;
992 }
993 if (portc->channels > 1)
994 cnt >>= 1;
995 cnt--;
996
997 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
998 intrflag &&
999 cnt == devc->xfer_count)
1000 {
1001 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1002 devc->intr_active = 1;
1003 return; /*
1004 * Auto DMA mode on. No need to react
1005 */
1006 }
1007 save_flags(flags);
1008 cli();
1009
1010 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1011 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1012
1013 devc->xfer_count = cnt;
1014 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1015 devc->intr_active = 1;
1016 restore_flags(flags);
1017 }
1018
1019 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1020 {
1021 unsigned long flags, cnt;
1022 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1023 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1024
1025 cnt = count;
1026 if (portc->audio_format == AFMT_IMA_ADPCM)
1027 {
1028 cnt /= 4;
1029 }
1030 else
1031 {
1032 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1033 cnt >>= 1;
1034 }
1035 if (portc->channels > 1)
1036 cnt >>= 1;
1037 cnt--;
1038
1039 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1040 intrflag &&
1041 cnt == devc->xfer_count)
1042 {
1043 devc->audio_mode |= PCM_ENABLE_INPUT;
1044 devc->intr_active = 1;
1045 return; /*
1046 * Auto DMA mode on. No need to react
1047 */
1048 }
1049 save_flags(flags);
1050 cli();
1051
1052 if (devc->model == MD_1848)
1053 {
1054 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1055 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1056 }
1057 else
1058 {
1059 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1060 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1061 }
1062
1063 ad_unmute(devc);
1064
1065 devc->xfer_count = cnt;
1066 devc->audio_mode |= PCM_ENABLE_INPUT;
1067 devc->intr_active = 1;
1068 restore_flags(flags);
1069 }
1070
1071 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1072 {
1073 int timeout;
1074 unsigned char fs, old_fs, tmp = 0;
1075 unsigned long flags;
1076 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1077 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1078
1079 ad_mute(devc);
1080
1081 save_flags(flags);
1082 cli();
1083 fs = portc->speed_bits | (portc->format_bits << 5);
1084
1085 if (portc->channels > 1)
1086 fs |= 0x10;
1087
1088 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1089
1090 if (devc->model == MD_1845) /* Use alternate speed select registers */
1091 {
1092 fs &= 0xf0; /* Mask off the rate select bits */
1093
1094 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1095 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1096 }
1097 old_fs = ad_read(devc, 8);
1098
1099 if (devc->model == MD_4232)
1100 {
1101 tmp = ad_read(devc, 16);
1102 ad_write(devc, 16, tmp | 0x30);
1103 }
1104 if (devc->model == MD_IWAVE)
1105 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1106
1107 ad_write(devc, 8, fs);
1108
1109 /*
1110 * Write to I8 starts resynchronization. Wait until it completes.
1111 */
1112
1113 timeout = 0;
1114 while (timeout < 100 && inb(devc->base) != 0x80)
1115 timeout++;
1116 timeout = 0;
1117 while (timeout < 10000 && inb(devc->base) == 0x80)
1118 timeout++;
1119
1120 if (devc->model == MD_4232)
1121 ad_write(devc, 16, tmp & ~0x30);
1122
1123 ad_leave_MCE(devc); /*
1124 * Starts the calibration process.
1125 */
1126 restore_flags(flags);
1127 devc->xfer_count = 0;
1128
1129 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1130 if (dev == timer_installed && devc->timer_running)
1131 if ((fs & 0x01) != (old_fs & 0x01))
1132 {
1133 ad1848_tmr_reprogram(dev);
1134 }
1135 #endif
1136 ad1848_halt_output(dev);
1137 return 0;
1138 }
1139
1140 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1141 {
1142 int timeout;
1143 unsigned char fs, old_fs, tmp = 0;
1144 unsigned long flags;
1145 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1146 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1147
1148 if (devc->audio_mode)
1149 return 0;
1150
1151 save_flags(flags);
1152 cli();
1153 fs = portc->speed_bits | (portc->format_bits << 5);
1154
1155 if (portc->channels > 1)
1156 fs |= 0x10;
1157
1158 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1159
1160 if (devc->model == MD_1845) /* Use alternate speed select registers */
1161 {
1162 fs &= 0xf0; /* Mask off the rate select bits */
1163
1164 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1165 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1166 }
1167 if (devc->model == MD_4232)
1168 {
1169 tmp = ad_read(devc, 16);
1170 ad_write(devc, 16, tmp | 0x30);
1171 }
1172 if (devc->model == MD_IWAVE)
1173 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1174
1175 /*
1176 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1177 */
1178
1179 if (devc->model != MD_1848)
1180 {
1181 old_fs = ad_read(devc, 28);
1182 ad_write(devc, 28, fs);
1183
1184 /*
1185 * Write to I28 starts resynchronization. Wait until it completes.
1186 */
1187
1188 timeout = 0;
1189 while (timeout < 100 && inb(devc->base) != 0x80)
1190 timeout++;
1191
1192 timeout = 0;
1193 while (timeout < 10000 && inb(devc->base) == 0x80)
1194 timeout++;
1195
1196 if (devc->model != MD_1848 && devc->model != MD_1845)
1197 {
1198 /*
1199 * CS4231 compatible devices don't have separate sampling rate selection
1200 * register for recording an playback. The I8 register is shared so we have to
1201 * set the speed encoding bits of it too.
1202 */
1203 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1204
1205 ad_write(devc, 8, tmp);
1206 /*
1207 * Write to I8 starts resynchronization. Wait until it completes.
1208 */
1209 timeout = 0;
1210 while (timeout < 100 && inb(devc->base) != 0x80)
1211 timeout++;
1212
1213 timeout = 0;
1214 while (timeout < 10000 && inb(devc->base) == 0x80)
1215 timeout++;
1216 }
1217 }
1218 else
1219 { /* For AD1848 set I8. */
1220
1221 old_fs = ad_read(devc, 8);
1222 ad_write(devc, 8, fs);
1223 /*
1224 * Write to I8 starts resynchronization. Wait until it completes.
1225 */
1226 timeout = 0;
1227 while (timeout < 100 && inb(devc->base) != 0x80)
1228 timeout++;
1229 timeout = 0;
1230 while (timeout < 10000 && inb(devc->base) == 0x80)
1231 timeout++;
1232 }
1233
1234 if (devc->model == MD_4232)
1235 ad_write(devc, 16, tmp & ~0x30);
1236
1237 ad_leave_MCE(devc); /*
1238 * Starts the calibration process.
1239 */
1240 restore_flags(flags);
1241 devc->xfer_count = 0;
1242
1243 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1244 if (dev == timer_installed && devc->timer_running)
1245 {
1246 if ((fs & 0x01) != (old_fs & 0x01))
1247 {
1248 ad1848_tmr_reprogram(dev);
1249 }
1250 }
1251 #endif
1252 ad1848_halt_input(dev);
1253 return 0;
1254 }
1255
1256 static void ad1848_halt(int dev)
1257 {
1258 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1259 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1260
1261 unsigned char bits = ad_read(devc, 9);
1262
1263 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1264 ad1848_halt_output(dev);
1265
1266 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1267 ad1848_halt_input(dev);
1268 devc->audio_mode = 0;
1269 }
1270
1271 static void ad1848_halt_input(int dev)
1272 {
1273 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1274 unsigned long flags;
1275
1276 if (!(ad_read(devc, 9) & 0x02))
1277 return; /* Capture not enabled */
1278
1279 save_flags(flags);
1280 cli();
1281
1282 ad_mute(devc);
1283
1284 {
1285 int tmout;
1286
1287 if(!isa_dma_bridge_buggy)
1288 disable_dma(audio_devs[dev]->dmap_in->dma);
1289
1290 for (tmout = 0; tmout < 100000; tmout++)
1291 if (ad_read(devc, 11) & 0x10)
1292 break;
1293 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1294
1295 if(!isa_dma_bridge_buggy)
1296 enable_dma(audio_devs[dev]->dmap_in->dma);
1297 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1298 }
1299
1300 outb(0, io_Status(devc)); /* Clear interrupt status */
1301 outb(0, io_Status(devc)); /* Clear interrupt status */
1302
1303 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1304
1305 restore_flags(flags);
1306 }
1307
1308 static void ad1848_halt_output(int dev)
1309 {
1310 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1311 unsigned long flags;
1312
1313 if (!(ad_read(devc, 9) & 0x01))
1314 return; /* Playback not enabled */
1315
1316 save_flags(flags);
1317 cli();
1318
1319 ad_mute(devc);
1320 {
1321 int tmout;
1322
1323 if(!isa_dma_bridge_buggy)
1324 disable_dma(audio_devs[dev]->dmap_out->dma);
1325
1326 for (tmout = 0; tmout < 100000; tmout++)
1327 if (ad_read(devc, 11) & 0x10)
1328 break;
1329 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1330
1331 if(!isa_dma_bridge_buggy)
1332 enable_dma(audio_devs[dev]->dmap_out->dma);
1333
1334 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1335 }
1336
1337 outb((0), io_Status(devc)); /* Clear interrupt status */
1338 outb((0), io_Status(devc)); /* Clear interrupt status */
1339
1340 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1341
1342 restore_flags(flags);
1343 }
1344
1345 static void ad1848_trigger(int dev, int state)
1346 {
1347 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1348 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1349 unsigned long flags;
1350 unsigned char tmp, old;
1351
1352 save_flags(flags);
1353 cli();
1354 state &= devc->audio_mode;
1355
1356 tmp = old = ad_read(devc, 9);
1357
1358 if (portc->open_mode & OPEN_READ)
1359 {
1360 if (state & PCM_ENABLE_INPUT)
1361 tmp |= 0x02;
1362 else
1363 tmp &= ~0x02;
1364 }
1365 if (portc->open_mode & OPEN_WRITE)
1366 {
1367 if (state & PCM_ENABLE_OUTPUT)
1368 tmp |= 0x01;
1369 else
1370 tmp &= ~0x01;
1371 }
1372 /* ad_mute(devc); */
1373 if (tmp != old)
1374 {
1375 ad_write(devc, 9, tmp);
1376 ad_unmute(devc);
1377 }
1378 restore_flags(flags);
1379 }
1380
1381 static void ad1848_init_hw(ad1848_info * devc)
1382 {
1383 int i;
1384
1385 /*
1386 * Initial values for the indirect registers of CS4248/AD1848.
1387 */
1388 static int init_values[] =
1389 {
1390 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1391 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1392
1393 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1394 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1396 };
1397
1398
1399 for (i = 0; i < 16; i++)
1400 ad_write(devc, i, init_values[i]);
1401
1402
1403 ad_mute(devc); /* Initialize some variables */
1404 ad_unmute(devc); /* Leave it unmuted now */
1405
1406 if (devc->model > MD_1848)
1407 {
1408 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1409
1410 if (devc->model == MD_IWAVE)
1411 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1412
1413 for (i = 16; i < 32; i++)
1414 ad_write(devc, i, init_values[i]);
1415
1416 if (devc->model == MD_IWAVE)
1417 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1418 }
1419 if (devc->model > MD_1848)
1420 {
1421 if (devc->audio_flags & DMA_DUPLEX)
1422 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1423 else
1424 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1425
1426 if (devc->model == MD_1845)
1427 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1428
1429 if (devc->model == MD_IWAVE)
1430 { /* Some magic Interwave specific initialization */
1431 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1432 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1433 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1434 }
1435 }
1436 else
1437 {
1438 devc->audio_flags &= ~DMA_DUPLEX;
1439 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1440 if (soundpro)
1441 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1442 }
1443
1444 outb((0), io_Status(devc)); /* Clear pending interrupts */
1445
1446 /*
1447 * Toggle the MCE bit. It completes the initialization phase.
1448 */
1449
1450 ad_enter_MCE(devc); /* In case the bit was off */
1451 ad_leave_MCE(devc);
1452
1453 ad1848_mixer_reset(devc);
1454 }
1455
1456 int ad1848_detect(int io_base, int *ad_flags, int *osp)
1457 {
1458 unsigned char tmp;
1459 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1460 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1461 int optiC930 = 0; /* OPTi 82C930 flag */
1462 int interwave = 0;
1463 int ad1847_flag = 0;
1464 int cs4248_flag = 0;
1465
1466 int i;
1467
1468 DDB(printk("ad1848_detect(%x)\n", io_base));
1469
1470 if (ad_flags)
1471 {
1472 if (*ad_flags == 0x12345678)
1473 {
1474 interwave = 1;
1475 *ad_flags = 0;
1476 }
1477 if (*ad_flags == 0x12345677)
1478 {
1479 cs4248_flag = 1;
1480 *ad_flags = 0;
1481 }
1482 }
1483 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1484 {
1485 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1486 return 0;
1487 }
1488 if (check_region(io_base, 4))
1489 {
1490 printk(KERN_ERR "ad1848.c: Port %x not free.\n", io_base);
1491 return 0;
1492 }
1493 devc->base = io_base;
1494 devc->irq_ok = 0;
1495 devc->timer_running = 0;
1496 devc->MCE_bit = 0x40;
1497 devc->irq = 0;
1498 devc->open_mode = 0;
1499 devc->chip_name = devc->name = "AD1848";
1500 devc->model = MD_1848; /* AD1848 or CS4248 */
1501 devc->levels = NULL;
1502 devc->debug_flag = 0;
1503
1504 /*
1505 * Check that the I/O address is in use.
1506 *
1507 * The bit 0x80 of the base I/O port is known to be 0 after the
1508 * chip has performed its power on initialization. Just assume
1509 * this has happened before the OS is starting.
1510 *
1511 * If the I/O address is unused, it typically returns 0xff.
1512 */
1513
1514 if (inb(devc->base) == 0xff)
1515 {
1516 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1517 }
1518
1519 /*
1520 * Wait for the device to stop initialization
1521 */
1522
1523 DDB(printk("ad1848_detect() - step 0\n"));
1524
1525 for (i = 0; i < 10000000; i++)
1526 {
1527 unsigned char x = inb(devc->base);
1528
1529 if (x == 0xff || !(x & 0x80))
1530 break;
1531 }
1532
1533 DDB(printk("ad1848_detect() - step A\n"));
1534
1535 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1536 ad_leave_MCE(devc);
1537
1538 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1539 {
1540 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1541 return 0;
1542 }
1543
1544 /*
1545 * Test if it's possible to change contents of the indirect registers.
1546 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1547 * so try to avoid using it.
1548 */
1549
1550 DDB(printk("ad1848_detect() - step B\n"));
1551 ad_write(devc, 0, 0xaa);
1552 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1553
1554 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1555 {
1556 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1557 ad1847_flag = 1;
1558 else
1559 {
1560 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1561 return 0;
1562 }
1563 }
1564 DDB(printk("ad1848_detect() - step C\n"));
1565 ad_write(devc, 0, 0x45);
1566 ad_write(devc, 1, 0xaa);
1567
1568 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1569 {
1570 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1571 ad1847_flag = 1;
1572 else
1573 {
1574 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1575 return 0;
1576 }
1577 }
1578
1579 /*
1580 * The indirect register I12 has some read only bits. Let's
1581 * try to change them.
1582 */
1583
1584 DDB(printk("ad1848_detect() - step D\n"));
1585 tmp = ad_read(devc, 12);
1586 ad_write(devc, 12, (~tmp) & 0x0f);
1587
1588 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1589 {
1590 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1591 return 0;
1592 }
1593
1594 /*
1595 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1596 * 0x01=RevB and 0x0A=RevC.
1597 */
1598
1599 /*
1600 * The original AD1848/CS4248 has just 15 indirect registers. This means
1601 * that I0 and I16 should return the same value (etc.).
1602 * However this doesn't work with CS4248. Actually it seems to be impossible
1603 * to detect if the chip is a CS4231 or CS4248.
1604 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1605 * with CS4231.
1606 */
1607
1608 /*
1609 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1610 * with it. Accept this situation as a possible indication of this chip.
1611 */
1612
1613 DDB(printk("ad1848_detect() - step F\n"));
1614 ad_write(devc, 12, 0); /* Mode2=disabled */
1615
1616 for (i = 0; i < 16; i++)
1617 {
1618 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1619 {
1620 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1621 if (!ad1847_flag)
1622 optiC930 = 1;
1623 break;
1624 }
1625 }
1626
1627 /*
1628 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1629 * The bit 0x80 is always 1 in CS4248 and CS4231.
1630 */
1631
1632 DDB(printk("ad1848_detect() - step G\n"));
1633
1634 if (ad_flags && *ad_flags == 400)
1635 *ad_flags = 0;
1636 else
1637 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1638
1639
1640 if (ad_flags)
1641 *ad_flags = 0;
1642
1643 tmp1 = ad_read(devc, 12);
1644 if (tmp1 & 0x80)
1645 {
1646 if (ad_flags)
1647 *ad_flags |= AD_F_CS4248;
1648
1649 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1650 }
1651 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1652 {
1653 /*
1654 * CS4231 detected - is it?
1655 *
1656 * Verify that setting I0 doesn't change I16.
1657 */
1658
1659 DDB(printk("ad1848_detect() - step H\n"));
1660 ad_write(devc, 16, 0); /* Set I16 to known value */
1661
1662 ad_write(devc, 0, 0x45);
1663 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1664 {
1665 ad_write(devc, 0, 0xaa);
1666 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1667 {
1668 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1669 return 0;
1670 }
1671
1672 /*
1673 * Verify that some bits of I25 are read only.
1674 */
1675
1676 DDB(printk("ad1848_detect() - step I\n"));
1677 tmp1 = ad_read(devc, 25); /* Original bits */
1678 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1679 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1680 {
1681 int id;
1682
1683 /*
1684 * It's at least CS4231
1685 */
1686
1687 devc->chip_name = "CS4231";
1688 devc->model = MD_4231;
1689
1690 /*
1691 * It could be an AD1845 or CS4231A as well.
1692 * CS4231 and AD1845 report the same revision info in I25
1693 * while the CS4231A reports different.
1694 */
1695
1696 id = ad_read(devc, 25);
1697 if ((id & 0xe7) == 0x80) /* Device busy??? */
1698 id = ad_read(devc, 25);
1699 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1700 id = ad_read(devc, 25);
1701 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1702
1703 if ((id & 0xe7) == 0x80) {
1704 /*
1705 * It must be a CS4231 or AD1845. The register I23 of
1706 * CS4231 is undefined and it appears to be read only.
1707 * AD1845 uses I23 for setting sample rate. Assume
1708 * the chip is AD1845 if I23 is changeable.
1709 */
1710
1711 unsigned char tmp = ad_read(devc, 23);
1712 ad_write(devc, 23, ~tmp);
1713
1714 if (interwave)
1715 {
1716 devc->model = MD_IWAVE;
1717 devc->chip_name = "IWave";
1718 }
1719 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1720 {
1721 devc->chip_name = "AD1845";
1722 devc->model = MD_1845;
1723 }
1724 else if (cs4248_flag)
1725 {
1726 if (ad_flags)
1727 *ad_flags |= AD_F_CS4248;
1728 devc->chip_name = "CS4248";
1729 devc->model = MD_1848;
1730 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1731 }
1732 ad_write(devc, 23, tmp); /* Restore */
1733 }
1734 else
1735 {
1736 switch (id & 0x1f) {
1737 case 3: /* CS4236/CS4235 */
1738 {
1739 int xid;
1740 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1741 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1742 xid = inb(io_Indexed_Data(devc));
1743 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1744 if ((xid & 0x1f) == 0x1d) {
1745 devc->chip_name = "CS4235";
1746 devc->model = MD_4235;
1747 } else {
1748 devc->chip_name = "CS4236";
1749 devc->model = MD_4232;
1750 }
1751 }
1752 break;
1753
1754 case 2: /* CS4232/CS4232A */
1755 devc->chip_name = "CS4232";
1756 devc->model = MD_4232;
1757 break;
1758
1759 case 0:
1760 if ((id & 0xe0) == 0xa0)
1761 {
1762 devc->chip_name = "CS4231A";
1763 devc->model = MD_4231A;
1764 }
1765 else
1766 {
1767 devc->chip_name = "CS4321";
1768 devc->model = MD_4231;
1769 }
1770 break;
1771
1772 default: /* maybe */
1773 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1774 if (optiC930)
1775 {
1776 devc->chip_name = "82C930";
1777 devc->model = MD_C930;
1778 }
1779 else
1780 {
1781 devc->chip_name = "CS4231";
1782 devc->model = MD_4231;
1783 }
1784 }
1785 }
1786 }
1787 ad_write(devc, 25, tmp1); /* Restore bits */
1788
1789 DDB(printk("ad1848_detect() - step K\n"));
1790 }
1791 } else if (tmp1 == 0x0a) {
1792 /*
1793 * Is it perhaps a SoundPro CMI8330?
1794 * If so, then we should be able to change indirect registers
1795 * greater than I15 after activating MODE2, even though reading
1796 * back I12 does not show it.
1797 */
1798
1799 /*
1800 * Let's try comparing register values
1801 */
1802 for (i = 0; i < 16; i++) {
1803 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1804 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1805 soundpro = 1;
1806 devc->chip_name = "SoundPro CMI 8330";
1807 break;
1808 }
1809 }
1810 }
1811
1812 DDB(printk("ad1848_detect() - step L\n"));
1813 if (ad_flags)
1814 {
1815 if (devc->model != MD_1848)
1816 *ad_flags |= AD_F_CS4231;
1817 }
1818 DDB(printk("ad1848_detect() - Detected OK\n"));
1819
1820 if (devc->model == MD_1848 && ad1847_flag)
1821 devc->chip_name = "AD1847";
1822
1823
1824 return 1;
1825 }
1826
1827 int ad1848_init(char *name, int io_base, int irq, int dma_playback, int dma_capture, int share_dma, int *osp)
1828 {
1829 /*
1830 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1831 * so that this driver doesn't need to allocate/deallocate it.
1832 * The actually used IRQ is ABS(irq).
1833 */
1834
1835
1836 int my_dev;
1837 char dev_name[100];
1838 int e;
1839
1840 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1841
1842 ad1848_port_info *portc = NULL;
1843
1844 devc->irq = (irq > 0) ? irq : 0;
1845 devc->open_mode = 0;
1846 devc->timer_ticks = 0;
1847 devc->dma1 = dma_playback;
1848 devc->dma2 = dma_capture;
1849 devc->audio_flags = DMA_AUTOMODE;
1850 devc->playback_dev = devc->record_dev = 0;
1851 if (name != NULL)
1852 devc->name = name;
1853
1854 if (name != NULL && name[0] != 0)
1855 sprintf(dev_name,
1856 "%s (%s)", name, devc->chip_name);
1857 else
1858 sprintf(dev_name,
1859 "Generic audio codec (%s)", devc->chip_name);
1860
1861 request_region(devc->base, 4, devc->name);
1862
1863 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1864
1865 if (devc->model == MD_1848 || devc->model == MD_C930)
1866 devc->audio_flags |= DMA_HARDSTOP;
1867
1868 if (devc->model > MD_1848)
1869 {
1870 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1871 devc->audio_flags &= ~DMA_DUPLEX;
1872 else
1873 devc->audio_flags |= DMA_DUPLEX;
1874 }
1875
1876 portc = (ad1848_port_info *) kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1877 if(portc==NULL)
1878 return -1;
1879
1880 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
1881 dev_name,
1882 &ad1848_audio_driver,
1883 sizeof(struct audio_driver),
1884 devc->audio_flags,
1885 ad_format_mask[devc->model],
1886 devc,
1887 dma_playback,
1888 dma_capture)) < 0)
1889 {
1890 kfree(portc);
1891 portc=NULL;
1892 return -1;
1893 }
1894
1895 audio_devs[my_dev]->portc = portc;
1896 audio_devs[my_dev]->mixer_dev = -1;
1897 memset((char *) portc, 0, sizeof(*portc));
1898
1899 nr_ad1848_devs++;
1900
1901 ad1848_init_hw(devc);
1902
1903 if (irq > 0)
1904 {
1905 devc->dev_no = my_dev;
1906 if (request_irq(devc->irq, adintr, 0, devc->name, (void *)my_dev) < 0)
1907 {
1908 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
1909 /* Don't free it either then.. */
1910 devc->irq = 0;
1911 }
1912 if (capabilities[devc->model].flags & CAP_F_TIMER)
1913 {
1914 #ifndef __SMP__
1915 int x;
1916 unsigned char tmp = ad_read(devc, 16);
1917 #endif
1918
1919 devc->timer_ticks = 0;
1920
1921 ad_write(devc, 21, 0x00); /* Timer MSB */
1922 ad_write(devc, 20, 0x10); /* Timer LSB */
1923 #ifndef __SMP__
1924 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
1925 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
1926 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
1927
1928 if (devc->timer_ticks == 0)
1929 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
1930 else
1931 {
1932 DDB(printk("Interrupt test OK\n"));
1933 devc->irq_ok = 1;
1934 }
1935 #else
1936 devc->irq_ok=1;
1937 #endif
1938 }
1939 else
1940 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
1941 } else if (irq < 0)
1942 irq2dev[-irq] = devc->dev_no = my_dev;
1943
1944 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
1945 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
1946 devc->irq_ok)
1947 ad1848_tmr_install(my_dev);
1948 #endif
1949
1950 if (!share_dma)
1951 {
1952 if (sound_alloc_dma(dma_playback, devc->name))
1953 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
1954
1955 if (dma_capture != dma_playback)
1956 if (sound_alloc_dma(dma_capture, devc->name))
1957 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
1958 }
1959 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
1960 dev_name,
1961 &ad1848_mixer_operations,
1962 sizeof(struct mixer_operations),
1963 devc)) >= 0)
1964 {
1965 audio_devs[my_dev]->mixer_dev = e;
1966 }
1967 return my_dev;
1968 }
1969
1970 int ad1848_control(int cmd, int arg)
1971 {
1972 ad1848_info *devc;
1973
1974 if (nr_ad1848_devs < 1)
1975 return -ENODEV;
1976
1977 devc = &adev_info[nr_ad1848_devs - 1];
1978
1979 switch (cmd)
1980 {
1981 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
1982 if (devc->model != MD_1845)
1983 return -EINVAL;
1984 ad_enter_MCE(devc);
1985 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
1986 ad_leave_MCE(devc);
1987 break;
1988
1989 case AD1848_MIXER_REROUTE:
1990 {
1991 int o = (arg >> 8) & 0xff;
1992 int n = arg & 0xff;
1993
1994 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
1995 return -EINVAL;
1996
1997 if (!(devc->supported_devices & (1 << o)) &&
1998 !(devc->supported_rec_devices & (1 << o)))
1999 return -EINVAL;
2000
2001 if (n == SOUND_MIXER_NONE)
2002 { /* Just hide this control */
2003 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2004 devc->supported_devices &= ~(1 << o);
2005 devc->supported_rec_devices &= ~(1 << o);
2006 break;
2007 }
2008
2009 /* Make the mixer control identified by o to appear as n */
2010 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2011 return -EINVAL;
2012
2013 devc->mixer_reroute[n] = o; /* Rename the control */
2014 if (devc->supported_devices & (1 << o))
2015 devc->supported_devices |= (1 << n);
2016 if (devc->supported_rec_devices & (1 << o))
2017 devc->supported_rec_devices |= (1 << n);
2018
2019 devc->supported_devices &= ~(1 << o);
2020 devc->supported_rec_devices &= ~(1 << o);
2021 }
2022 break;
2023 }
2024 return 0;
2025 }
2026
2027 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2028 {
2029 int i, mixer, dev = 0;
2030 ad1848_info *devc = NULL;
2031
2032 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2033 {
2034 if (adev_info[i].base == io_base)
2035 {
2036 devc = &adev_info[i];
2037 dev = devc->dev_no;
2038 }
2039 }
2040
2041 if (devc != NULL)
2042 {
2043 if(audio_devs[dev]->portc!=NULL)
2044 kfree(audio_devs[dev]->portc);
2045 release_region(devc->base, 4);
2046
2047 if (!share_dma)
2048 {
2049 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2050 free_irq(devc->irq, (void *)devc->dev_no);
2051
2052 sound_free_dma(dma_playback);
2053
2054 if (dma_playback != dma_capture)
2055 sound_free_dma(dma_capture);
2056
2057 }
2058 mixer = audio_devs[devc->dev_no]->mixer_dev;
2059 if(mixer>=0)
2060 sound_unload_mixerdev(mixer);
2061
2062 nr_ad1848_devs--;
2063 for ( ; i < nr_ad1848_devs ; i++)
2064 adev_info[i] = adev_info[i+1];
2065 }
2066 else
2067 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2068 }
2069
2070 void adintr(int irq, void *dev_id, struct pt_regs *dummy)
2071 {
2072 unsigned char status;
2073 ad1848_info *devc;
2074 int dev;
2075 int alt_stat = 0xff;
2076 unsigned char c930_stat = 0;
2077 int cnt = 0;
2078
2079 dev = (int)dev_id;
2080 devc = (ad1848_info *) audio_devs[dev]->devc;
2081
2082 interrupt_again: /* Jump back here if int status doesn't reset */
2083
2084 status = inb(io_Status(devc));
2085
2086 if (status == 0x80)
2087 printk(KERN_DEBUG "adintr: Why?\n");
2088 if (devc->model == MD_1848)
2089 outb((0), io_Status(devc)); /* Clear interrupt status */
2090
2091 if (status & 0x01)
2092 {
2093 if (devc->model == MD_C930)
2094 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2095 unsigned long flags;
2096
2097 save_flags(flags);
2098 cli();
2099
2100 /* 0xe0e is C930 address port
2101 * 0xe0f is C930 data port
2102 */
2103 outb(11, 0xe0e);
2104 c930_stat = inb(0xe0f);
2105 outb((~c930_stat), 0xe0f);
2106
2107 restore_flags(flags);
2108
2109 alt_stat = (c930_stat << 2) & 0x30;
2110 }
2111 else if (devc->model != MD_1848)
2112 {
2113 alt_stat = ad_read(devc, 24);
2114 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2115 }
2116
2117 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2118 {
2119 DMAbuf_inputintr(devc->record_dev);
2120 }
2121 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2122 (alt_stat & 0x10))
2123 {
2124 DMAbuf_outputintr(devc->playback_dev, 1);
2125 }
2126 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2127 {
2128 devc->timer_ticks++;
2129 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
2130 if (timer_installed == dev && devc->timer_running)
2131 sound_timer_interrupt();
2132 #endif
2133 }
2134 }
2135 /*
2136 * Sometimes playback or capture interrupts occur while a timer interrupt
2137 * is being handled. The interrupt will not be retriggered if we don't
2138 * handle it now. Check if an interrupt is still pending and restart
2139 * the handler in this case.
2140 */
2141 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2142 {
2143 goto interrupt_again;
2144 }
2145 }
2146
2147 /*
2148 * Experimental initialization sequence for the integrated sound system
2149 * of Compaq Deskpro XL.
2150 */
2151
2152 static int init_deskpro(struct address_info *hw_config)
2153 {
2154 unsigned char tmp;
2155
2156 if ((tmp = inb(0xc44)) == 0xff)
2157 {
2158 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2159 return 0;
2160 }
2161 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2162 if (inb(0xc44) != 0x04)
2163 {
2164 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2165 return 0;
2166 }
2167 /*
2168 * OK. It looks like a Deskpro so let's proceed.
2169 */
2170
2171 /*
2172 * I/O port 0xc44 Audio configuration register.
2173 *
2174 * bits 0xc0: Audio revision bits
2175 * 0x00 = Compaq Business Audio
2176 * 0x40 = MS Sound System Compatible (reset default)
2177 * 0x80 = Reserved
2178 * 0xc0 = Reserved
2179 * bit 0x20: No Wait State Enable
2180 * 0x00 = Disabled (reset default, DMA mode)
2181 * 0x20 = Enabled (programmed I/O mode)
2182 * bit 0x10: MS Sound System Decode Enable
2183 * 0x00 = Decoding disabled (reset default)
2184 * 0x10 = Decoding enabled
2185 * bit 0x08: FM Synthesis Decode Enable
2186 * 0x00 = Decoding Disabled (reset default)
2187 * 0x08 = Decoding enabled
2188 * bit 0x04 Bank select
2189 * 0x00 = Bank 0
2190 * 0x04 = Bank 1
2191 * bits 0x03 MSS Base address
2192 * 0x00 = 0x530 (reset default)
2193 * 0x01 = 0x604
2194 * 0x02 = 0xf40
2195 * 0x03 = 0xe80
2196 */
2197
2198 #ifdef DEBUGXL
2199 /* Debug printing */
2200 printk("Port 0xc44 (before): ");
2201 outb((tmp & ~0x04), 0xc44);
2202 printk("%02x ", inb(0xc44));
2203 outb((tmp | 0x04), 0xc44);
2204 printk("%02x\n", inb(0xc44));
2205 #endif
2206
2207 /* Set bank 1 of the register */
2208 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2209
2210 switch (hw_config->io_base)
2211 {
2212 case 0x530:
2213 tmp |= 0x00;
2214 break;
2215 case 0x604:
2216 tmp |= 0x01;
2217 break;
2218 case 0xf40:
2219 tmp |= 0x02;
2220 break;
2221 case 0xe80:
2222 tmp |= 0x03;
2223 break;
2224 default:
2225 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2226 return 0;
2227 }
2228 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2229
2230 #ifdef DEBUGXL
2231 /* Debug printing */
2232 printk("Port 0xc44 (after): ");
2233 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2234 printk("%02x ", inb(0xc44));
2235 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2236 printk("%02x\n", inb(0xc44));
2237 #endif
2238
2239 /*
2240 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2241 *
2242 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2243 * bank=0, bit 0x01: SBIC Power Control Bit
2244 * 0x00 = Powered up
2245 * 0x01 = Powered down
2246 * bank=1, bits 0xfc: MSS ID (default=0x40)
2247 */
2248
2249 #ifdef DEBUGXL
2250 /* Debug printing */
2251 printk("Port 0xc45 (before): ");
2252 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2253 printk("%02x ", inb(0xc45));
2254 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2255 printk("%02x\n", inb(0xc45));
2256 #endif
2257
2258 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2259 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2260 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2261 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2262
2263 #ifdef DEBUGXL
2264 /* Debug printing */
2265 printk("Port 0xc45 (after): ");
2266 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2267 printk("%02x ", inb(0xc45));
2268 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2269 printk("%02x\n", inb(0xc45));
2270 #endif
2271
2272
2273 /*
2274 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2275 *
2276 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2277 * bank=1, bits 0xff: Audio addressing ASIC id
2278 */
2279
2280 #ifdef DEBUGXL
2281 /* Debug printing */
2282 printk("Port 0xc46 (before): ");
2283 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2284 printk("%02x ", inb(0xc46));
2285 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2286 printk("%02x\n", inb(0xc46));
2287 #endif
2288
2289 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2290 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2291 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2292 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2293
2294 #ifdef DEBUGXL
2295 /* Debug printing */
2296 printk("Port 0xc46 (after): ");
2297 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2298 printk("%02x ", inb(0xc46));
2299 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2300 printk("%02x\n", inb(0xc46));
2301 #endif
2302
2303 /*
2304 * I/O port 0xc47 FM Address Decode Register.
2305 *
2306 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2307 * bank=1, bits 0xff: Reserved
2308 */
2309
2310 #ifdef DEBUGXL
2311 /* Debug printing */
2312 printk("Port 0xc47 (before): ");
2313 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2314 printk("%02x ", inb(0xc47));
2315 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2316 printk("%02x\n", inb(0xc47));
2317 #endif
2318
2319 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2320 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2321 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2322 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2323
2324 #ifdef DEBUGXL
2325 /* Debug printing */
2326 printk("Port 0xc47 (after): ");
2327 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2328 printk("%02x ", inb(0xc47));
2329 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2330 printk("%02x\n", inb(0xc47));
2331 #endif
2332
2333 /*
2334 * I/O port 0xc6f = Audio Disable Function Register
2335 */
2336
2337 #ifdef DEBUGXL
2338 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2339 #endif
2340
2341 outb((0x80), 0xc6f);
2342
2343 #ifdef DEBUGXL
2344 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2345 #endif
2346
2347 return 1;
2348 }
2349
2350 int probe_ms_sound(struct address_info *hw_config)
2351 {
2352 unsigned char tmp;
2353
2354 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2355
2356 if (check_region(hw_config->io_base, 8))
2357 {
2358 printk(KERN_ERR "MSS: I/O port conflict\n");
2359 return 0;
2360 }
2361 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2362 {
2363 /* check_opl3(0x388, hw_config); */
2364 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2365 }
2366
2367 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2368 {
2369 if (!init_deskpro(hw_config))
2370 return 0;
2371 }
2372
2373 /*
2374 * Check if the IO port returns valid signature. The original MS Sound
2375 * system returns 0x04 while some cards (AudioTrix Pro for example)
2376 * return 0x00 or 0x0f.
2377 */
2378
2379 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2380 {
2381 int ret;
2382
2383 DDB(printk("I/O address is inactive (%x)\n", tmp));
2384 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2385 return 0;
2386 return 1;
2387 }
2388 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2389 if ((tmp & 0x3f) != 0x04 &&
2390 (tmp & 0x3f) != 0x0f &&
2391 (tmp & 0x3f) != 0x00)
2392 {
2393 int ret;
2394
2395 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2396 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2397 if (!(ret = ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp)))
2398 return 0;
2399
2400 hw_config->card_subtype = 1;
2401 return 1;
2402 }
2403 if ((hw_config->irq != 5) &&
2404 (hw_config->irq != 7) &&
2405 (hw_config->irq != 9) &&
2406 (hw_config->irq != 10) &&
2407 (hw_config->irq != 11) &&
2408 (hw_config->irq != 12))
2409 {
2410 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2411 return 0;
2412 }
2413 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2414 {
2415 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2416 return 0;
2417 }
2418 /*
2419 * Check that DMA0 is not in use with a 8 bit board.
2420 */
2421
2422 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2423 {
2424 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2425 return 0;
2426 }
2427 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2428 {
2429 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2430 return 0;
2431 }
2432 return ad1848_detect(hw_config->io_base + 4, NULL, hw_config->osp);
2433 }
2434
2435 void attach_ms_sound(struct address_info *hw_config)
2436 {
2437 static char interrupt_bits[12] =
2438 {
2439 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2440 };
2441 char bits, dma2_bit = 0;
2442
2443 static char dma_bits[4] =
2444 {
2445 1, 2, 0, 3
2446 };
2447
2448 int config_port = hw_config->io_base + 0;
2449 int version_port = hw_config->io_base + 3;
2450 int dma = hw_config->dma;
2451 int dma2 = hw_config->dma2;
2452
2453 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2454 {
2455 hw_config->slots[0] = ad1848_init("MS Sound System", hw_config->io_base + 4,
2456 hw_config->irq,
2457 hw_config->dma,
2458 hw_config->dma2, 0, hw_config->osp);
2459 request_region(hw_config->io_base, 4, "WSS config");
2460 return;
2461 }
2462 /*
2463 * Set the IRQ and DMA addresses.
2464 */
2465
2466 bits = interrupt_bits[hw_config->irq];
2467 if (bits == -1)
2468 {
2469 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2470 return;
2471 }
2472 outb((bits | 0x40), config_port);
2473 if ((inb(version_port) & 0x40) == 0)
2474 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2475
2476 /*
2477 * Handle the capture DMA channel
2478 */
2479
2480 if (dma2 != -1 && dma2 != dma)
2481 {
2482 if (!((dma == 0 && dma2 == 1) ||
2483 (dma == 1 && dma2 == 0) ||
2484 (dma == 3 && dma2 == 0)))
2485 { /* Unsupported combination. Try to swap channels */
2486 int tmp = dma;
2487
2488 dma = dma2;
2489 dma2 = tmp;
2490 }
2491 if ((dma == 0 && dma2 == 1) ||
2492 (dma == 1 && dma2 == 0) ||
2493 (dma == 3 && dma2 == 0))
2494 {
2495 dma2_bit = 0x04; /* Enable capture DMA */
2496 }
2497 else
2498 {
2499 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2500 dma2 = dma;
2501 }
2502 }
2503 else
2504 {
2505 dma2 = dma;
2506 }
2507
2508 hw_config->dma = dma;
2509 hw_config->dma2 = dma2;
2510
2511 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2512
2513 hw_config->slots[0] = ad1848_init("MSS audio codec", hw_config->io_base + 4,
2514 hw_config->irq,
2515 dma,
2516 dma2, 0,
2517 hw_config->osp);
2518 request_region(hw_config->io_base, 4, "WSS config");
2519 }
2520
2521 void unload_ms_sound(struct address_info *hw_config)
2522 {
2523 ad1848_unload(hw_config->io_base + 4,
2524 hw_config->irq,
2525 hw_config->dma,
2526 hw_config->dma2, 0);
2527 sound_unload_audiodev(hw_config->slots[0]);
2528 release_region(hw_config->io_base, 4);
2529 }
2530
2531 #if defined(CONFIG_SEQUENCER) && !defined(EXCLUDE_TIMERS)
2532
2533 /*
2534 * Timer stuff (for /dev/music).
2535 */
2536
2537 static unsigned int current_interval = 0;
2538
2539 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2540 {
2541 unsigned long flags;
2542 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2543 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2544 unsigned long divider;
2545
2546 save_flags(flags);
2547 cli();
2548
2549 /*
2550 * Length of the timer interval (in nanoseconds) depends on the
2551 * selected crystal oscillator. Check this from bit 0x01 of I8.
2552 *
2553 * AD1845 has just one oscillator which has cycle time of 10.050 us
2554 * (when a 24.576 MHz xtal oscillator is used).
2555 *
2556 * Convert requested interval to nanoseconds before computing
2557 * the timer divider.
2558 */
2559
2560 if (devc->model == MD_1845)
2561 xtal_nsecs = 10050;
2562 else if (ad_read(devc, 8) & 0x01)
2563 xtal_nsecs = 9920;
2564 else
2565 xtal_nsecs = 9969;
2566
2567 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2568
2569 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2570 divider = 100;
2571
2572 if (divider > 65535) /* Overflow check */
2573 divider = 65535;
2574
2575 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2576 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2577 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2578 devc->timer_running = 1;
2579 restore_flags(flags);
2580
2581 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2582 }
2583
2584 static void ad1848_tmr_reprogram(int dev)
2585 {
2586 /*
2587 * Audio driver has changed sampling rate so that a different xtal
2588 * oscillator was selected. We have to reprogram the timer rate.
2589 */
2590
2591 ad1848_tmr_start(dev, current_interval);
2592 sound_timer_syncinterval(current_interval);
2593 }
2594
2595 static void ad1848_tmr_disable(int dev)
2596 {
2597 unsigned long flags;
2598 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2599
2600 save_flags(flags);
2601 cli();
2602 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2603 devc->timer_running = 0;
2604 restore_flags(flags);
2605 }
2606
2607 static void ad1848_tmr_restart(int dev)
2608 {
2609 unsigned long flags;
2610 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2611
2612 if (current_interval == 0)
2613 return;
2614
2615 save_flags(flags);
2616 cli();
2617 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2618 devc->timer_running = 1;
2619 restore_flags(flags);
2620 }
2621
2622 static struct sound_lowlev_timer ad1848_tmr =
2623 {
2624 0,
2625 2,
2626 ad1848_tmr_start,
2627 ad1848_tmr_disable,
2628 ad1848_tmr_restart
2629 };
2630
2631 static int ad1848_tmr_install(int dev)
2632 {
2633 if (timer_installed != -1)
2634 return 0; /* Don't install another timer */
2635
2636 timer_installed = ad1848_tmr.dev = dev;
2637 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2638
2639 return 1;
2640 }
2641 #endif
2642
2643
2644 EXPORT_SYMBOL(ad1848_detect);
2645 EXPORT_SYMBOL(ad1848_init);
2646 EXPORT_SYMBOL(ad1848_unload);
2647 EXPORT_SYMBOL(ad1848_control);
2648 EXPORT_SYMBOL(adintr);
2649 EXPORT_SYMBOL(probe_ms_sound);
2650 EXPORT_SYMBOL(attach_ms_sound);
2651 EXPORT_SYMBOL(unload_ms_sound);
2652
2653 #ifdef MODULE
2654
2655 MODULE_PARM(io, "i"); /* I/O for a raw AD1848 card */
2656 MODULE_PARM(irq, "i"); /* IRQ to use */
2657 MODULE_PARM(dma, "i"); /* First DMA channel */
2658 MODULE_PARM(dma2, "i"); /* Second DMA channel */
2659 MODULE_PARM(type, "i"); /* Card type */
2660 MODULE_PARM(deskpro_xl, "i"); /* Special magic for Deskpro XL boxen */
2661 MODULE_PARM(soundpro, "i"); /* More special magic for SoundPro chips */
2662
2663 int io = -1;
2664 int irq = -1;
2665 int dma = -1;
2666 int dma2 = -1;
2667 int type = 0;
2668
2669 static int loaded = 0;
2670
2671 struct address_info hw_config;
2672
2673 int init_module(void)
2674 {
2675 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2676 if(io != -1)
2677 {
2678 if(irq == -1 || dma == -1)
2679 {
2680 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
2681 return -EINVAL;
2682 }
2683 hw_config.irq = irq;
2684 hw_config.io_base = io;
2685 hw_config.dma = dma;
2686 hw_config.dma2 = dma2;
2687 hw_config.card_subtype = type;
2688 if(!probe_ms_sound(&hw_config))
2689 return -ENODEV;
2690 attach_ms_sound(&hw_config);
2691 loaded=1;
2692 }
2693 SOUND_LOCK;
2694 return 0;
2695 }
2696
2697 void cleanup_module(void)
2698 {
2699 SOUND_LOCK_END;
2700 if(loaded)
2701 unload_ms_sound(&hw_config);
2702 }
2703
2704 #endif
2705 #endif
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