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Import 2.3.18pre1
[davej-history.git] / drivers / net / sunqe.h
blob7b59a91ce8e82e4163fe6906f6f77dd98f3f1f96
1 /* sunqe.h: Definitions for the Sun QuadEthernet driver.
2 *
3 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6 #ifndef _SUNQE_H
7 #define _SUNQE_H
8
9 /* QEC global registers. */
10 struct qe_globreg {
11 volatile unsigned int ctrl; /* Control */
12 volatile unsigned int stat; /* Status */
13 volatile unsigned int psize; /* Packet Size */
14 volatile unsigned int msize; /* Local-mem size (64K) */
15 volatile unsigned int rsize; /* Receive partition size */
16 volatile unsigned int tsize; /* Transmit partition size */
17 };
18
19 #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
20 #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
21 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
22 #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */
23 #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
24 #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
25 #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
26 #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */
27
28 #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
29 #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
30 #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */
31 #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */
32
33 #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
34 #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
35 #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
36 #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
37
38 /* In MACE mode, there are four qe channels. Each channel has it's own
39 * status bits in the QEC status register. This macro picks out the
40 * ones you want.
41 */
42 #define GLOB_STAT_PER_QE(status, channel) (((status) >> ((channel) * 4)) & 0xf)
43
44 /* The following registers are for per-qe channel information/status. */
45 struct qe_creg {
46 volatile unsigned int ctrl; /* Control */
47 volatile unsigned int stat; /* Status */
48 volatile unsigned int rxds; /* RX descriptor ring ptr */
49 volatile unsigned int txds; /* TX descriptor ring ptr */
50 volatile unsigned int rimask; /* RX Interrupt Mask */
51 volatile unsigned int timask; /* TX Interrupt Mask */
52 volatile unsigned int qmask; /* QEC Error Interrupt Mask */
53 volatile unsigned int mmask; /* MACE Error Interrupt Mask */
54 volatile unsigned int rxwbufptr; /* Local memory rx write ptr */
55 volatile unsigned int rxrbufptr; /* Local memory rx read ptr */
56 volatile unsigned int txwbufptr; /* Local memory tx write ptr */
57 volatile unsigned int txrbufptr; /* Local memory tx read ptr */
58 volatile unsigned int ccnt; /* Collision Counter */
59 volatile unsigned int pipg; /* Inter-Frame Gap */
60 };
61
62 #define CREG_CTRL_RXOFF 0x00000004 /* Disable this qe's receiver*/
63 #define CREG_CTRL_RESET 0x00000002 /* Reset this qe channel */
64 #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */
65
66 #define CREG_STAT_EDEFER 0x10000000 /* Excessive Defers */
67 #define CREG_STAT_CLOSS 0x08000000 /* Carrier Loss */
68 #define CREG_STAT_ERETRIES 0x04000000 /* More than 16 retries */
69 #define CREG_STAT_LCOLL 0x02000000 /* Late TX Collision */
70 #define CREG_STAT_FUFLOW 0x01000000 /* FIFO Underflow */
71 #define CREG_STAT_JERROR 0x00800000 /* Jabber Error */
72 #define CREG_STAT_BERROR 0x00400000 /* Babble Error */
73 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
74 #define CREG_STAT_CCOFLOW 0x00100000 /* TX Coll-counter Overflow */
75 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
76 #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
77 #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
78 #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
79 #define CREG_STAT_RCCOFLOW 0x00001000 /* RX Coll-counter Overflow */
80 #define CREG_STAT_RUOFLOW 0x00000800 /* Runt Counter Overflow */
81 #define CREG_STAT_MCOFLOW 0x00000400 /* Missed Counter Overflow */
82 #define CREG_STAT_RXFOFLOW 0x00000200 /* RX FIFO Overflow */
83 #define CREG_STAT_RLCOLL 0x00000100 /* RX Late Collision */
84 #define CREG_STAT_FCOFLOW 0x00000080 /* Frame Counter Overflow */
85 #define CREG_STAT_CECOFLOW 0x00000040 /* CRC Error-counter Overflow*/
86 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
88 #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
89 #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
90 #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
91 #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
92
93 #define CREG_STAT_ERRORS (CREG_STAT_EDEFER|CREG_STAT_CLOSS|CREG_STAT_ERETRIES| \
94 CREG_STAT_LCOLL|CREG_STAT_FUFLOW|CREG_STAT_JERROR| \
95 CREG_STAT_BERROR|CREG_STAT_CCOFLOW|CREG_STAT_TXDERROR| \
96 CREG_STAT_TXLERR|CREG_STAT_TXPERR|CREG_STAT_TXSERR| \
97 CREG_STAT_RCCOFLOW|CREG_STAT_RUOFLOW|CREG_STAT_MCOFLOW| \
98 CREG_STAT_RXFOFLOW|CREG_STAT_RLCOLL|CREG_STAT_FCOFLOW| \
99 CREG_STAT_CECOFLOW|CREG_STAT_RXDROP|CREG_STAT_RXSMALL| \
100 CREG_STAT_RXLERR|CREG_STAT_RXPERR|CREG_STAT_RXSERR)
101
102 #define CREG_QMASK_COFLOW 0x00100000 /* CollCntr overflow */
103 #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */
104 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
105 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
106 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
107 #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
108 #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
109 #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
110 #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
111 #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
112
113 #define CREG_MMASK_EDEFER 0x10000000 /* Excess defer */
114 #define CREG_MMASK_CLOSS 0x08000000 /* Carrier loss */
115 #define CREG_MMASK_ERETRY 0x04000000 /* Excess retry */
116 #define CREG_MMASK_LCOLL 0x02000000 /* Late collision error */
117 #define CREG_MMASK_UFLOW 0x01000000 /* Underflow */
118 #define CREG_MMASK_JABBER 0x00800000 /* Jabber error */
119 #define CREG_MMASK_BABBLE 0x00400000 /* Babble error */
120 #define CREG_MMASK_OFLOW 0x00000800 /* Overflow */
121 #define CREG_MMASK_RXCOLL 0x00000400 /* RX Coll-Cntr overflow */
122 #define CREG_MMASK_RPKT 0x00000200 /* Runt pkt overflow */
123 #define CREG_MMASK_MPKT 0x00000100 /* Missed pkt overflow */
124
125 #define CREG_PIPG_TENAB 0x00000020 /* Enable Throttle */
126 #define CREG_PIPG_MMODE 0x00000010 /* Manual Mode */
127 #define CREG_PIPG_WMASK 0x0000000f /* SBUS Wait Mask */
128
129 /* Per-channel AMD 79C940 MACE registers. */
130 struct qe_mregs {
131 volatile unsigned char rxfifo; /* Receive FIFO */
132 volatile unsigned char txfifo; /* Transmit FIFO */
133 volatile unsigned char txfcntl; /* Transmit Frame Control */
134 volatile unsigned char txfstat; /* Transmit Frame Status */
135 volatile unsigned char txrcnt; /* Transmit Retry Count */
136 volatile unsigned char rxfcntl; /* Receive Frame Control */
137 volatile unsigned char rxfstat; /* Receive Frame Status */
138 volatile unsigned char ffcnt; /* FIFO Frame Count */
139 volatile unsigned char ireg; /* Interrupt Register */
140 volatile unsigned char imask; /* Interrupt Mask */
141 volatile unsigned char poll; /* POLL Register */
142 volatile unsigned char bconfig; /* BIU Config */
143 volatile unsigned char fconfig; /* FIFO Config */
144 volatile unsigned char mconfig; /* MAC Config */
145 volatile unsigned char plsconfig;/* PLS Config */
146 volatile unsigned char phyconfig;/* PHY Config */
147 volatile unsigned char chipid1; /* Chip-ID, low bits */
148 volatile unsigned char chipid2; /* Chip-ID, high bits */
149 volatile unsigned char iaconfig; /* Internal Address Config */
150 volatile unsigned char _unused0; /* Reserved... */
151 volatile unsigned char filter; /* Logical Address Filter */
152 volatile unsigned char ethaddr; /* Our Ethernet Address */
153 volatile unsigned char _unused1; /* Reserved... */
154 volatile unsigned char _unused2; /* Reserved... */
155 volatile unsigned char mpcnt; /* Missed Packet Count */
156 volatile unsigned char _unused3; /* Reserved... */
157 volatile unsigned char rpcnt; /* Runt Packet Count */
158 volatile unsigned char rccnt; /* RX Collision Count */
159 volatile unsigned char _unused4; /* Reserved... */
160 volatile unsigned char utest; /* User Test */
161 volatile unsigned char rtest1; /* Reserved Test 1 */
162 volatile unsigned char rtest2; /* Reserved Test 2 */
163 };
164
165 #define MREGS_TXFCNTL_DRETRY 0x80 /* Retry disable */
166 #define MREGS_TXFCNTL_DFCS 0x08 /* Disable TX FCS */
167 #define MREGS_TXFCNTL_AUTOPAD 0x01 /* TX auto pad */
168
169 #define MREGS_TXFSTAT_VALID 0x80 /* TX valid */
170 #define MREGS_TXFSTAT_UNDERFLOW 0x40 /* TX underflow */
171 #define MREGS_TXFSTAT_LCOLL 0x20 /* TX late collision */
172 #define MREGS_TXFSTAT_MRETRY 0x10 /* TX > 1 retries */
173 #define MREGS_TXFSTAT_ORETRY 0x08 /* TX 1 retry */
174 #define MREGS_TXFSTAT_PDEFER 0x04 /* TX pkt deferred */
175 #define MREGS_TXFSTAT_CLOSS 0x02 /* TX carrier lost */
176 #define MREGS_TXFSTAT_RERROR 0x01 /* TX retry error */
177
178 #define MREGS_TXRCNT_EDEFER 0x80 /* TX Excess defers */
179 #define MREGS_TXRCNT_CMASK 0x0f /* TX retry count */
180
181 #define MREGS_RXFCNTL_LOWLAT 0x08 /* RX low latency */
182 #define MREGS_RXFCNTL_AREJECT 0x04 /* RX addr match rej */
183 #define MREGS_RXFCNTL_AUTOSTRIP 0x01 /* RX auto strip */
184
185 #define MREGS_RXFSTAT_OVERFLOW 0x80 /* RX overflow */
186 #define MREGS_RXFSTAT_LCOLL 0x40 /* RX late collision */
187 #define MREGS_RXFSTAT_FERROR 0x20 /* RX framing error */
188 #define MREGS_RXFSTAT_FCSERROR 0x10 /* RX FCS error */
189 #define MREGS_RXFSTAT_RBCNT 0x0f /* RX msg byte count */
190
191 #define MREGS_FFCNT_RX 0xf0 /* RX FIFO frame cnt */
192 #define MREGS_FFCNT_TX 0x0f /* TX FIFO frame cnt */
193
194 #define MREGS_IREG_JABBER 0x80 /* IRQ Jabber error */
195 #define MREGS_IREG_BABBLE 0x40 /* IRQ Babble error */
196 #define MREGS_IREG_COLL 0x20 /* IRQ Collision error */
197 #define MREGS_IREG_RCCO 0x10 /* IRQ Collision cnt overflow */
198 #define MREGS_IREG_RPKTCO 0x08 /* IRQ Runt packet count overflow */
199 #define MREGS_IREG_MPKTCO 0x04 /* IRQ missed packet cnt overflow */
200 #define MREGS_IREG_RXIRQ 0x02 /* IRQ RX'd a packet */
201 #define MREGS_IREG_TXIRQ 0x01 /* IRQ TX'd a packet */
202
203 #define MREGS_IMASK_BABBLE 0x40 /* IMASK Babble errors */
204 #define MREGS_IMASK_COLL 0x20 /* IMASK Collision errors */
205 #define MREGS_IMASK_MPKTCO 0x04 /* IMASK Missed pkt cnt overflow */
206 #define MREGS_IMASK_RXIRQ 0x02 /* IMASK RX interrupts */
207 #define MREGS_IMASK_TXIRQ 0x01 /* IMASK TX interrupts */
208
209 #define MREGS_POLL_TXVALID 0x80 /* TX is valid */
210 #define MREGS_POLL_TDTR 0x40 /* TX data transfer request */
211 #define MREGS_POLL_RDTR 0x20 /* RX data transfer request */
212
213 #define MREGS_BCONFIG_BSWAP 0x40 /* Byte Swap */
214 #define MREGS_BCONFIG_4TS 0x00 /* 4byte transmit start point */
215 #define MREGS_BCONFIG_16TS 0x10 /* 16byte transmit start point */
216 #define MREGS_BCONFIG_64TS 0x20 /* 64byte transmit start point */
217 #define MREGS_BCONFIG_112TS 0x30 /* 112byte transmit start point */
218 #define MREGS_BCONFIG_RESET 0x01 /* SW-Reset the MACE */
219
220 #define MREGS_FCONFIG_TXF8 0x00 /* TX fifo 8 write cycles */
221 #define MREGS_FCONFIG_TXF32 0x80 /* TX fifo 32 write cycles */
222 #define MREGS_FCONFIG_TXF16 0x40 /* TX fifo 16 write cycles */
223 #define MREGS_FCONFIG_RXF64 0x20 /* RX fifo 64 write cycles */
224 #define MREGS_FCONFIG_RXF32 0x10 /* RX fifo 32 write cycles */
225 #define MREGS_FCONFIG_RXF16 0x00 /* RX fifo 16 write cycles */
226 #define MREGS_FCONFIG_TFWU 0x08 /* TX fifo watermark update */
227 #define MREGS_FCONFIG_RFWU 0x04 /* RX fifo watermark update */
228 #define MREGS_FCONFIG_TBENAB 0x02 /* TX burst enable */
229 #define MREGS_FCONFIG_RBENAB 0x01 /* RX burst enable */
230
231 #define MREGS_MCONFIG_PROMISC 0x80 /* Promiscuous mode enable */
232 #define MREGS_MCONFIG_TPDDISAB 0x40 /* TX 2part deferral enable */
233 #define MREGS_MCONFIG_MBAENAB 0x20 /* Modified backoff enable */
234 #define MREGS_MCONFIG_RPADISAB 0x08 /* RX physical addr disable */
235 #define MREGS_MCONFIG_RBDISAB 0x04 /* RX broadcast disable */
236 #define MREGS_MCONFIG_TXENAB 0x02 /* Enable transmitter */
237 #define MREGS_MCONFIG_RXENAB 0x01 /* Enable receiver */
238
239 #define MREGS_PLSCONFIG_TXMS 0x08 /* TX mode select */
240 #define MREGS_PLSCONFIG_GPSI 0x06 /* Use GPSI connector */
241 #define MREGS_PLSCONFIG_DAI 0x04 /* Use DAI connector */
242 #define MREGS_PLSCONFIG_TP 0x02 /* Use TwistedPair connector */
243 #define MREGS_PLSCONFIG_AUI 0x00 /* Use AUI connector */
244 #define MREGS_PLSCONFIG_IOENAB 0x01 /* PLS I/O enable */
245
246 #define MREGS_PHYCONFIG_LSTAT 0x80 /* Link status */
247 #define MREGS_PHYCONFIG_LTESTDIS 0x40 /* Disable link test logic */
248 #define MREGS_PHYCONFIG_RXPOLARITY 0x20 /* RX polarity */
249 #define MREGS_PHYCONFIG_APCDISAB 0x10 /* AutoPolarityCorrect disab */
250 #define MREGS_PHYCONFIG_LTENAB 0x08 /* Select low threshold */
251 #define MREGS_PHYCONFIG_AUTO 0x04 /* Connector port auto-sel */
252 #define MREGS_PHYCONFIG_RWU 0x02 /* Remote WakeUp */
253 #define MREGS_PHYCONFIG_AW 0x01 /* Auto Wakeup */
254
255 #define MREGS_IACONFIG_ACHNGE 0x80 /* Do address change */
256 #define MREGS_IACONFIG_PARESET 0x04 /* Physical address reset */
257 #define MREGS_IACONFIG_LARESET 0x02 /* Logical address reset */
258
259 #define MREGS_UTEST_RTRENAB 0x80 /* Enable resv test register */
260 #define MREGS_UTEST_RTRDISAB 0x40 /* Disab resv test register */
261 #define MREGS_UTEST_RPACCEPT 0x20 /* Accept runt packets */
262 #define MREGS_UTEST_FCOLL 0x10 /* Force collision status */
263 #define MREGS_UTEST_FCSENAB 0x08 /* Enable FCS on RX */
264 #define MREGS_UTEST_INTLOOPM 0x06 /* Intern lpback w/MENDEC */
265 #define MREGS_UTEST_INTLOOP 0x04 /* Intern lpback */
266 #define MREGS_UTEST_EXTLOOP 0x02 /* Extern lpback */
267 #define MREGS_UTEST_NOLOOP 0x00 /* No loopback */
268
269 struct qe_rxd {
270 unsigned int rx_flags;
271 unsigned int rx_addr;
272 };
273
274 #define RXD_OWN 0x80000000 /* Ownership. */
275 #define RXD_UPDATE 0x10000000 /* Being Updated? */
276 #define RXD_LENGTH 0x000007ff /* Packet Length. */
277
278 struct qe_txd {
279 unsigned int tx_flags;
280 unsigned int tx_addr;
281 };
282
283 #define TXD_OWN 0x80000000 /* Ownership. */
284 #define TXD_SOP 0x40000000 /* Start Of Packet */
285 #define TXD_EOP 0x20000000 /* End Of Packet */
286 #define TXD_UPDATE 0x10000000 /* Being Updated? */
287 #define TXD_LENGTH 0x000007ff /* Packet Length. */
288
289 #define TX_RING_MAXSIZE 256
290 #define RX_RING_MAXSIZE 256
291
292 #define TX_RING_SIZE 256
293 #define RX_RING_SIZE 256
294
295 #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
296 #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
297 #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
298 #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
299
300 #define TX_BUFFS_AVAIL(qp) \
301 (((qp)->tx_old <= (qp)->tx_new) ? \
302 (qp)->tx_old + (TX_RING_SIZE - 1) - (qp)->tx_new : \
303 (qp)->tx_old - (qp)->tx_new - 1)
304
305
306 #define SUN4C_TX_BUFFS_AVAIL(qp) \
307 (((qp)->tx_old <= (qp)->tx_new) ? \
308 (qp)->tx_old + (SUN4C_TX_RING_SIZE - 1) - (qp)->tx_new : \
309 (qp)->tx_old - (qp)->tx_new - (TX_RING_SIZE - SUN4C_TX_RING_SIZE))
310
311
312 #define RX_COPY_THRESHOLD 256
313 #define RX_BUF_ALLOC_SIZE (1546 + 64)
314
315 struct qe_init_block {
316 struct qe_rxd qe_rxd[RX_RING_MAXSIZE];
317 struct qe_txd qe_txd[TX_RING_MAXSIZE];
318 };
319
320 #define qib_offset(mem, elem) \
321 ((__u32)((unsigned long)(&(((struct qe_init_block *)0)->mem[elem]))))
322
323 struct sunqe;
324
325 struct sunqec {
326 struct qe_globreg *gregs; /* QEC Global Registers */
327
328 struct sunqe *qes[4];
329 unsigned int qec_bursts;
330 struct linux_sbus_device *qec_sbus_dev;
331 struct sunqec *next_module;
332 };
333
334 #define SUN4C_PKT_BUF_SZ 1544
335 #define SUN4C_RX_BUFF_SIZE SUN4C_PKT_BUF_SZ
336 #define SUN4C_TX_BUFF_SIZE SUN4C_PKT_BUF_SZ
337
338 #define SUN4C_RX_RING_SIZE 16
339 #define SUN4C_TX_RING_SIZE 16
340
341 struct sunqe_buffers {
342 char tx_buf[SUN4C_TX_RING_SIZE][SUN4C_TX_BUFF_SIZE];
343 char pad[2]; /* Align rx_buf for copy_and_sum(). */
344 char rx_buf[SUN4C_RX_RING_SIZE][SUN4C_RX_BUFF_SIZE];
345 };
346
347 #define qebuf_offset(mem, elem) \
348 ((__u32)((unsigned long)(&(((struct sunqe_buffers *)0)->mem[elem][0]))))
349
350 #define SUN4C_NEXT_RX(num) (((num) + 1) & (SUN4C_RX_RING_SIZE - 1))
351 #define SUN4C_NEXT_TX(num) (((num) + 1) & (SUN4C_TX_RING_SIZE - 1))
352 #define SUN4C_PREV_RX(num) (((num) - 1) & (SUN4C_RX_RING_SIZE - 1))
353 #define SUN4C_PREV_TX(num) (((num) - 1) & (SUN4C_TX_RING_SIZE - 1))
354
355 struct sunqe {
356 struct qe_creg *qcregs; /* QEC per-channel Registers */
357 struct qe_mregs *mregs; /* Per-channel MACE Registers */
358 struct qe_init_block *qe_block; /* RX and TX descriptors */
359 __u32 qblock_dvma; /* RX and TX descriptors */
360
361 struct sk_buff *rx_skbs[RX_RING_SIZE];
362 struct sk_buff *tx_skbs[TX_RING_SIZE];
363
364 int rx_new, tx_new, rx_old, tx_old;
365
366 struct sunqe_buffers *sun4c_buffers; /* CPU visible address. */
367 __u32 s4c_buf_dvma; /* DVMA visible address. */
368
369 struct sunqec *parent;
370
371 struct net_device_stats net_stats; /* Statistical counters */
372 struct linux_sbus_device *qe_sbusdev; /* QE's SBUS device struct */
373 struct net_device *dev; /* QE's netdevice struct */
374 int channel; /* Who am I? */
375 };
376
377 /* We use this to acquire receive skb's that we can DMA directly into. */
378 #define ALIGNED_RX_SKB_ADDR(addr) \
379 ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
380
381 static inline struct sk_buff *qe_alloc_skb(unsigned int length, int gfp_flags)
382 {
383 struct sk_buff *skb;
384
385 skb = alloc_skb(length + 64, gfp_flags);
386 if(skb) {
387 int offset = ALIGNED_RX_SKB_ADDR(skb->data);
388
389 if(offset)
390 skb_reserve(skb, offset);
391 }
392 return skb;
393 }
394
395 #endif /* !(_SUNQE_H) */
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