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Import 2.3.18pre1
[davej-history.git] / drivers / net / sunbmac.h
blob15c691acd5c7633517ffc8dec520211d9da6c9fa
1 /* sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
2 *
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4 */
5
6 #ifndef _SUNBMAC_H
7 #define _SUNBMAC_H
8
9 /* QEC global registers. */
10 struct qe_globreg {
11 volatile unsigned int ctrl; /* Control */
12 volatile unsigned int stat; /* Status */
13 volatile unsigned int psize; /* Packet Size */
14 volatile unsigned int msize; /* Local-mem size (64K) */
15 volatile unsigned int rsize; /* Receive partition size */
16 volatile unsigned int tsize; /* Transmit partition size */
17 };
18
19 #define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
20 #define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
21 #define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
22 #define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */
23 #define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
24 #define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
25 #define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
26 #define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */
27
28 #define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
29 #define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
30 #define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */
31 #define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */
32
33 #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
34 #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
35 #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
36 #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
37
38 /* QEC BigMAC channel registers. */
39 struct qe_creg {
40 volatile unsigned int ctrl; /* Control */
41 volatile unsigned int stat; /* Status */
42 volatile unsigned int rxds; /* RX descriptor ring ptr */
43 volatile unsigned int txds; /* TX descriptor ring ptr */
44 volatile unsigned int rimask; /* RX Interrupt Mask */
45 volatile unsigned int timask; /* TX Interrupt Mask */
46 volatile unsigned int qmask; /* QEC Error Interrupt Mask */
47 volatile unsigned int bmask; /* BigMAC Error Interrupt Mask */
48 volatile unsigned int rxwbufptr; /* Local memory rx write ptr */
49 volatile unsigned int rxrbufptr; /* Local memory rx read ptr */
50 volatile unsigned int txwbufptr; /* Local memory tx write ptr */
51 volatile unsigned int txrbufptr; /* Local memory tx read ptr */
52 volatile unsigned int ccnt; /* Collision Counter */
53 };
54
55 #define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */
56
57 #define CREG_STAT_BERROR 0x80000000 /* BigMAC error */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
59 #define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
60 #define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
61 #define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
62 #define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
64 #define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
65 #define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
66 #define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
67 #define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
68 #define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
69
70 #define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \
71 CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \
72 CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \
73 CREG_STAT_RXSERR)
74
75 #define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */
76 #define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
77 #define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
78 #define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
79 #define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
80 #define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
81 #define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
82 #define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
83 #define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
84
85 struct BIG_MAC_regs {
86 volatile unsigned int xif_cfg; /* XIF config register */
87 volatile unsigned int _unused[63]; /* Reserved... */
88 volatile unsigned int status; /* Status register, clear on read */
89 volatile unsigned int imask; /* Interrupt mask register */
90 volatile unsigned int _unused2[64]; /* Reserved... */
91 volatile unsigned int tx_swreset; /* Transmitter software reset */
92 volatile unsigned int tx_cfg; /* Transmitter config register */
93 volatile unsigned int ipkt_gap1; /* Inter-packet gap 1 */
94 volatile unsigned int ipkt_gap2; /* Inter-packet gap 2 */
95 volatile unsigned int attempt_limit; /* Transmit attempt limit */
96 volatile unsigned int stime; /* Transmit slot time */
97 volatile unsigned int preamble_len; /* Size of transmit preamble */
98 volatile unsigned int preamble_pattern; /* Pattern for transmit preamble */
99 volatile unsigned int tx_sframe_delim; /* Transmit delimiter */
100 volatile unsigned int jsize; /* Toe jam... */
101 volatile unsigned int tx_pkt_max; /* Transmit max pkt size */
102 volatile unsigned int tx_pkt_min; /* Transmit min pkt size */
103 volatile unsigned int peak_attempt; /* Count of transmit peak attempts */
104 volatile unsigned int dt_ctr; /* Transmit defer timer */
105 volatile unsigned int nc_ctr; /* Transmit normal-collision counter */
106 volatile unsigned int fc_ctr; /* Transmit first-collision counter */
107 volatile unsigned int ex_ctr; /* Transmit excess-collision counter */
108 volatile unsigned int lt_ctr; /* Transmit late-collision counter */
109 volatile unsigned int rand_seed; /* Transmit random number seed */
110 volatile unsigned int tx_smachine; /* Transmit state machine */
111 volatile unsigned int _unused3[44]; /* Reserved */
112 volatile unsigned int rx_swreset; /* Receiver software reset */
113 volatile unsigned int rx_cfg; /* Receiver config register */
114 volatile unsigned int rx_pkt_max; /* Receive max pkt size */
115 volatile unsigned int rx_pkt_min; /* Receive min pkt size */
116 volatile unsigned int mac_addr2; /* Ether address register 2 */
117 volatile unsigned int mac_addr1; /* Ether address register 1 */
118 volatile unsigned int mac_addr0; /* Ether address register 0 */
119 volatile unsigned int fr_ctr; /* Receive frame receive counter */
120 volatile unsigned int gle_ctr; /* Receive giant-length error counter */
121 volatile unsigned int unale_ctr; /* Receive unaligned error counter */
122 volatile unsigned int rcrce_ctr; /* Receive CRC error counter */
123 volatile unsigned int rx_smachine; /* Receiver state machine */
124 volatile unsigned int rx_cvalid; /* Receiver code violation */
125 volatile unsigned int _unused4; /* Reserved... */
126 volatile unsigned int htable3; /* Hash table 3 */
127 volatile unsigned int htable2; /* Hash table 2 */
128 volatile unsigned int htable1; /* Hash table 1 */
129 volatile unsigned int htable0; /* Hash table 0 */
130 volatile unsigned int afilter2; /* Address filter 2 */
131 volatile unsigned int afilter1; /* Address filter 1 */
132 volatile unsigned int afilter0; /* Address filter 0 */
133 volatile unsigned int afilter_mask; /* Address filter mask */
134 };
135
136 /* BigMac XIF config register. */
137 #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
138 #define BIGMAC_XCFG_RESV 0x00000002 /* Reserved, write always as 1 */
139 #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
140 #define BIGMAC_XCFG_SMODE 0x00000008 /* Enable serial mode */
141
142 /* BigMAC status register. */
143 #define BIGMAC_STAT_GOTFRAME 0x00000001 /* Received a frame */
144 #define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
145 #define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
146 #define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
147 #define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
148 #define BIGMAC_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
149 #define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
150 #define BIGMAC_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
151 #define BIGMAC_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
152 #define BIGMAC_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
153 #define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
154 #define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
155 #define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
156 #define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
157 #define BIGMAC_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
158
159 /* BigMAC interrupt mask register. */
160 #define BIGMAC_IMASK_GOTFRAME 0x00000001 /* Received a frame */
161 #define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
162 #define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
163 #define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
164 #define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
165 #define BIGMAC_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
166 #define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
167 #define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
168 #define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
169 #define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
170 #define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
171 #define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
172 #define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
173 #define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
174 #define BIGMAC_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
175
176 /* BigMac transmit config register. */
177 #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
178 #define BIGMAC_TXCFG_FIFO 0x00000010 /* Default tx fthresh... */
179 #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
180 #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
181 #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
182 #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
183 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
184
185 /* BigMac receive config register. */
186 #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
187 #define BIGMAC_RXCFG_FIFO 0x0000000e /* Default rx fthresh... */
188 #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
189 #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
190 #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
191 #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
192 #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
193 #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
194 #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
195 #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
196
197 /* The BigMAC PHY transceiver. Not nearly as sophisticated as the happy meal
198 * one. But it does have the "bit banger", oh baby.
199 */
200 struct bmac_tcvr {
201 unsigned int tcvr_pal;
202 unsigned int mgmt_pal;
203 };
204
205 /* Frame commands. */
206 #define FRAME_WRITE 0x50020000
207 #define FRAME_READ 0x60020000
208
209 /* Tranceiver registers. */
210 #define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */
211 #define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */
212 #define TCVR_PAL_MSENSE 0x00000004 /* Media sense */
213 #define TCVR_PAL_LTENABLE 0x00000008 /* Link test enable */
214 #define TCVR_PAL_LTSTATUS 0x00000010 /* Link test status (P1 only) */
215
216 /* Management PAL. */
217 #define MGMT_PAL_DCLOCK 0x00000001 /* Data clock */
218 #define MGMT_PAL_OENAB 0x00000002 /* Output enabler */
219 #define MGMT_PAL_MDIO 0x00000004 /* MDIO Data/attached */
220 #define MGMT_PAL_TIMEO 0x00000008 /* Transmit enable timeout error */
221 #define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO
222 #define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO
223
224 /* Here are some PHY addresses. */
225 #define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */
226 #define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */
227
228 /* PHY registers */
229 #define BIGMAC_BMCR 0x00 /* Basic mode control register */
230 #define BIGMAC_BMSR 0x01 /* Basic mode status register */
231
232 /* BMCR bits */
233 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
234 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
235 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
236 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
237 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
238 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
239
240 /* BMSR bits */
241 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
242 #define BMSR_JCD 0x0002 /* Jabber detected */
243 #define BMSR_LSTATUS 0x0004 /* Link status */
244
245 /* Ring descriptors and such, same as Quad Ethernet. */
246 struct be_rxd {
247 unsigned int rx_flags;
248 unsigned int rx_addr;
249 };
250
251 #define RXD_OWN 0x80000000 /* Ownership. */
252 #define RXD_UPDATE 0x10000000 /* Being Updated? */
253 #define RXD_LENGTH 0x000007ff /* Packet Length. */
254
255 struct be_txd {
256 unsigned int tx_flags;
257 unsigned int tx_addr;
258 };
259
260 #define TXD_OWN 0x80000000 /* Ownership. */
261 #define TXD_SOP 0x40000000 /* Start Of Packet */
262 #define TXD_EOP 0x20000000 /* End Of Packet */
263 #define TXD_UPDATE 0x10000000 /* Being Updated? */
264 #define TXD_LENGTH 0x000007ff /* Packet Length. */
265
266 #define TX_RING_MAXSIZE 256
267 #define RX_RING_MAXSIZE 256
268
269 #define TX_RING_SIZE 256
270 #define RX_RING_SIZE 256
271
272 #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
273 #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
274 #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
275 #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
276
277 #define TX_BUFFS_AVAIL(bp) \
278 (((bp)->tx_old <= (bp)->tx_new) ? \
279 (bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \
280 (bp)->tx_old - (bp)->tx_new - 1)
281
282
283 #define SUN4C_TX_BUFFS_AVAIL(bp) \
284 (((bp)->tx_old <= (bp)->tx_new) ? \
285 (bp)->tx_old + (SUN4C_TX_RING_SIZE - 1) - (bp)->tx_new : \
286 (bp)->tx_old - (bp)->tx_new - (TX_RING_SIZE - SUN4C_TX_RING_SIZE))
287
288
289 #define RX_COPY_THRESHOLD 128
290 #define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3))
291
292 struct bmac_init_block {
293 struct be_rxd be_rxd[RX_RING_MAXSIZE];
294 struct be_txd be_txd[TX_RING_MAXSIZE];
295 };
296
297 #define bib_offset(mem, elem) \
298 ((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
299
300 #define SUN4C_PKT_BUF_SZ 1546
301 #define SUN4C_RX_BUFF_SIZE SUN4C_PKT_BUF_SZ
302 #define SUN4C_TX_BUFF_SIZE SUN4C_PKT_BUF_SZ
303
304 #define SUN4C_RX_RING_SIZE 16
305 #define SUN4C_TX_RING_SIZE 16
306
307 struct bigmac_buffers {
308 char tx_buf[SUN4C_TX_RING_SIZE][SUN4C_TX_BUFF_SIZE];
309 char pad[2]; /* Align rx_buf for copy_and_sum(). */
310 char rx_buf[SUN4C_RX_RING_SIZE][SUN4C_RX_BUFF_SIZE];
311 };
312
313 #define bbuf_offset(mem, elem) \
314 ((__u32)((unsigned long)(&(((struct bigmac_buffers *)0)->mem[elem][0]))))
315
316 /* Now software state stuff. */
317 enum bigmac_transceiver {
318 external = 0,
319 internal = 1,
320 none = 2,
321 };
322
323 /* Timer state engine. */
324 enum bigmac_timer_state {
325 ltrywait = 1, /* Forcing try of all modes, from fastest to slowest. */
326 asleep = 2, /* Timer inactive. */
327 };
328
329 struct bigmac {
330 struct qe_globreg *gregs; /* QEC Global Registers */
331 struct qe_creg *creg; /* QEC BigMAC Channel Registers */
332 struct BIG_MAC_regs *bregs; /* BigMAC Registers */
333 struct bmac_tcvr *tregs; /* BigMAC Transceiver */
334 struct bmac_init_block *bmac_block; /* RX and TX descriptors */
335 __u32 bblock_dvma; /* RX and TX descriptors */
336
337 struct sk_buff *rx_skbs[RX_RING_SIZE];
338 struct sk_buff *tx_skbs[TX_RING_SIZE];
339
340 int rx_new, tx_new, rx_old, tx_old;
341
342 struct bigmac_buffers *sun4c_buffers;
343 __u32 s4c_buf_dvma;
344
345 int board_rev; /* BigMAC board revision. */
346
347 enum bigmac_transceiver tcvr_type;
348 unsigned int bigmac_bursts;
349 unsigned int paddr;
350 unsigned short sw_bmsr; /* SW copy of PHY BMSR */
351 unsigned short sw_bmcr; /* SW copy of PHY BMCR */
352 struct timer_list bigmac_timer;
353 enum bigmac_timer_state timer_state;
354 unsigned int timer_ticks;
355
356 struct enet_statistics enet_stats;
357 struct linux_sbus_device *qec_sbus_dev;
358 struct linux_sbus_device *bigmac_sbus_dev;
359 struct net_device *dev;
360 struct bigmac *next_module;
361 };
362
363 /* We use this to acquire receive skb's that we can DMA directly into. */
364 #define ALIGNED_RX_SKB_ADDR(addr) \
365 ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
366
367 static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, int gfp_flags)
368 {
369 struct sk_buff *skb;
370
371 skb = alloc_skb(length + 64, gfp_flags);
372 if(skb) {
373 int offset = ALIGNED_RX_SKB_ADDR(skb->data);
374
375 if(offset)
376 skb_reserve(skb, offset);
377 }
378 return skb;
379 }
380
381 #endif /* !(_SUNBMAC_H) */
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