?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Import 2.3.18pre1
[davej-history.git] / drivers / net / bmac.c
bloba40d2c1434fd028dc93a77252640220e250948d3
1 /*
2 * Network device driver for the BMAC ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
4 *
5 * Copyright (C) 1998 Randy Gobbel.
6 */
7 #include <linux/config.h>
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/delay.h>
13 #include <linux/string.h>
14 #include <linux/timer.h>
15 #include <linux/proc_fs.h>
16 #include <asm/prom.h>
17 #include <asm/dbdma.h>
18 #include <asm/io.h>
19 #include <asm/page.h>
20 #include <asm/pgtable.h>
21 #include <asm/feature.h>
22 #include "bmac.h"
23
24 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
25 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
26
27 /*
28 * CRC polynomial - used in working out multicast filter bits.
29 */
30 #define ENET_CRCPOLY 0x04c11db7
31
32 /* switch to use multicast code lifted from sunhme driver */
33 #define SUNHME_MULTICAST
34
35 #define N_RX_RING 64
36 #define N_TX_RING 32
37 #define MAX_TX_ACTIVE 1
38 #define ETHERCRC 4
39 #define ETHERMINPACKET 64
40 #define ETHERMTU 1500
41 #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
42 #define TX_TIMEOUT HZ /* 1 second */
43
44 /* Bits in transmit DMA status */
45 #define TX_DMA_ERR 0x80
46
47 #define XXDEBUG(args)
48
49 struct bmac_data {
50 /* volatile struct bmac *bmac; */
51 struct sk_buff_head *queue;
52 volatile struct dbdma_regs *tx_dma;
53 int tx_dma_intr;
54 volatile struct dbdma_regs *rx_dma;
55 int rx_dma_intr;
56 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
57 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
58 struct device_node *node;
59 struct sk_buff *rx_bufs[N_RX_RING];
60 int rx_fill;
61 int rx_empty;
62 struct sk_buff *tx_bufs[N_TX_RING];
63 int tx_fill;
64 int tx_empty;
65 unsigned char tx_fullup;
66 struct net_device_stats stats;
67 struct timer_list tx_timeout;
68 int timeout_active;
69 int reset_and_enabled;
70 int rx_allocated;
71 int tx_allocated;
72 unsigned short hash_use_count[64];
73 unsigned short hash_table_mask[4];
74 };
75
76 typedef struct bmac_reg_entry {
77 char *name;
78 unsigned short reg_offset;
79 } bmac_reg_entry_t;
80
81 #define N_REG_ENTRIES 31
82
83 bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
84 {"MEMADD", MEMADD},
85 {"MEMDATAHI", MEMDATAHI},
86 {"MEMDATALO", MEMDATALO},
87 {"TXPNTR", TXPNTR},
88 {"RXPNTR", RXPNTR},
89 {"IPG1", IPG1},
90 {"IPG2", IPG2},
91 {"ALIMIT", ALIMIT},
92 {"SLOT", SLOT},
93 {"PALEN", PALEN},
94 {"PAPAT", PAPAT},
95 {"TXSFD", TXSFD},
96 {"JAM", JAM},
97 {"TXCFG", TXCFG},
98 {"TXMAX", TXMAX},
99 {"TXMIN", TXMIN},
100 {"PAREG", PAREG},
101 {"DCNT", DCNT},
102 {"NCCNT", NCCNT},
103 {"NTCNT", NTCNT},
104 {"EXCNT", EXCNT},
105 {"LTCNT", LTCNT},
106 {"TXSM", TXSM},
107 {"RXCFG", RXCFG},
108 {"RXMAX", RXMAX},
109 {"RXMIN", RXMIN},
110 {"FRCNT", FRCNT},
111 {"AECNT", AECNT},
112 {"FECNT", FECNT},
113 {"RXSM", RXSM},
114 {"RXCV", RXCV}
115 };
116
117 struct net_device *bmac_devs = NULL;
118 static int is_bmac_plus;
119
120 #if 0
121 /*
122 * If we can't get a skbuff when we need it, we use this area for DMA.
123 */
124 static unsigned char dummy_buf[RX_BUFLEN];
125 #endif
126
127 /*
128 * Number of bytes of private data per BMAC: allow enough for
129 * the rx and tx dma commands plus a branch dma command each,
130 * and another 16 bytes to allow us to align the dma command
131 * buffers on a 16 byte boundary.
132 */
133 #define PRIV_BYTES (sizeof(struct bmac_data) \
134 + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
135 + sizeof(struct sk_buff_head))
136
137 static unsigned char bitrev(unsigned char b);
138 static int bmac_open(struct net_device *dev);
139 static int bmac_close(struct net_device *dev);
140 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
141 static struct net_device_stats *bmac_stats(struct net_device *dev);
142 static void bmac_set_multicast(struct net_device *dev);
143 static int bmac_reset_and_enable(struct net_device *dev, int enable);
144 static void bmac_start_chip(struct net_device *dev);
145 static int bmac_init_chip(struct net_device *dev);
146 static void bmac_init_registers(struct net_device *dev);
147 static void bmac_reset_chip(struct net_device *dev);
148 static int bmac_set_address(struct net_device *dev, void *addr);
149 static void bmac_misc_intr(int irq, void *dev_id, struct pt_regs *regs);
150 static void bmac_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
151 static void bmac_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);
152 static void bmac_set_timeout(struct net_device *dev);
153 static void bmac_tx_timeout(unsigned long data);
154 static int bmac_proc_info ( char *buffer, char **start, off_t offset, int length, int dummy);
155 static int bmac_output(struct sk_buff *skb, struct net_device *dev);
156 static void bmac_start(struct net_device *dev);
157
158 #define DBDMA_SET(x) ( ((x) | (x) << 16) )
159 #define DBDMA_CLEAR(x) ( (x) << 16)
160
161 static __inline__ void
162 dbdma_st32(volatile unsigned long *a, unsigned long x)
163 {
164 __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
165 return;
166 }
167
168 static __inline__ unsigned long
169 dbdma_ld32(volatile unsigned long *a)
170 {
171 unsigned long swap;
172 __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
173 return swap;
174 }
175
176 void
177 dbdma_stop(volatile struct dbdma_regs *dmap)
178 {
179 dbdma_st32((volatile unsigned long *)&dmap->control, DBDMA_CLEAR(RUN) | DBDMA_SET(FLUSH));
180 eieio();
181
182 while (dbdma_ld32((volatile unsigned long *)&dmap->status) & (ACTIVE|FLUSH))
183 eieio();
184 }
185
186 static void
187 dbdma_continue(volatile struct dbdma_regs *dmap)
188 {
189 dbdma_st32((volatile unsigned long *)&dmap->control,
190 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
191 eieio();
192 }
193
194 static void
195 dbdma_reset(volatile struct dbdma_regs *dmap)
196 {
197 dbdma_st32((volatile unsigned long *)&dmap->control,
198 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
199 eieio();
200 while (dbdma_ld32((volatile unsigned long *)&dmap->status) & RUN) eieio();
201 }
202
203 static void
204 dbdma_setcmd(volatile struct dbdma_cmd *cp,
205 unsigned short cmd, unsigned count, unsigned long addr,
206 unsigned long cmd_dep)
207 {
208 out_le16(&cp->command, cmd);
209 out_le16(&cp->req_count, count);
210 out_le32(&cp->phy_addr, addr);
211 out_le32(&cp->cmd_dep, cmd_dep);
212 out_le16(&cp->xfer_status, 0);
213 out_le16(&cp->res_count, 0);
214 }
215
216 static __inline__
217 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
218 {
219 out_le16((void *)dev->base_addr + reg_offset, data);
220 }
221
222
223 static __inline__
224 volatile unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
225 {
226 return in_le16((void *)dev->base_addr + reg_offset);
227 }
228
229 static void
230 bmac_reset_chip(struct net_device *dev)
231 {
232 struct bmac_data *bp = (struct bmac_data *) dev->priv;
233 volatile struct dbdma_regs *rd = bp->rx_dma;
234 volatile struct dbdma_regs *td = bp->tx_dma;
235
236 dbdma_reset(rd);
237 dbdma_reset(td);
238
239 feature_set(bp->node, FEATURE_BMac_IO_enable);
240 udelay(10000);
241 feature_set(bp->node, FEATURE_BMac_reset);
242 udelay(10000);
243 feature_clear(bp->node, FEATURE_BMac_reset);
244 udelay(10000);
245 }
246
247 #define MIFDELAY udelay(500)
248
249 static unsigned int
250 bmac_mif_readbits(struct net_device *dev, int nb)
251 {
252 unsigned int val = 0;
253
254 while (--nb >= 0) {
255 bmwrite(dev, MIFCSR, 0);
256 MIFDELAY;
257 if (bmread(dev, MIFCSR) & 8)
258 val |= 1 << nb;
259 bmwrite(dev, MIFCSR, 1);
260 MIFDELAY;
261 }
262 bmwrite(dev, MIFCSR, 0);
263 MIFDELAY;
264 bmwrite(dev, MIFCSR, 1);
265 MIFDELAY;
266 return val;
267 }
268
269 static void
270 bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
271 {
272 int b;
273
274 while (--nb >= 0) {
275 b = (val & (1 << nb))? 6: 4;
276 bmwrite(dev, MIFCSR, b);
277 MIFDELAY;
278 bmwrite(dev, MIFCSR, b|1);
279 MIFDELAY;
280 }
281 }
282
283 static unsigned int
284 bmac_mif_read(struct net_device *dev, unsigned int addr)
285 {
286 unsigned int val;
287
288 bmwrite(dev, MIFCSR, 4);
289 MIFDELAY;
290 bmac_mif_writebits(dev, ~0U, 32);
291 bmac_mif_writebits(dev, 6, 4);
292 bmac_mif_writebits(dev, addr, 10);
293 bmwrite(dev, MIFCSR, 2);
294 MIFDELAY;
295 bmwrite(dev, MIFCSR, 1);
296 MIFDELAY;
297 val = bmac_mif_readbits(dev, 17);
298 bmwrite(dev, MIFCSR, 4);
299 MIFDELAY;
300 return val;
301 }
302
303 static void
304 bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
305 {
306 bmwrite(dev, MIFCSR, 4);
307 MIFDELAY;
308 bmac_mif_writebits(dev, ~0U, 32);
309 bmac_mif_writebits(dev, 5, 4);
310 bmac_mif_writebits(dev, addr, 10);
311 bmac_mif_writebits(dev, 2, 2);
312 bmac_mif_writebits(dev, val, 16);
313 bmac_mif_writebits(dev, 3, 2);
314 }
315
316 static void
317 bmac_init_registers(struct net_device *dev)
318 {
319 struct bmac_data *bp = (struct bmac_data *) dev->priv;
320 volatile unsigned short regValue;
321 unsigned short *pWord16;
322 int i;
323
324 /* XXDEBUG(("bmac: enter init_registers\n")); */
325
326 bmwrite(dev, RXRST, RxResetValue);
327 bmwrite(dev, TXRST, TxResetBit);
328
329 i = 100;
330 do {
331 --i;
332 udelay(10000);
333 regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
334 } while ((regValue & TxResetBit) && i > 0);
335
336 if (!is_bmac_plus) {
337 regValue = bmread(dev, XCVRIF);
338 regValue |= ClkBit | SerialMode | COLActiveLow;
339 bmwrite(dev, XCVRIF, regValue);
340 udelay(10000);
341 }
342
343 bmwrite(dev, RSEED, (unsigned short)0x1968);
344
345 regValue = bmread(dev, XIFC);
346 regValue |= TxOutputEnable;
347 bmwrite(dev, XIFC, regValue);
348
349 bmread(dev, PAREG);
350
351 /* set collision counters to 0 */
352 bmwrite(dev, NCCNT, 0);
353 bmwrite(dev, NTCNT, 0);
354 bmwrite(dev, EXCNT, 0);
355 bmwrite(dev, LTCNT, 0);
356
357 /* set rx counters to 0 */
358 bmwrite(dev, FRCNT, 0);
359 bmwrite(dev, LECNT, 0);
360 bmwrite(dev, AECNT, 0);
361 bmwrite(dev, FECNT, 0);
362 bmwrite(dev, RXCV, 0);
363
364 /* set tx fifo information */
365 bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
366
367 bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
368 bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
369
370 /* set rx fifo information */
371 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
372 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
373
374 //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
375 bmread(dev, STATUS); /* read it just to clear it */
376
377 /* zero out the chip Hash Filter registers */
378 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
379 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
380 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
381 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
382 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
383
384 pWord16 = (unsigned short *)dev->dev_addr;
385 bmwrite(dev, MADD0, *pWord16++);
386 bmwrite(dev, MADD1, *pWord16++);
387 bmwrite(dev, MADD2, *pWord16);
388
389 bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
390
391 bmwrite(dev, INTDISABLE, EnableNormal);
392
393 return;
394 }
395
396 #if 0
397 static void
398 bmac_disable_interrupts(struct net_device *dev)
399 {
400 bmwrite(dev, INTDISABLE, DisableAll);
401 }
402
403 static void
404 bmac_enable_interrupts(struct net_device *dev)
405 {
406 bmwrite(dev, INTDISABLE, EnableNormal);
407 }
408 #endif
409
410
411 static void
412 bmac_start_chip(struct net_device *dev)
413 {
414 struct bmac_data *bp = (struct bmac_data *) dev->priv;
415 volatile struct dbdma_regs *rd = bp->rx_dma;
416 unsigned short oldConfig;
417
418 /* enable rx dma channel */
419 dbdma_continue(rd);
420
421 oldConfig = bmread(dev, TXCFG);
422 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
423
424 /* turn on rx plus any other bits already on (promiscuous possibly) */
425 oldConfig = bmread(dev, RXCFG);
426 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
427 udelay(20000);
428 }
429
430 static int
431 bmac_init_chip(struct net_device *dev)
432 {
433 unsigned int addr;
434
435 printk(KERN_DEBUG "phy registers:");
436 for (addr = 0; addr < 32; ++addr) {
437 if ((addr & 7) == 0)
438 printk("\n" KERN_DEBUG);
439 printk(" %.4x", bmac_mif_read(dev, addr));
440 }
441 printk("\n");
442 if (is_bmac_plus) {
443 unsigned int capable, ctrl;
444
445 ctrl = bmac_mif_read(dev, 0);
446 capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
447 if (bmac_mif_read(dev, 4) != capable
448 || (ctrl & 0x1000) == 0) {
449 bmac_mif_write(dev, 4, capable);
450 bmac_mif_write(dev, 0, 0x1200);
451 } else
452 bmac_mif_write(dev, 0, 0x1000);
453 }
454 bmac_init_registers(dev);
455 return 1;
456 }
457
458 static int bmac_set_address(struct net_device *dev, void *addr)
459 {
460 unsigned char *p = addr;
461 unsigned short *pWord16;
462 unsigned long flags;
463 int i;
464
465 XXDEBUG(("bmac: enter set_address\n"));
466 save_flags(flags); cli();
467
468 for (i = 0; i < 6; ++i) {
469 dev->dev_addr[i] = p[i];
470 }
471 /* load up the hardware address */
472 pWord16 = (unsigned short *)dev->dev_addr;
473 bmwrite(dev, MADD0, *pWord16++);
474 bmwrite(dev, MADD1, *pWord16++);
475 bmwrite(dev, MADD2, *pWord16);
476
477 restore_flags(flags);
478 XXDEBUG(("bmac: exit set_address\n"));
479 return 0;
480 }
481
482 static inline void bmac_set_timeout(struct net_device *dev)
483 {
484 struct bmac_data *bp = (struct bmac_data *) dev->priv;
485 unsigned long flags;
486
487 save_flags(flags);
488 cli();
489 if (bp->timeout_active)
490 del_timer(&bp->tx_timeout);
491 bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
492 bp->tx_timeout.function = bmac_tx_timeout;
493 bp->tx_timeout.data = (unsigned long) dev;
494 add_timer(&bp->tx_timeout);
495 bp->timeout_active = 1;
496 restore_flags(flags);
497 }
498
499 static void
500 bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
501 {
502 void *vaddr;
503 unsigned long baddr;
504 unsigned long len;
505
506 len = skb->len;
507 vaddr = skb->data;
508 baddr = virt_to_bus(vaddr);
509
510 dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
511 }
512
513 static void
514 bmac_construct_rxbuff(unsigned char *addr, volatile struct dbdma_cmd *cp)
515 {
516 dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN, virt_to_bus(addr), 0);
517 }
518
519 /* Bit-reverse one byte of an ethernet hardware address. */
520 static unsigned char
521 bitrev(unsigned char b)
522 {
523 int d = 0, i;
524
525 for (i = 0; i < 8; ++i, b >>= 1)
526 d = (d << 1) | (b & 1);
527 return d;
528 }
529
530
531 static int
532 bmac_init_tx_ring(struct bmac_data *bp)
533 {
534 volatile struct dbdma_regs *td = bp->tx_dma;
535
536 memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
537
538 bp->tx_empty = 0;
539 bp->tx_fill = 0;
540 bp->tx_fullup = 0;
541
542 /* put a branch at the end of the tx command list */
543 dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
544 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
545
546 /* reset tx dma */
547 dbdma_reset(td);
548 out_le32(&td->wait_sel, 0x00200020);
549 out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
550
551 return 1;
552
553 }
554
555 static int
556 bmac_init_rx_ring(struct bmac_data *bp)
557 {
558 volatile struct dbdma_regs *rd = bp->rx_dma;
559 int i;
560
561 /* initialize list of sk_buffs for receiving and set up recv dma */
562 if (!bp->rx_allocated) {
563 for (i = 0; i < N_RX_RING; i++) {
564 bp->rx_bufs[i] = dev_alloc_skb(RX_BUFLEN+2);
565 if (bp->rx_bufs[i] == NULL) return 0;
566 skb_reserve(bp->rx_bufs[i], 2);
567 }
568 bp->rx_allocated = 1;
569 }
570
571 memset((char *)bp->rx_cmds, 0, (N_RX_RING+1) * sizeof(struct dbdma_cmd));
572 for (i = 0; i < N_RX_RING; i++)
573 bmac_construct_rxbuff(bp->rx_bufs[i]->data, &bp->rx_cmds[i]);
574
575 bp->rx_empty = 0;
576 bp->rx_fill = i;
577
578 /* Put a branch back to the beginning of the receive command list */
579 dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
580 (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
581
582 /* start rx dma */
583 dbdma_reset(rd);
584 out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
585
586 return 1;
587 }
588
589
590 static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
591 {
592 struct bmac_data *bp = (struct bmac_data *) dev->priv;
593 volatile struct dbdma_regs *td = bp->tx_dma;
594 int i;
595
596 /* see if there's a free slot in the tx ring */
597 /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
598 /* bp->tx_empty, bp->tx_fill)); */
599 i = bp->tx_fill + 1;
600 if (i >= N_TX_RING) i = 0;
601 if (i == bp->tx_empty) {
602 dev->tbusy = 1;
603 bp->tx_fullup = 1;
604 XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
605 return -1; /* can't take it at the moment */
606 }
607
608 dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
609
610 bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
611
612 bp->tx_bufs[bp->tx_fill] = skb;
613 bp->tx_fill = i;
614
615 bp->stats.tx_bytes += skb->len;
616
617 dbdma_continue(td);
618
619 return 0;
620 }
621
622 static int rxintcount = 0;
623
624 static void bmac_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
625 {
626 struct net_device *dev = (struct net_device *) dev_id;
627 struct bmac_data *bp = (struct bmac_data *) dev->priv;
628 volatile struct dbdma_regs *rd = bp->rx_dma;
629 volatile struct dbdma_cmd *cp;
630 int i, nb, stat;
631 struct sk_buff *skb;
632 unsigned int residual;
633 int last;
634 unsigned long flags;
635
636 save_flags(flags); cli();
637
638 if (++rxintcount < 10) {
639 XXDEBUG(("bmac_rxdma_intr\n"));
640 }
641
642 last = -1;
643 i = bp->rx_empty;
644
645 while (1) {
646 cp = &bp->rx_cmds[i];
647 stat = ld_le16(&cp->xfer_status);
648 residual = ld_le16(&cp->res_count);
649 if ((stat & ACTIVE) == 0) break;
650 nb = RX_BUFLEN - residual - 2;
651 if (nb < (ETHERMINPACKET - ETHERCRC)) {
652 skb = NULL;
653 bp->stats.rx_length_errors++;
654 bp->stats.rx_errors++;
655 } else skb = bp->rx_bufs[i];
656 if (skb != NULL) {
657 nb -= ETHERCRC;
658 skb_put(skb, nb);
659 skb->dev = dev;
660 skb->protocol = eth_type_trans(skb, dev);
661 netif_rx(skb);
662 bp->rx_bufs[i] = dev_alloc_skb(RX_BUFLEN+2);
663 skb_reserve(bp->rx_bufs[i], 2);
664 bmac_construct_rxbuff(bp->rx_bufs[i]->data, &bp->rx_cmds[i]);
665 ++bp->stats.rx_packets;
666 bp->stats.rx_bytes += nb;
667 } else {
668 ++bp->stats.rx_dropped;
669 }
670 st_le16(&cp->res_count, 0);
671 st_le16(&cp->xfer_status, 0);
672 last = i;
673 if (++i >= N_RX_RING) i = 0;
674 }
675
676 if (last != -1) {
677 bp->rx_fill = last;
678 bp->rx_empty = i;
679 }
680
681 restore_flags(flags);
682
683 dbdma_continue(rd);
684
685 if (rxintcount < 10) {
686 XXDEBUG(("bmac_rxdma_intr done\n"));
687 }
688 }
689
690 static int txintcount = 0;
691
692 static void bmac_txdma_intr(int irq, void *dev_id, struct pt_regs *regs)
693 {
694 struct net_device *dev = (struct net_device *) dev_id;
695 struct bmac_data *bp = (struct bmac_data *) dev->priv;
696 volatile struct dbdma_cmd *cp;
697 int stat;
698 unsigned long flags;
699
700 save_flags(flags); cli();
701
702 if (txintcount++ < 10) {
703 XXDEBUG(("bmac_txdma_intr\n"));
704 }
705
706 /* del_timer(&bp->tx_timeout); */
707 /* bp->timeout_active = 0; */
708
709 while (1) {
710 cp = &bp->tx_cmds[bp->tx_empty];
711 stat = ld_le16(&cp->xfer_status);
712 if (txintcount < 10) {
713 XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
714 }
715 if (!(stat & ACTIVE)) break;
716
717 if (bp->tx_bufs[bp->tx_empty]) {
718 ++bp->stats.tx_packets;
719 dev_kfree_skb(bp->tx_bufs[bp->tx_empty]);
720 }
721 bp->tx_bufs[bp->tx_empty] = NULL;
722 bp->tx_fullup = 0;
723 dev->tbusy = 0;
724 /* XXDEBUG(("bmac_intr: cleared tbusy, empty=%d fill=%d\n", */
725 /* i, bp->tx_fill)); */
726 mark_bh(NET_BH);
727 if (++bp->tx_empty >= N_TX_RING) bp->tx_empty = 0;
728 if (bp->tx_empty == bp->tx_fill) break;
729 }
730
731 restore_flags(flags);
732
733 if (txintcount < 10) {
734 XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
735 }
736
737 bmac_start(dev);
738 }
739
740 static struct net_device_stats *bmac_stats(struct net_device *dev)
741 {
742 struct bmac_data *p = (struct bmac_data *) dev->priv;
743
744 return &p->stats;
745 }
746
747 #ifndef SUNHME_MULTICAST
748 /* Real fast bit-reversal algorithm, 6-bit values */
749 static int reverse6[64] = {
750 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
751 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
752 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
753 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
754 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
755 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
756 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
757 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
758 };
759
760 static unsigned int
761 crc416(unsigned int curval, unsigned short nxtval)
762 {
763 register unsigned int counter, cur = curval, next = nxtval;
764 register int high_crc_set, low_data_set;
765
766 /* Swap bytes */
767 next = ((next & 0x00FF) << 8) | (next >> 8);
768
769 /* Compute bit-by-bit */
770 for (counter = 0; counter < 16; ++counter) {
771 /* is high CRC bit set? */
772 if ((cur & 0x80000000) == 0) high_crc_set = 0;
773 else high_crc_set = 1;
774
775 cur = cur << 1;
776
777 if ((next & 0x0001) == 0) low_data_set = 0;
778 else low_data_set = 1;
779
780 next = next >> 1;
781
782 /* do the XOR */
783 if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
784 }
785 return cur;
786 }
787
788 static unsigned int
789 bmac_crc(unsigned short *address)
790 {
791 unsigned int newcrc;
792
793 XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
794 newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
795 newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
796 newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
797
798 return(newcrc);
799 }
800
801 /*
802 * Add requested mcast addr to BMac's hash table filter.
803 *
804 */
805
806 static void
807 bmac_addhash(struct bmac_data *bp, unsigned char *addr)
808 {
809 unsigned int crc;
810 unsigned short mask;
811
812 if (!(*addr)) return;
813 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
814 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
815 if (bp->hash_use_count[crc]++) return; /* This bit is already set */
816 mask = crc % 16;
817 mask = (unsigned char)1 << mask;
818 bp->hash_use_count[crc/16] |= mask;
819 }
820
821 static void
822 bmac_removehash(struct bmac_data *bp, unsigned char *addr)
823 {
824 unsigned int crc;
825 unsigned char mask;
826
827 /* Now, delete the address from the filter copy, as indicated */
828 crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
829 crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
830 if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
831 if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
832 mask = crc % 16;
833 mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
834 bp->hash_table_mask[crc/16] &= mask;
835 }
836
837 /*
838 * Sync the adapter with the software copy of the multicast mask
839 * (logical address filter).
840 */
841
842 static void
843 bmac_rx_off(struct net_device *dev)
844 {
845 unsigned short rx_cfg;
846
847 rx_cfg = bmread(dev, RXCFG);
848 rx_cfg &= ~RxMACEnable;
849 bmwrite(dev, RXCFG, rx_cfg);
850 do {
851 rx_cfg = bmread(dev, RXCFG);
852 } while (rx_cfg & RxMACEnable);
853 }
854
855 unsigned short
856 bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
857 {
858 unsigned short rx_cfg;
859
860 rx_cfg = bmread(dev, RXCFG);
861 rx_cfg |= RxMACEnable;
862 if (hash_enable) rx_cfg |= RxHashFilterEnable;
863 else rx_cfg &= ~RxHashFilterEnable;
864 if (promisc_enable) rx_cfg |= RxPromiscEnable;
865 else rx_cfg &= ~RxPromiscEnable;
866 bmwrite(dev, RXRST, RxResetValue);
867 bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
868 bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
869 bmwrite(dev, RXCFG, rx_cfg );
870 return rx_cfg;
871 }
872
873 static void
874 bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
875 {
876 bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
877 bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
878 bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
879 bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
880 }
881
882 #if 0
883 static void
884 bmac_add_multi(struct net_device *dev,
885 struct bmac_data *bp, unsigned char *addr)
886 {
887 /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
888 bmac_addhash(bp, addr);
889 bmac_rx_off(dev);
890 bmac_update_hash_table_mask(dev, bp);
891 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
892 /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
893 }
894
895 static void
896 bmac_remove_multi(struct net_device *dev,
897 struct bmac_data *bp, unsigned char *addr)
898 {
899 bmac_removehash(bp, addr);
900 bmac_rx_off(dev);
901 bmac_update_hash_table_mask(dev, bp);
902 bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
903 }
904 #endif
905
906 /* Set or clear the multicast filter for this adaptor.
907 num_addrs == -1 Promiscuous mode, receive all packets
908 num_addrs == 0 Normal mode, clear multicast list
909 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
910 best-effort filtering.
911 */
912 static void bmac_set_multicast(struct net_device *dev)
913 {
914 struct dev_mc_list *dmi;
915 struct bmac_data *bp = (struct bmac_data *) dev->priv;
916 int num_addrs = dev->mc_count;
917 unsigned short rx_cfg;
918 int i;
919
920 XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
921
922 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
923 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
924 bmac_update_hash_table_mask(dev, bp);
925 rx_cfg = bmac_rx_on(dev, 1, 0);
926 XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
927 } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
928 rx_cfg = bmread(dev, RXCFG);
929 rx_cfg |= RxPromiscEnable;
930 bmwrite(dev, RXCFG, rx_cfg);
931 rx_cfg = bmac_rx_on(dev, 0, 1);
932 XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
933 } else {
934 for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
935 for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
936 if (num_addrs == 0) {
937 rx_cfg = bmac_rx_on(dev, 0, 0);
938 XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
939 } else {
940 for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
941 bmac_addhash(bp, dmi->dmi_addr);
942 bmac_update_hash_table_mask(dev, bp);
943 rx_cfg = bmac_rx_on(dev, 1, 0);
944 XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
945 }
946 }
947 /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
948 }
949 #else /* ifdef SUNHME_MULTICAST */
950
951 /* The version of set_multicast below was lifted from sunhme.c */
952
953 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
954 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
955
956 static void bmac_set_multicast(struct net_device *dev)
957 {
958 struct dev_mc_list *dmi = dev->mc_list;
959 char *addrs;
960 int i, j, bit, byte;
961 unsigned short rx_cfg;
962 u32 crc, poly = CRC_POLYNOMIAL_LE;
963
964 /* Let the transmits drain. */
965 /* while(dev->tbusy) schedule(); */
966
967 /* Lock out others. */
968 /* set_bit(0, (void *) &dev->tbusy); */
969
970 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
971 bmwrite(dev, BHASH0, 0xffff);
972 bmwrite(dev, BHASH1, 0xffff);
973 bmwrite(dev, BHASH2, 0xffff);
974 bmwrite(dev, BHASH3, 0xffff);
975 } else if(dev->flags & IFF_PROMISC) {
976 rx_cfg = bmread(dev, RXCFG);
977 rx_cfg |= RxPromiscEnable;
978 bmwrite(dev, RXCFG, rx_cfg);
979 } else {
980 u16 hash_table[4];
981
982 rx_cfg = bmread(dev, RXCFG);
983 rx_cfg &= ~RxPromiscEnable;
984 bmwrite(dev, RXCFG, rx_cfg);
985
986 for(i = 0; i < 4; i++) hash_table[i] = 0;
987
988 for(i = 0; i < dev->mc_count; i++) {
989 addrs = dmi->dmi_addr;
990 dmi = dmi->next;
991
992 if(!(*addrs & 1))
993 continue;
994
995 crc = 0xffffffffU;
996 for(byte = 0; byte < 6; byte++) {
997 for(bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
998 int test;
999
1000 test = ((bit ^ crc) & 0x01);
1001 crc >>= 1;
1002 if(test)
1003 crc = crc ^ poly;
1004 }
1005 }
1006 crc >>= 26;
1007 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1008 }
1009 bmwrite(dev, BHASH0, hash_table[0]);
1010 bmwrite(dev, BHASH1, hash_table[1]);
1011 bmwrite(dev, BHASH2, hash_table[2]);
1012 bmwrite(dev, BHASH3, hash_table[3]);
1013 }
1014
1015 /* Let us get going again. */
1016 /* dev->tbusy = 0; */
1017 }
1018 #endif /* SUNHME_MULTICAST */
1019
1020 static int miscintcount = 0;
1021
1022 static void bmac_misc_intr(int irq, void *dev_id, struct pt_regs *regs)
1023 {
1024 struct net_device *dev = (struct net_device *) dev_id;
1025 struct bmac_data *bp = (struct bmac_data *)dev->priv;
1026 unsigned int status = bmread(dev, STATUS);
1027 if (miscintcount++ < 10) {
1028 XXDEBUG(("bmac_misc_intr\n"));
1029 }
1030 /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
1031 /* bmac_txdma_intr_inner(irq, dev_id, regs); */
1032 /* if (status & FrameReceived) bp->stats.rx_dropped++; */
1033 if (status & RxErrorMask) bp->stats.rx_errors++;
1034 if (status & RxCRCCntExp) bp->stats.rx_crc_errors++;
1035 if (status & RxLenCntExp) bp->stats.rx_length_errors++;
1036 if (status & RxOverFlow) bp->stats.rx_over_errors++;
1037 if (status & RxAlignCntExp) bp->stats.rx_frame_errors++;
1038
1039 /* if (status & FrameSent) bp->stats.tx_dropped++; */
1040 if (status & TxErrorMask) bp->stats.tx_errors++;
1041 if (status & TxUnderrun) bp->stats.tx_fifo_errors++;
1042 if (status & TxNormalCollExp) bp->stats.collisions++;
1043 }
1044
1045 /*
1046 * Procedure for reading EEPROM
1047 */
1048 #define SROMAddressLength 5
1049 #define DataInOn 0x0008
1050 #define DataInOff 0x0000
1051 #define Clk 0x0002
1052 #define ChipSelect 0x0001
1053 #define SDIShiftCount 3
1054 #define SD0ShiftCount 2
1055 #define DelayValue 1000 /* number of microseconds */
1056 #define SROMStartOffset 10 /* this is in words */
1057 #define SROMReadCount 3 /* number of words to read from SROM */
1058 #define SROMAddressBits 6
1059 #define EnetAddressOffset 20
1060
1061 static unsigned char
1062 bmac_clock_out_bit(struct net_device *dev)
1063 {
1064 unsigned short data;
1065 unsigned short val;
1066
1067 bmwrite(dev, SROMCSR, ChipSelect | Clk);
1068 udelay(DelayValue);
1069
1070 data = bmread(dev, SROMCSR);
1071 udelay(DelayValue);
1072 val = (data >> SD0ShiftCount) & 1;
1073
1074 bmwrite(dev, SROMCSR, ChipSelect);
1075 udelay(DelayValue);
1076
1077 return val;
1078 }
1079
1080 static void
1081 bmac_clock_in_bit(struct net_device *dev, unsigned int val)
1082 {
1083 unsigned short data;
1084
1085 if (val != 0 && val != 1) return;
1086
1087 data = (val << SDIShiftCount);
1088 bmwrite(dev, SROMCSR, data | ChipSelect );
1089 udelay(DelayValue);
1090
1091 bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
1092 udelay(DelayValue);
1093
1094 bmwrite(dev, SROMCSR, data | ChipSelect);
1095 udelay(DelayValue);
1096 }
1097
1098 static void
1099 reset_and_select_srom(struct net_device *dev)
1100 {
1101 /* first reset */
1102 bmwrite(dev, SROMCSR, 0);
1103 udelay(DelayValue);
1104
1105 /* send it the read command (110) */
1106 bmac_clock_in_bit(dev, 1);
1107 bmac_clock_in_bit(dev, 1);
1108 bmac_clock_in_bit(dev, 0);
1109 }
1110
1111 static unsigned short
1112 read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
1113 {
1114 unsigned short data, val;
1115 int i;
1116
1117 /* send out the address we want to read from */
1118 for (i = 0; i < addr_len; i++) {
1119 val = addr >> (addr_len-i-1);
1120 bmac_clock_in_bit(dev, val & 1);
1121 }
1122
1123 /* Now read in the 16-bit data */
1124 data = 0;
1125 for (i = 0; i < 16; i++) {
1126 val = bmac_clock_out_bit(dev);
1127 data <<= 1;
1128 data |= val;
1129 }
1130 bmwrite(dev, SROMCSR, 0);
1131
1132 return data;
1133 }
1134
1135 /*
1136 * It looks like Cogent and SMC use different methods for calculating
1137 * checksums. What a pain..
1138 */
1139
1140 static int
1141 bmac_verify_checksum(struct net_device *dev)
1142 {
1143 unsigned short data, storedCS;
1144
1145 reset_and_select_srom(dev);
1146 data = read_srom(dev, 3, SROMAddressBits);
1147 storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
1148
1149 return 0;
1150 }
1151
1152
1153 static void
1154 bmac_get_station_address(struct net_device *dev, unsigned char *ea)
1155 {
1156 int i;
1157 unsigned short data;
1158
1159 for (i = 0; i < 6; i++)
1160 {
1161 reset_and_select_srom(dev);
1162 data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
1163 ea[2*i] = bitrev(data & 0x0ff);
1164 ea[2*i+1] = bitrev((data >> 8) & 0x0ff);
1165 }
1166 }
1167
1168 static int bmac_reset_and_enable(struct net_device *dev, int enable)
1169 {
1170 struct bmac_data *bp = dev->priv;
1171 unsigned long flags;
1172 struct sk_buff *skb;
1173 unsigned char *data;
1174
1175 save_flags(flags); cli();
1176 bp->reset_and_enabled = 0;
1177 bmac_reset_chip(dev);
1178 if (enable) {
1179 if (!bmac_init_tx_ring(bp) || !bmac_init_rx_ring(bp)) return 0;
1180 if (!bmac_init_chip(dev)) return 0;
1181 bmac_start_chip(dev);
1182 bmwrite(dev, INTDISABLE, EnableNormal);
1183 bp->reset_and_enabled = 1;
1184
1185 /*
1186 * It seems that the bmac can't receive until it's transmitted
1187 * a packet. So we give it a dummy packet to transmit.
1188 */
1189 skb = dev_alloc_skb(ETHERMINPACKET);
1190 data = skb_put(skb, ETHERMINPACKET);
1191 memset(data, 0, ETHERMINPACKET);
1192 memcpy(data, dev->dev_addr, 6);
1193 memcpy(data+6, dev->dev_addr, 6);
1194 bmac_transmit_packet(skb, dev);
1195 }
1196 restore_flags(flags);
1197 return 1;
1198 }
1199
1200 int
1201 bmac_probe(struct net_device *dev)
1202 {
1203 int j, rev;
1204 struct bmac_data *bp;
1205 struct device_node *bmacs;
1206 unsigned char *addr;
1207 static struct device_node *all_bmacs = NULL, *next_bmac;
1208
1209 if (all_bmacs == NULL) {
1210 all_bmacs = find_devices("bmac");
1211 is_bmac_plus = 0;
1212 if (all_bmacs == NULL) {
1213 all_bmacs = find_compatible_devices("network", "bmac+");
1214 if (all_bmacs)
1215 is_bmac_plus = 1;
1216 }
1217 next_bmac = all_bmacs;
1218 }
1219 bmacs = next_bmac;
1220 if (bmacs == NULL) return -ENODEV;
1221 next_bmac = bmacs->next;
1222
1223 bmac_devs = dev; /* KLUDGE!! */
1224
1225 if (bmacs->n_addrs != 3 || bmacs->n_intrs != 3) {
1226 printk(KERN_ERR "can't use BMAC %s: expect 3 addrs and 3 intrs\n",
1227 bmacs->full_name);
1228 return -EINVAL;
1229 }
1230
1231 if (dev == NULL) {
1232 dev = init_etherdev(NULL, PRIV_BYTES);
1233 bmac_devs = dev; /*KLUDGE!!*/
1234 } else {
1235 /* XXX this doesn't look right (but it's never used :-) */
1236 dev->priv = kmalloc(PRIV_BYTES, GFP_KERNEL);
1237 if (dev->priv == 0) return -ENOMEM;
1238 }
1239
1240 #ifdef MODULE
1241 bmac_devs = dev;
1242 #endif
1243
1244 dev->base_addr = (unsigned long)
1245 ioremap(bmacs->addrs[0].address, bmacs->addrs[0].size);
1246 dev->irq = bmacs->intrs[0].line;
1247
1248 bmwrite(dev, INTDISABLE, DisableAll);
1249
1250 addr = get_property(bmacs, "mac-address", NULL);
1251 if (addr == NULL) {
1252 addr = get_property(bmacs, "local-mac-address", NULL);
1253 if (addr == NULL) {
1254 printk(KERN_ERR "Can't get mac-address for BMAC at %lx\n",
1255 dev->base_addr);
1256 return -EAGAIN;
1257 }
1258 }
1259
1260 printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
1261 rev = addr[0] == 0 && addr[1] == 0xA0;
1262 for (j = 0; j < 6; ++j) {
1263 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
1264 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
1265 }
1266 XXDEBUG((", base_addr=%#0lx", dev->base_addr));
1267 printk("\n");
1268
1269 dev->open = bmac_open;
1270 dev->stop = bmac_close;
1271 dev->hard_start_xmit = bmac_output;
1272 dev->get_stats = bmac_stats;
1273 dev->set_multicast_list = bmac_set_multicast;
1274 dev->set_mac_address = bmac_set_address;
1275
1276 bmac_get_station_address(dev, addr);
1277 if (bmac_verify_checksum(dev) != 0) return -EINVAL;
1278
1279 ether_setup(dev);
1280
1281 bp = (struct bmac_data *) dev->priv;
1282 memset(bp, 0, sizeof(struct bmac_data));
1283 bp->tx_dma = (volatile struct dbdma_regs *)
1284 ioremap(bmacs->addrs[1].address, bmacs->addrs[1].size);
1285 bp->tx_dma_intr = bmacs->intrs[1].line;
1286 bp->rx_dma = (volatile struct dbdma_regs *)
1287 ioremap(bmacs->addrs[2].address, bmacs->addrs[2].size);
1288 bp->rx_dma_intr = bmacs->intrs[2].line;
1289
1290 bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
1291 bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
1292
1293 bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
1294 skb_queue_head_init(bp->queue);
1295
1296 bp->node = bmacs;
1297 memset(&bp->stats, 0, sizeof(bp->stats));
1298 memset((char *) bp->tx_cmds, 0,
1299 (N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
1300 /* init_timer(&bp->tx_timeout); */
1301 /* bp->timeout_active = 0; */
1302
1303 if (request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev)) {
1304 printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
1305 return -EAGAIN;
1306 }
1307 if (request_irq(bmacs->intrs[1].line, bmac_txdma_intr, 0, "BMAC-txdma",
1308 dev)) {
1309 printk(KERN_ERR "BMAC: can't get irq %d\n", bmacs->intrs[1].line);
1310 return -EAGAIN;
1311 }
1312 if (request_irq(bmacs->intrs[2].line, bmac_rxdma_intr, 0, "BMAC-rxdma",
1313 dev)) {
1314 printk(KERN_ERR "BMAC: can't get irq %d\n", bmacs->intrs[2].line);
1315 return -EAGAIN;
1316 }
1317
1318 if (!bmac_reset_and_enable(dev, 0)) return -ENOMEM;
1319
1320 #ifdef CONFIG_PROC_FS
1321 proc_net_register(&(struct proc_dir_entry) {
1322 PROC_NET_BMAC, 4, "bmac",
1323 S_IFREG | S_IRUGO, 1, 0, 0,
1324 0, &proc_net_inode_operations,
1325 bmac_proc_info
1326 });
1327 #endif
1328
1329 return 0;
1330 }
1331
1332 static int bmac_open(struct net_device *dev)
1333 {
1334 /* XXDEBUG(("bmac: enter open\n")); */
1335 /* reset the chip */
1336 bmac_reset_and_enable(dev, 1);
1337
1338 dev->flags |= IFF_UP | IFF_RUNNING;
1339
1340 MOD_INC_USE_COUNT;
1341 return 0;
1342 }
1343
1344 static int bmac_close(struct net_device *dev)
1345 {
1346 struct bmac_data *bp = (struct bmac_data *) dev->priv;
1347 volatile struct dbdma_regs *rd = bp->rx_dma;
1348 volatile struct dbdma_regs *td = bp->tx_dma;
1349 unsigned short config;
1350 int i;
1351
1352 dev->flags &= ~(IFF_UP | IFF_RUNNING);
1353
1354 /* disable rx and tx */
1355 config = bmread(dev, RXCFG);
1356 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1357
1358 config = bmread(dev, TXCFG);
1359 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1360
1361 bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
1362
1363 /* disable rx and tx dma */
1364 st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1365 st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
1366
1367 /* free some skb's */
1368 XXDEBUG(("bmac: free rx bufs\n"));
1369 for (i=0; i<N_RX_RING; i++) {
1370 if (bp->rx_bufs[i] != NULL) {
1371 dev_kfree_skb(bp->rx_bufs[i]);
1372 bp->rx_bufs[i] = NULL;
1373 }
1374 }
1375 bp->rx_allocated = 0;
1376 XXDEBUG(("bmac: free tx bufs\n"));
1377 for (i = 0; i<N_TX_RING; i++) {
1378 if (bp->tx_bufs[i] != NULL) {
1379 dev_kfree_skb(bp->tx_bufs[i]);
1380 bp->tx_bufs[i] = NULL;
1381 }
1382 }
1383 bp->reset_and_enabled = 0;
1384 XXDEBUG(("bmac: all bufs freed\n"));
1385
1386 MOD_DEC_USE_COUNT;
1387
1388 return 0;
1389 }
1390
1391 static void
1392 bmac_start(struct net_device *dev)
1393 {
1394 struct bmac_data *bp = dev->priv;
1395 int i;
1396 struct sk_buff *skb;
1397 unsigned long flags;
1398
1399 save_flags(flags); cli();
1400 while (1) {
1401 i = bp->tx_fill + 1;
1402 if (i >= N_TX_RING) i = 0;
1403 if (i == bp->tx_empty) break;
1404 skb = skb_dequeue(bp->queue);
1405 if (skb == NULL) break;
1406 bmac_transmit_packet(skb, dev);
1407 }
1408 restore_flags(flags);
1409 }
1410
1411 static int
1412 bmac_output(struct sk_buff *skb, struct net_device *dev)
1413 {
1414 struct bmac_data *bp = dev->priv;
1415 skb_queue_tail(bp->queue, skb);
1416 bmac_start(dev);
1417 return 0;
1418 }
1419
1420 static void bmac_tx_timeout(unsigned long data)
1421 {
1422 struct net_device *dev = (struct net_device *) data;
1423 struct bmac_data *bp = (struct bmac_data *) dev->priv;
1424 volatile struct dbdma_regs *td = bp->tx_dma;
1425 volatile struct dbdma_regs *rd = bp->rx_dma;
1426 volatile struct dbdma_cmd *cp;
1427 unsigned long flags;
1428 unsigned short config, oldConfig;
1429 int i;
1430
1431 XXDEBUG(("bmac: tx_timeout called\n"));
1432 save_flags(flags); cli();
1433 bp->timeout_active = 0;
1434
1435 /* update various counters */
1436 /* bmac_handle_misc_intrs(bp, 0); */
1437
1438 cp = &bp->tx_cmds[bp->tx_empty];
1439 /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
1440 /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
1441 /* mb->pr, mb->xmtfs, mb->fifofc)); */
1442
1443 /* turn off both tx and rx and reset the chip */
1444 config = bmread(dev, RXCFG);
1445 bmwrite(dev, RXCFG, (config & ~RxMACEnable));
1446 config = bmread(dev, TXCFG);
1447 bmwrite(dev, TXCFG, (config & ~TxMACEnable));
1448 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1449 printk(KERN_ERR "bmac: transmit timeout - resetting\n");
1450 bmac_reset_chip(dev);
1451
1452 /* restart rx dma */
1453 cp = bus_to_virt(ld_le32(&rd->cmdptr));
1454 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
1455 out_le16(&cp->xfer_status, 0);
1456 out_le32(&rd->cmdptr, virt_to_bus(cp));
1457 out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
1458
1459 /* fix up the transmit side */
1460 XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
1461 bp->tx_empty, bp->tx_fill, bp->tx_fullup));
1462 i = bp->tx_empty;
1463 ++bp->stats.tx_errors;
1464 if (i != bp->tx_fill) {
1465 dev_kfree_skb(bp->tx_bufs[i]);
1466 bp->tx_bufs[i] = NULL;
1467 if (++i >= N_TX_RING) i = 0;
1468 bp->tx_empty = i;
1469 }
1470 bp->tx_fullup = 0;
1471 dev->tbusy = 0;
1472 mark_bh(NET_BH);
1473 XXDEBUG((KERN_DEBUG "bmac: clearing tbusy\n"));
1474 if (i != bp->tx_fill) {
1475 cp = &bp->tx_cmds[i];
1476 out_le16(&cp->xfer_status, 0);
1477 out_le16(&cp->command, OUTPUT_LAST);
1478 out_le32(&td->cmdptr, virt_to_bus(cp));
1479 out_le32(&td->control, DBDMA_SET(RUN));
1480 /* bmac_set_timeout(dev); */
1481 XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
1482 }
1483
1484 /* turn it back on */
1485 oldConfig = bmread(dev, RXCFG);
1486 bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
1487 oldConfig = bmread(dev, TXCFG);
1488 bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
1489
1490 restore_flags(flags);
1491 }
1492
1493 #if 0
1494 static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
1495 {
1496 int i,*ip;
1497
1498 for (i=0;i< count;i++) {
1499 ip = (int*)(cp+i);
1500
1501 printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
1502 ld_le32(ip+0),
1503 ld_le32(ip+1),
1504 ld_le32(ip+2),
1505 ld_le32(ip+3));
1506 }
1507
1508 }
1509 #endif
1510
1511 static int
1512 bmac_proc_info(char *buffer, char **start, off_t offset, int length, int dummy)
1513 {
1514 int len = 0;
1515 off_t pos = 0;
1516 off_t begin = 0;
1517 int i;
1518
1519 if (bmac_devs == NULL) return (-ENOSYS);
1520
1521 len += sprintf(buffer, "BMAC counters & registers\n");
1522
1523 for (i = 0; i<N_REG_ENTRIES; i++) {
1524 len += sprintf(buffer + len, "%s: %#08x\n",
1525 reg_entries[i].name,
1526 bmread(bmac_devs, reg_entries[i].reg_offset));
1527 pos = begin + len;
1528
1529 if (pos < offset) {
1530 len = 0;
1531 begin = pos;
1532 }
1533
1534 if (pos > offset+length) break;
1535 }
1536
1537 *start = buffer + (offset - begin);
1538 len -= (offset - begin);
1539
1540 if (len > length) len = length;
1541
1542 return len;
1543 }
1544
1545 #ifdef MODULE
1546
1547 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
1548 MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
1549
1550 int init_module(void)
1551 {
1552 int res;
1553
1554 if(bmac_devs != NULL)
1555 return -EBUSY;
1556 res = bmac_probe(NULL);
1557 return res;
1558 }
1559 void cleanup_module(void)
1560 {
1561 struct bmac_data *bp = (struct bmac_data *) bmac_devs->priv;
1562 unregister_netdev(bmac_devs);
1563
1564 free_irq(bmac_devs->irq, bmac_misc_intr);
1565 free_irq(bp->tx_dma_intr, bmac_txdma_intr);
1566 free_irq(bp->rx_dma_intr, bmac_rxdma_intr);
1567
1568 kfree(bmac_devs);
1569 bmac_devs = NULL;
1570 }
1571
1572 #endif
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux