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Import 2.3.18pre1
[davej-history.git] / drivers / net / bagetlance.c
blobeeb6b77c519cd85fba5f28a2fff3b9999d8b01b5
1 /* $Id$
2 * vmelance.c: Ethernet driver for VME Lance cards on Baget/MIPS
3 * This code stealed and adopted from linux/drivers/net/atarilance.c
4 * See that for author info
5 *
6 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
7 */
8
9 /*
10 * Driver code for Baget/Lance taken from atarilance.c, which also
11 * works well in case of Besta. Most significant changes made here
12 * related with 16BIT-only access to A24 space.
13 */
14
15 static char *version = "bagetlance.c: v1.1 11/10/98\n";
16
17 #include <linux/module.h>
18
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/errno.h>
25 #include <linux/malloc.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28
29 #include <asm/irq.h>
30 #include <asm/bitops.h>
31 #include <asm/io.h>
32
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36
37 #include <asm/baget/baget.h>
38
39 #define BAGET_LANCE_IRQ BAGET_IRQ_MASK(0xdf)
40
41 /*
42 * Define following if you don't need 16BIT-only access to Lance memory
43 * (Normally BAGET needs it)
44 */
45 #undef NORMAL_MEM_ACCESS
46
47 /* Debug level:
48 * 0 = silent, print only serious errors
49 * 1 = normal, print error messages
50 * 2 = debug, print debug infos
51 * 3 = debug, print even more debug infos (packet data)
52 */
53
54 #define LANCE_DEBUG 1
55
56 #ifdef LANCE_DEBUG
57 static int lance_debug = LANCE_DEBUG;
58 #else
59 static int lance_debug = 1;
60 #endif
61 MODULE_PARM(lance_debug, "i");
62
63 /* Print debug messages on probing? */
64 #undef LANCE_DEBUG_PROBE
65
66 #define DPRINTK(n,a) \
67 do { \
68 if (lance_debug >= n) \
69 printk a; \
70 } while( 0 )
71
72 #ifdef LANCE_DEBUG_PROBE
73 # define PROBE_PRINT(a) printk a
74 #else
75 # define PROBE_PRINT(a)
76 #endif
77
78 /* These define the number of Rx and Tx buffers as log2. (Only powers
79 * of two are valid)
80 * Much more rx buffers (32) are reserved than tx buffers (8), since receiving
81 * is more time critical then sending and packets may have to remain in the
82 * board's memory when main memory is low.
83 */
84
85 /* Baget Lance has 64K on-board memory, so it looks we can't increase
86 buffer quantity (40*1.5K is about 64K) */
87
88 #define TX_LOG_RING_SIZE 3
89 #define RX_LOG_RING_SIZE 5
90
91 /* These are the derived values */
92
93 #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
94 #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
95 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
96
97 #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
98 #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
99 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
100
101 /* The LANCE Rx and Tx ring descriptors. */
102 struct lance_rx_head {
103 volatile unsigned short base; /* Low word of base addr */
104 #ifdef NORMAL_MEM_ACCESS
105 /* Following two fields are joined into one short to guarantee
106 16BIT access to Baget lance registers */
107 volatile unsigned char flag;
108 unsigned char base_hi; /* High word of base addr (unused) */
109 #else
110 /* Following macros are used as replecements to 8BIT fields */
111 #define GET_FLAG(h) (((h)->flag_base_hi >> 8) & 0xff)
112 #define SET_FLAG(h,f) (h)->flag_base_hi = ((h)->flag_base_hi & 0xff) | \
113 (((unsigned)(f)) << 8)
114 volatile unsigned short flag_base_hi;
115 #endif
116 volatile short buf_length; /* This length is 2s complement! */
117 volatile short msg_length; /* This length is "normal". */
118 };
119
120
121 struct lance_tx_head {
122 volatile unsigned short base; /* Low word of base addr */
123 #ifdef NORMAL_MEM_ACCESS
124 /* See comments above about 8BIT-access Baget A24-space problems */
125 volatile unsigned char flag;
126 unsigned char base_hi; /* High word of base addr (unused) */
127 #else
128 volatile unsigned short flag_base_hi;
129 #endif
130 volatile short length; /* Length is 2s complement! */
131 volatile short misc;
132 };
133
134 struct ringdesc {
135 volatile unsigned short adr_lo; /* Low 16 bits of address */
136 #ifdef NORMAL_MEM_ACCESS
137 /* See comments above about 8BIT-access Bage A24-space problems */
138 unsigned char len; /* Length bits */
139 unsigned char adr_hi; /* High 8 bits of address (unused) */
140 #else
141 volatile unsigned short len_adr_hi;
142 #endif
143 };
144
145 /* The LANCE initialization block, described in databook. */
146 struct lance_init_block {
147 unsigned short mode; /* Pre-set mode */
148 unsigned char hwaddr[6]; /* Physical ethernet address */
149 unsigned filter[2]; /* Multicast filter (unused). */
150 /* Receive and transmit ring base, along with length bits. */
151 struct ringdesc rx_ring;
152 struct ringdesc tx_ring;
153 };
154
155 /* The whole layout of the Lance shared memory */
156 struct lance_memory {
157 struct lance_init_block init;
158 struct lance_tx_head tx_head[TX_RING_SIZE];
159 struct lance_rx_head rx_head[RX_RING_SIZE];
160 char packet_area[0]; /* packet data follow after the
161 * init block and the ring
162 * descriptors and are located
163 * at runtime */
164 };
165
166 /* RieblCard specifics:
167 * The original TOS driver for these cards reserves the area from offset
168 * 0xee70 to 0xeebb for storing configuration data. Of interest to us is the
169 * Ethernet address there, and the magic for verifying the data's validity.
170 * The reserved area isn't touch by packet buffers. Furthermore, offset 0xfffe
171 * is reserved for the interrupt vector number.
172 */
173 #define RIEBL_RSVD_START 0xee70
174 #define RIEBL_RSVD_END 0xeec0
175 #define RIEBL_MAGIC 0x09051990
176 #define RIEBL_MAGIC_ADDR ((unsigned long *)(((char *)MEM) + 0xee8a))
177 #define RIEBL_HWADDR_ADDR ((unsigned char *)(((char *)MEM) + 0xee8e))
178 #define RIEBL_IVEC_ADDR ((unsigned short *)(((char *)MEM) + 0xfffe))
179
180 /* This is a default address for the old RieblCards without a battery
181 * that have no ethernet address at boot time. 00:00:36:04 is the
182 * prefix for Riebl cards, the 00:00 at the end is arbitrary.
183 */
184
185 static unsigned char OldRieblDefHwaddr[6] = {
186 0x00, 0x00, 0x36, 0x04, 0x00, 0x00
187 };
188
189 /* I/O registers of the Lance chip */
190
191 struct lance_ioreg {
192 /* base+0x0 */ volatile unsigned short data;
193 /* base+0x2 */ volatile unsigned short addr;
194 unsigned char _dummy1[3];
195 /* base+0x7 */ volatile unsigned char ivec;
196 unsigned char _dummy2[5];
197 /* base+0xd */ volatile unsigned char eeprom;
198 unsigned char _dummy3;
199 /* base+0xf */ volatile unsigned char mem;
200 };
201
202 /* Types of boards this driver supports */
203
204 enum lance_type {
205 OLD_RIEBL, /* old Riebl card without battery */
206 NEW_RIEBL, /* new Riebl card with battery */
207 PAM_CARD /* PAM card with EEPROM */
208 };
209
210 static char *lance_names[] = {
211 "Riebl-Card (without battery)",
212 "Riebl-Card (with battery)",
213 "PAM intern card"
214 };
215
216 /* The driver's private device structure */
217
218 struct lance_private {
219 enum lance_type cardtype;
220 struct lance_ioreg *iobase;
221 struct lance_memory *mem;
222 int cur_rx, cur_tx; /* The next free ring entry */
223 int dirty_tx; /* Ring entries to be freed. */
224 /* copy function */
225 void *(*memcpy_f)( void *, const void *, size_t );
226 struct net_device_stats stats;
227 /* These two must be ints for set_bit() */
228 int tx_full;
229 int lock;
230 };
231
232 /* I/O register access macros */
233
234 #define MEM lp->mem
235 #define DREG IO->data
236 #define AREG IO->addr
237 #define REGA(a) ( AREG = (a), DREG )
238
239 /* Definitions for packet buffer access: */
240 #define PKT_BUF_SZ 1544
241 /* Get the address of a packet buffer corresponding to a given buffer head */
242 #define PKTBUF_ADDR(head) (((unsigned char *)(MEM)) + (head)->base)
243
244 /* Possible memory/IO addresses for probing */
245
246 struct lance_addr {
247 unsigned long memaddr;
248 unsigned long ioaddr;
249 int slow_flag;
250 } lance_addr_list[] = {
251 { BAGET_LANCE_MEM_BASE, BAGET_LANCE_IO_BASE, 1 } /* Baget Lance */
252 };
253
254 #define N_LANCE_ADDR (sizeof(lance_addr_list)/sizeof(*lance_addr_list))
255
256
257 #define LANCE_HI_BASE (0xff & (BAGET_LANCE_MEM_BASE >> 16))
258
259 /* Definitions for the Lance */
260
261 /* tx_head flags */
262 #define TMD1_ENP 0x01 /* end of packet */
263 #define TMD1_STP 0x02 /* start of packet */
264 #define TMD1_DEF 0x04 /* deferred */
265 #define TMD1_ONE 0x08 /* one retry needed */
266 #define TMD1_MORE 0x10 /* more than one retry needed */
267 #define TMD1_ERR 0x40 /* error summary */
268 #define TMD1_OWN 0x80 /* ownership (set: chip owns) */
269
270 #define TMD1_OWN_CHIP TMD1_OWN
271 #define TMD1_OWN_HOST 0
272
273 /* tx_head misc field */
274 #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
275 #define TMD3_RTRY 0x0400 /* failed after 16 retries */
276 #define TMD3_LCAR 0x0800 /* carrier lost */
277 #define TMD3_LCOL 0x1000 /* late collision */
278 #define TMD3_UFLO 0x4000 /* underflow (late memory) */
279 #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
280
281 /* rx_head flags */
282 #define RMD1_ENP 0x01 /* end of packet */
283 #define RMD1_STP 0x02 /* start of packet */
284 #define RMD1_BUFF 0x04 /* buffer error */
285 #define RMD1_CRC 0x08 /* CRC error */
286 #define RMD1_OFLO 0x10 /* overflow */
287 #define RMD1_FRAM 0x20 /* framing error */
288 #define RMD1_ERR 0x40 /* error summary */
289 #define RMD1_OWN 0x80 /* ownership (set: ship owns) */
290
291 #define RMD1_OWN_CHIP RMD1_OWN
292 #define RMD1_OWN_HOST 0
293
294 /* register names */
295 #define CSR0 0 /* mode/status */
296 #define CSR1 1 /* init block addr (low) */
297 #define CSR2 2 /* init block addr (high) */
298 #define CSR3 3 /* misc */
299 #define CSR8 8 /* address filter */
300 #define CSR15 15 /* promiscuous mode */
301
302 /* CSR0 */
303 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
304 #define CSR0_INIT 0x0001 /* initialize (RS) */
305 #define CSR0_STRT 0x0002 /* start (RS) */
306 #define CSR0_STOP 0x0004 /* stop (RS) */
307 #define CSR0_TDMD 0x0008 /* transmit demand (RS) */
308 #define CSR0_TXON 0x0010 /* transmitter on (R) */
309 #define CSR0_RXON 0x0020 /* receiver on (R) */
310 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */
311 #define CSR0_INTR 0x0080 /* interrupt active (R) */
312 #define CSR0_IDON 0x0100 /* initialization done (RC) */
313 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
314 #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
315 #define CSR0_MERR 0x0800 /* memory error (RC) */
316 #define CSR0_MISS 0x1000 /* missed frame (RC) */
317 #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
318 #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
319 #define CSR0_ERR 0x8000 /* error (RC) */
320
321 /* CSR3 */
322 #define CSR3_BCON 0x0001 /* byte control */
323 #define CSR3_ACON 0 // fixme: 0x0002 /* ALE control */
324 #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
325
326
327
328 /***************************** Prototypes *****************************/
329
330 static int addr_accessible( volatile void *regp, int wordflag, int
331 writeflag );
332 static unsigned long lance_probe1( struct net_device *dev, struct lance_addr
333 *init_rec );
334 static int lance_open( struct net_device *dev );
335 static void lance_init_ring( struct net_device *dev );
336 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
337 static void lance_interrupt( int irq, void *dev_id, struct pt_regs *fp );
338 static int lance_rx( struct net_device *dev );
339 static int lance_close( struct net_device *dev );
340 static struct net_device_stats *lance_get_stats( struct net_device *dev );
341 static void set_multicast_list( struct net_device *dev );
342 static int lance_set_mac_address( struct net_device *dev, void *addr );
343
344 /************************* End of Prototypes **************************/
345
346 /* Network traffic statistic (bytes) */
347
348 int lance_stat = 0;
349
350 static void update_lance_stat (int len) {
351 lance_stat += len;
352 }
353
354 /*
355 This function is used to access Baget/Lance memory to avoid
356 8/32BIT access to VAC A24 space
357 ALL memcpy calls was chenged to this function to avoid dbe problems
358 Don't confuse with function name -- it stays from original code
359 */
360
361 void *slow_memcpy( void *dst, const void *src, size_t len )
362
363 {
364 unsigned long to = (unsigned long)dst;
365 unsigned long from = (unsigned long)src;
366 unsigned long to_end = to +len;
367
368 /* Unaligned flags */
369
370 int odd_from = from & 1;
371 int odd_to = to & 1;
372 int odd_to_end = to_end & 1;
373
374 /* Align for 16BIT-access first */
375
376 register unsigned short *from_a = (unsigned short*) (from & ~1);
377 register unsigned short *to_a = (unsigned short*) (to & ~1);
378 register unsigned short *to_end_a = (unsigned short*) (to_end & ~1);
379
380 /* Caching values -- not in loop invariant */
381
382 register unsigned short from_v;
383 register unsigned short to_v;
384
385 /* Invariant is: from_a and to_a are pointers before or exactly to
386 currently copying byte */
387
388 if (odd_to) {
389 /* First byte unaligned case */
390 from_v = *from_a;
391 to_v = *to_a;
392
393 to_v &= ~0xff;
394 to_v |= 0xff & (from_v >> (odd_from ? 0 : 8));
395 *to_a++ = to_v;
396
397 if (odd_from) from_a++;
398 }
399 if (odd_from == odd_to) {
400 /* Same parity */
401 while (to_a + 7 < to_end_a) {
402 unsigned long dummy1, dummy2;
403 unsigned long reg1, reg2, reg3, reg4;
404
405 __asm__ __volatile__(
406 ".set\tnoreorder\n\t"
407 ".set\tnoat\n\t"
408 "lh\t%2,0(%1)\n\t"
409 "nop\n\t"
410 "lh\t%3,2(%1)\n\t"
411 "sh\t%2,0(%0)\n\t"
412 "lh\t%4,4(%1)\n\t"
413 "sh\t%3,2(%0)\n\t"
414 "lh\t%5,6(%1)\n\t"
415 "sh\t%4,4(%0)\n\t"
416 "lh\t%2,8(%1)\n\t"
417 "sh\t%5,6(%0)\n\t"
418 "lh\t%3,10(%1)\n\t"
419 "sh\t%2,8(%0)\n\t"
420 "lh\t%4,12(%1)\n\t"
421 "sh\t%3,10(%0)\n\t"
422 "lh\t%5,14(%1)\n\t"
423 "sh\t%4,12(%0)\n\t"
424 "nop\n\t"
425 "sh\t%5,14(%0)\n\t"
426 ".set\tat\n\t"
427 ".set\treorder"
428 :"=r" (dummy1), "=r" (dummy2),
429 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
430 :"0" (to_a), "1" (from_a)
431 :"memory");
432
433 to_a += 8;
434 from_a += 8;
435
436 }
437 while (to_a < to_end_a) {
438 *to_a++ = *from_a++;
439 }
440 } else {
441 /* Different parity */
442 from_v = *from_a;
443 while (to_a < to_end_a) {
444 unsigned short from_v_next;
445 from_v_next = *++from_a;
446 *to_a++ = ((from_v & 0xff)<<8) | ((from_v_next>>8) & 0xff);
447 from_v = from_v_next;
448 }
449
450 }
451 if (odd_to_end) {
452 /* Last byte unaligned case */
453 to_v = *to_a;
454 from_v = *from_a;
455
456 to_v &= ~0xff00;
457 if (odd_from == odd_to) {
458 to_v |= from_v & 0xff00;
459 } else {
460 to_v |= (from_v<<8) & 0xff00;
461 }
462
463 *to_a = to_v;
464 }
465
466 update_lance_stat( len );
467
468 return( dst );
469 }
470
471
472 int __init bagetlance_probe( struct net_device *dev )
473
474 { int i;
475 static int found = 0;
476
477 if (found)
478 /* Assume there's only one board possible... That seems true, since
479 * the Riebl/PAM board's address cannot be changed. */
480 return( ENODEV );
481
482 for( i = 0; i < N_LANCE_ADDR; ++i ) {
483 if (lance_probe1( dev, &lance_addr_list[i] )) {
484 found = 1;
485 return( 0 );
486 }
487 }
488
489 return( ENODEV );
490 }
491
492
493
494 /* Derived from hwreg_present() in vme/config.c: */
495
496 static int __init addr_accessible( volatile void *regp,
497 int wordflag,
498 int writeflag )
499 {
500 /* We have a fine function to do it */
501 extern int try_read(unsigned long, int);
502 return try_read((unsigned long)regp, sizeof(short)) != -1;
503 }
504
505
506
507 /* Original atari driver uses it */
508 #define IRQ_TYPE_PRIO SA_INTERRUPT
509 #define IRQ_SOURCE_TO_VECTOR(x) (x)
510
511 static unsigned long __init lance_probe1( struct net_device *dev,
512 struct lance_addr *init_rec )
513
514 { volatile unsigned short *memaddr =
515 (volatile unsigned short *)init_rec->memaddr;
516 volatile unsigned short *ioaddr =
517 (volatile unsigned short *)init_rec->ioaddr;
518 struct lance_private *lp;
519 struct lance_ioreg *IO;
520 int i;
521 static int did_version = 0;
522 unsigned short save1, save2;
523
524 PROBE_PRINT(( "Probing for Lance card at mem %#lx io %#lx\n",
525 (long)memaddr, (long)ioaddr ));
526
527 /* Test whether memory readable and writable */
528 PROBE_PRINT(( "lance_probe1: testing memory to be accessible\n" ));
529 if (!addr_accessible( memaddr, 1, 1 )) goto probe_fail;
530
531 if ((unsigned long)memaddr >= KSEG2) {
532 extern int kseg2_alloc_io (unsigned long addr, unsigned long size);
533 if (kseg2_alloc_io((unsigned long)memaddr, BAGET_LANCE_MEM_SIZE)) {
534 printk("bagetlance: unable map lance memory\n");
535 goto probe_fail;
536 }
537 }
538
539 /* Written values should come back... */
540 PROBE_PRINT(( "lance_probe1: testing memory to be writable (1)\n" ));
541 save1 = *memaddr;
542 *memaddr = 0x0001;
543 if (*memaddr != 0x0001) goto probe_fail;
544 PROBE_PRINT(( "lance_probe1: testing memory to be writable (2)\n" ));
545 *memaddr = 0x0000;
546 if (*memaddr != 0x0000) goto probe_fail;
547 *memaddr = save1;
548
549 /* First port should be readable and writable */
550 PROBE_PRINT(( "lance_probe1: testing ioport to be accessible\n" ));
551 if (!addr_accessible( ioaddr, 1, 1 )) goto probe_fail;
552
553 /* and written values should be readable */
554 PROBE_PRINT(( "lance_probe1: testing ioport to be writeable\n" ));
555 save2 = ioaddr[1];
556 ioaddr[1] = 0x0001;
557 if (ioaddr[1] != 0x0001) goto probe_fail;
558
559 /* The CSR0_INIT bit should not be readable */
560 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" ));
561 save1 = ioaddr[0];
562 ioaddr[1] = CSR0;
563 ioaddr[0] = CSR0_INIT | CSR0_STOP;
564 if (ioaddr[0] != CSR0_STOP) {
565 ioaddr[0] = save1;
566 ioaddr[1] = save2;
567 goto probe_fail;
568 }
569 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" ));
570 ioaddr[0] = CSR0_STOP;
571 if (ioaddr[0] != CSR0_STOP) {
572 ioaddr[0] = save1;
573 ioaddr[1] = save2;
574 goto probe_fail;
575 }
576
577 /* Now ok... */
578 PROBE_PRINT(( "lance_probe1: Lance card detected\n" ));
579 goto probe_ok;
580
581 probe_fail:
582 return( 0 );
583
584 probe_ok:
585 init_etherdev( dev, sizeof(struct lance_private) );
586 if (!dev->priv)
587 dev->priv = kmalloc( sizeof(struct lance_private), GFP_KERNEL );
588 lp = (struct lance_private *)dev->priv;
589 MEM = (struct lance_memory *)memaddr;
590 IO = lp->iobase = (struct lance_ioreg *)ioaddr;
591 dev->base_addr = (unsigned long)ioaddr; /* informational only */
592 lp->memcpy_f = init_rec->slow_flag ? slow_memcpy : memcpy;
593
594 REGA( CSR0 ) = CSR0_STOP;
595
596 /* Now test for type: If the eeprom I/O port is readable, it is a
597 * PAM card */
598 if (addr_accessible( &(IO->eeprom), 0, 0 )) {
599 /* Switch back to Ram */
600 i = IO->mem;
601 lp->cardtype = PAM_CARD;
602 }
603 #ifdef NORMAL_MEM_ACCESS
604 else if (*RIEBL_MAGIC_ADDR == RIEBL_MAGIC) {
605 #else
606 else if (({
607 unsigned short *a = (unsigned short*)RIEBL_MAGIC_ADDR;
608 (((int)a[0]) << 16) + ((int)a[1]) == RIEBL_MAGIC;
609 })) {
610 #endif
611 lp->cardtype = NEW_RIEBL;
612 }
613 else
614 lp->cardtype = OLD_RIEBL;
615
616 if (lp->cardtype == PAM_CARD ||
617 memaddr == (unsigned short *)0xffe00000) {
618 /* PAMs card and Riebl on ST use level 5 autovector */
619 request_irq(BAGET_LANCE_IRQ, lance_interrupt, IRQ_TYPE_PRIO,
620 "PAM/Riebl-ST Ethernet", dev);
621 dev->irq = (unsigned short)BAGET_LANCE_IRQ;
622 }
623 else {
624 /* For VME-RieblCards, request a free VME int;
625 * (This must be unsigned long, since dev->irq is short and the
626 * IRQ_MACHSPEC bit would be cut off...)
627 */
628 unsigned long irq = BAGET_LANCE_IRQ;
629 if (!irq) {
630 printk( "Lance: request for VME interrupt failed\n" );
631 return( 0 );
632 }
633 request_irq(irq, lance_interrupt, IRQ_TYPE_PRIO,
634 "Riebl-VME Ethernet", dev);
635 dev->irq = irq;
636 }
637
638 printk("%s: %s at io %#lx, mem %#lx, irq %d%s, hwaddr ",
639 dev->name, lance_names[lp->cardtype],
640 (unsigned long)ioaddr,
641 (unsigned long)memaddr,
642 dev->irq,
643 init_rec->slow_flag ? " (slow memcpy)" : "" );
644
645 /* Get the ethernet address */
646 switch( lp->cardtype ) {
647 case OLD_RIEBL:
648 /* No ethernet address! (Set some default address) */
649 slow_memcpy( dev->dev_addr, OldRieblDefHwaddr, 6 );
650 break;
651 case NEW_RIEBL:
652 lp->memcpy_f( dev->dev_addr, RIEBL_HWADDR_ADDR, 6 );
653 break;
654 case PAM_CARD:
655 i = IO->eeprom;
656 for( i = 0; i < 6; ++i )
657 dev->dev_addr[i] =
658 ((((unsigned short *)MEM)[i*2] & 0x0f) << 4) |
659 ((((unsigned short *)MEM)[i*2+1] & 0x0f));
660 i = IO->mem;
661 break;
662 }
663 for( i = 0; i < 6; ++i )
664 printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" );
665 if (lp->cardtype == OLD_RIEBL) {
666 printk( "%s: Warning: This is a default ethernet address!\n",
667 dev->name );
668 printk( " Use \"ifconfig hw ether ...\" to set the address.\n" );
669 }
670
671 MEM->init.mode = 0x0000; /* Disable Rx and Tx. */
672
673 {
674 unsigned char hwaddr[6];
675 for( i = 0; i < 6; i++ )
676 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
677 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
678 }
679
680 MEM->init.filter[0] = 0x00000000;
681 MEM->init.filter[1] = 0x00000000;
682 MEM->init.rx_ring.adr_lo = offsetof( struct lance_memory, rx_head );
683
684 #ifdef NORMAL_MEM_ACCESS
685 MEM->init.rx_ring.adr_hi = LANCE_HI_BASE;
686 MEM->init.rx_ring.len = RX_RING_LEN_BITS;
687 #else
688 MEM->init.rx_ring.len_adr_hi =
689 ((unsigned)RX_RING_LEN_BITS << 8) | LANCE_HI_BASE;
690 #endif
691
692
693 MEM->init.tx_ring.adr_lo = offsetof( struct lance_memory, tx_head );
694
695 #ifdef NORMAL_MEM_ACCESS
696 MEM->init.tx_ring.adr_hi = LANCE_HI_BASE;
697 MEM->init.tx_ring.len = TX_RING_LEN_BITS;
698 #else
699 MEM->init.tx_ring.len_adr_hi =
700 ((unsigned)TX_RING_LEN_BITS<<8) | LANCE_HI_BASE;
701 #endif
702
703 if (lp->cardtype == PAM_CARD)
704 IO->ivec = IRQ_SOURCE_TO_VECTOR(dev->irq);
705 else
706 *RIEBL_IVEC_ADDR = IRQ_SOURCE_TO_VECTOR(dev->irq);
707
708 if (did_version++ == 0)
709 DPRINTK( 1, ( version ));
710
711 /* The LANCE-specific entries in the device structure. */
712 dev->open = &lance_open;
713 dev->hard_start_xmit = &lance_start_xmit;
714 dev->stop = &lance_close;
715 dev->get_stats = &lance_get_stats;
716 dev->set_multicast_list = &set_multicast_list;
717 dev->set_mac_address = &lance_set_mac_address;
718 dev->start = 0;
719
720 memset( &lp->stats, 0, sizeof(lp->stats) );
721
722 return( 1 );
723 }
724
725
726 static int lance_open( struct net_device *dev )
727
728 { struct lance_private *lp = (struct lance_private *)dev->priv;
729 struct lance_ioreg *IO = lp->iobase;
730 int i;
731
732 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
733
734 lance_init_ring(dev);
735 /* Re-initialize the LANCE, and start it when done. */
736
737 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
738 REGA( CSR2 ) = 0;
739 REGA( CSR1 ) = 0;
740 REGA( CSR0 ) = CSR0_INIT;
741 /* From now on, AREG is kept to point to CSR0 */
742
743 i = 1000000;
744 while (--i > 0)
745 if (DREG & CSR0_IDON)
746 break;
747 if (i < 0 || (DREG & CSR0_ERR)) {
748 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
749 dev->name, i, DREG ));
750 DREG = CSR0_STOP;
751 return( -EIO );
752 }
753 DREG = CSR0_IDON;
754 DREG = CSR0_STRT;
755 DREG = CSR0_INEA;
756
757 dev->tbusy = 0;
758 dev->interrupt = 0;
759 dev->start = 1;
760
761 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
762 MOD_INC_USE_COUNT;
763
764 return( 0 );
765 }
766
767
768 /* Initialize the LANCE Rx and Tx rings. */
769
770 static void lance_init_ring( struct net_device *dev )
771
772 { struct lance_private *lp = (struct lance_private *)dev->priv;
773 int i;
774 unsigned offset;
775
776 lp->lock = 0;
777 lp->tx_full = 0;
778 lp->cur_rx = lp->cur_tx = 0;
779 lp->dirty_tx = 0;
780
781 offset = offsetof( struct lance_memory, packet_area );
782
783 /* If the packet buffer at offset 'o' would conflict with the reserved area
784 * of RieblCards, advance it */
785 #define CHECK_OFFSET(o) \
786 do { \
787 if (lp->cardtype == OLD_RIEBL || lp->cardtype == NEW_RIEBL) { \
788 if (((o) < RIEBL_RSVD_START) ? (o)+PKT_BUF_SZ > RIEBL_RSVD_START \
789 : (o) < RIEBL_RSVD_END) \
790 (o) = RIEBL_RSVD_END; \
791 } \
792 } while(0)
793
794 for( i = 0; i < TX_RING_SIZE; i++ ) {
795 CHECK_OFFSET(offset);
796 MEM->tx_head[i].base = offset;
797 #ifdef NORMAL_MEM_ACCESS
798 MEM->tx_head[i].flag = TMD1_OWN_HOST;
799 MEM->tx_head[i].base_hi = LANCE_HI_BASE;
800 #else
801 MEM->tx_head[i].flag_base_hi =
802 (TMD1_OWN_HOST<<8) | LANCE_HI_BASE;
803 #endif
804 MEM->tx_head[i].length = 0;
805 MEM->tx_head[i].misc = 0;
806 offset += PKT_BUF_SZ;
807 }
808
809 for( i = 0; i < RX_RING_SIZE; i++ ) {
810 CHECK_OFFSET(offset);
811 MEM->rx_head[i].base = offset;
812 #ifdef NORMAL_MEM_ACCESS
813 MEM->rx_head[i].flag = TMD1_OWN_CHIP;
814 MEM->rx_head[i].base_hi = LANCE_HI_BASE;
815 #else
816 MEM->rx_head[i].flag_base_hi =
817 (TMD1_OWN_CHIP<<8) | LANCE_HI_BASE;
818 #endif
819 MEM->rx_head[i].buf_length = -PKT_BUF_SZ;
820 MEM->rx_head[i].msg_length = 0;
821 offset += PKT_BUF_SZ;
822 }
823 }
824
825
826 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
827
828 { struct lance_private *lp = (struct lance_private *)dev->priv;
829 struct lance_ioreg *IO = lp->iobase;
830 int entry, len;
831 struct lance_tx_head *head;
832 unsigned long flags;
833
834 /* Transmitter timeout, serious problems. */
835 if (dev->tbusy) {
836 int tickssofar = jiffies - dev->trans_start;
837 if (tickssofar < 20)
838 return( 1 );
839 AREG = CSR0;
840 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
841 dev->name, DREG ));
842 DREG = CSR0_STOP;
843 /*
844 * Always set BSWP after a STOP as STOP puts it back into
845 * little endian mode.
846 */
847 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
848 lp->stats.tx_errors++;
849 #ifndef final_version
850 { int i;
851 DPRINTK( 2, ( "Ring data: dirty_tx %d cur_tx %d%s cur_rx %d\n",
852 lp->dirty_tx, lp->cur_tx,
853 lp->tx_full ? " (full)" : "",
854 lp->cur_rx ));
855 for( i = 0 ; i < RX_RING_SIZE; i++ )
856 DPRINTK( 2, ( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
857 i, MEM->rx_head[i].base,
858 -MEM->rx_head[i].buf_length,
859 MEM->rx_head[i].msg_length ));
860 for( i = 0 ; i < TX_RING_SIZE; i++ )
861 DPRINTK( 2, ( "tx #%d: base=%04x len=%04x misc=%04x\n",
862 i, MEM->tx_head[i].base,
863 -MEM->tx_head[i].length,
864 MEM->tx_head[i].misc ));
865 }
866 #endif
867 lance_init_ring(dev);
868 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
869
870 dev->tbusy = 0;
871 dev->trans_start = jiffies;
872
873 return( 0 );
874 }
875
876 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
877 dev->name, DREG ));
878
879 /* Block a timer-based transmit from overlapping. This could better be
880 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
881 if (test_and_set_bit( 0, (void*)&dev->tbusy ) != 0) {
882 DPRINTK( 0, ( "%s: Transmitter access conflict.\n", dev->name ));
883 return 1;
884 }
885
886 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
887 DPRINTK( 0, ( "%s: tx queue lock!.\n", dev->name ));
888 /* don't clear dev->tbusy flag. */
889 return 1;
890 }
891
892 /* Fill in a Tx ring entry */
893 if (lance_debug >= 3) {
894 u_char *p;
895 int i;
896 printk( "%s: TX pkt type 0x%04x from ", dev->name,
897 ((u_short *)skb->data)[6]);
898 for( p = &((u_char *)skb->data)[6], i = 0; i < 6; i++ )
899 printk("%02x%s", *p++, i != 5 ? ":" : "" );
900 printk(" to ");
901 for( p = (u_char *)skb->data, i = 0; i < 6; i++ )
902 printk("%02x%s", *p++, i != 5 ? ":" : "" );
903 printk(" data at 0x%08x len %d\n", (int)skb->data,
904 (int)skb->len );
905 }
906
907 /* We're not prepared for the int until the last flags are set/reset. And
908 * the int may happen already after setting the OWN_CHIP... */
909 save_flags(flags);
910 cli();
911
912 /* Mask to ring buffer boundary. */
913 entry = lp->cur_tx & TX_RING_MOD_MASK;
914 head = &(MEM->tx_head[entry]);
915
916 /* Caution: the write order is important here, set the "ownership" bits
917 * last.
918 */
919
920 /* The old LANCE chips doesn't automatically pad buffers to min. size. */
921 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
922 /* PAM-Card has a bug: Can only send packets with even number of bytes! */
923 if (lp->cardtype == PAM_CARD && (len & 1))
924 ++len;
925
926 head->length = -len;
927 head->misc = 0;
928 lp->memcpy_f( PKTBUF_ADDR(head), (void *)skb->data, skb->len );
929 #ifdef NORMAL_MEM_ACCESS
930 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
931 #else
932 SET_FLAG(head,(TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP));
933 #endif
934 dev_kfree_skb( skb );
935 lp->cur_tx++;
936 lp->stats.tx_bytes += skb->len;
937 while( lp->cur_tx >= TX_RING_SIZE && lp->dirty_tx >= TX_RING_SIZE ) {
938 lp->cur_tx -= TX_RING_SIZE;
939 lp->dirty_tx -= TX_RING_SIZE;
940 }
941
942 /* Trigger an immediate send poll. */
943 DREG = CSR0_INEA | CSR0_TDMD;
944 dev->trans_start = jiffies;
945
946 lp->lock = 0;
947 #ifdef NORMAL_MEM_ACCESS
948 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
949 #else
950 if ((GET_FLAG(&MEM->tx_head[(entry+1) & TX_RING_MOD_MASK]) & TMD1_OWN) ==
951 #endif
952 TMD1_OWN_HOST)
953 dev->tbusy = 0;
954 else
955 lp->tx_full = 1;
956 restore_flags(flags);
957
958 return 0;
959 }
960
961 /* The LANCE interrupt handler. */
962
963 static void lance_interrupt( int irq, void *dev_id, struct pt_regs *fp)
964 {
965 struct net_device *dev = dev_id;
966 struct lance_private *lp;
967 struct lance_ioreg *IO;
968 int csr0, boguscnt = 10;
969
970 if (dev == NULL) {
971 DPRINTK( 1, ( "lance_interrupt(): interrupt for unknown device.\n" ));
972 return;
973 }
974
975 lp = (struct lance_private *)dev->priv;
976 IO = lp->iobase;
977 AREG = CSR0;
978
979 if (dev->interrupt) {
980 DPRINTK( 1, ( "Re-entering CAUSE=%08x STATUS=%08x\n",
981 read_32bit_cp0_register(CP0_CAUSE),
982 read_32bit_cp0_register(CP0_STATUS) ));
983 panic("lance: interrupt handler reentered !");
984 }
985
986 dev->interrupt = 1;
987
988 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) &&
989 --boguscnt >= 0) {
990 /* Acknowledge all of the current interrupt sources ASAP. */
991 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
992 CSR0_TDMD | CSR0_INEA);
993
994 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
995 dev->name, csr0, DREG ));
996
997 if (csr0 & CSR0_RINT) /* Rx interrupt */
998 lance_rx( dev );
999
1000 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
1001 int dirty_tx = lp->dirty_tx;
1002
1003 while( dirty_tx < lp->cur_tx) {
1004 int entry = dirty_tx & TX_RING_MOD_MASK;
1005 #ifdef NORMAL_MEM_ACCESS
1006 int status = MEM->tx_head[entry].flag;
1007 #else
1008 int status = GET_FLAG(&MEM->tx_head[entry]);
1009 #endif
1010 if (status & TMD1_OWN_CHIP)
1011 break; /* It still hasn't been Txed */
1012
1013 #ifdef NORMAL_MEM_ACCESS
1014 MEM->tx_head[entry].flag = 0;
1015 #else
1016 SET_FLAG(&MEM->tx_head[entry],0);
1017 #endif
1018
1019 if (status & TMD1_ERR) {
1020 /* There was an major error, log it. */
1021 int err_status = MEM->tx_head[entry].misc;
1022 lp->stats.tx_errors++;
1023 if (err_status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
1024 if (err_status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
1025 if (err_status & TMD3_LCOL) lp->stats.tx_window_errors++;
1026 if (err_status & TMD3_UFLO) {
1027 /* Ackk! On FIFO errors the Tx unit is turned off! */
1028 lp->stats.tx_fifo_errors++;
1029 /* Remove this verbosity later! */
1030 DPRINTK( 1, ( "%s: Tx FIFO error! Status %04x\n",
1031 dev->name, csr0 ));
1032 /* Restart the chip. */
1033 DREG = CSR0_STRT;
1034 }
1035 } else {
1036 if (status & (TMD1_MORE | TMD1_ONE | TMD1_DEF))
1037 lp->stats.collisions++;
1038 lp->stats.tx_packets++;
1039 }
1040 dirty_tx++;
1041 }
1042
1043 #ifndef final_version
1044 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1045 DPRINTK( 0, ( "out-of-sync dirty pointer,"
1046 " %d vs. %d, full=%d.\n",
1047 dirty_tx, lp->cur_tx, lp->tx_full ));
1048 dirty_tx += TX_RING_SIZE;
1049 }
1050 #endif
1051
1052 if (lp->tx_full && dev->tbusy
1053 && dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1054 /* The ring is no longer full, clear tbusy. */
1055 lp->tx_full = 0;
1056 dev->tbusy = 0;
1057 mark_bh( NET_BH );
1058 }
1059
1060 lp->dirty_tx = dirty_tx;
1061 }
1062
1063 /* Log misc errors. */
1064 if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */
1065 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */
1066 if (csr0 & CSR0_MERR) {
1067 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
1068 "status %04x.\n", dev->name, csr0 ));
1069 /* Restart the chip. */
1070 DREG = CSR0_STRT;
1071 }
1072 }
1073
1074 /* Clear any other interrupt, and set interrupt enable. */
1075 DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
1076 CSR0_IDON | CSR0_INEA;
1077
1078 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
1079 dev->name, DREG ));
1080 dev->interrupt = 0;
1081 return;
1082 }
1083
1084
1085 static int lance_rx( struct net_device *dev )
1086
1087 { struct lance_private *lp = (struct lance_private *)dev->priv;
1088 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1089 int i;
1090
1091 #ifdef NORMAL_MEM_ACCESS
1092 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1093 MEM->rx_head[entry].flag ));
1094 #else
1095 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1096 GET_FLAG(&MEM->rx_head[entry]) ));
1097 #endif
1098
1099 /* If we own the next entry, it's a new packet. Send it up. */
1100 #ifdef NORMAL_MEM_ACCESS
1101 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
1102 #else
1103 while( (GET_FLAG(&MEM->rx_head[entry]) & RMD1_OWN) == RMD1_OWN_HOST ) {
1104 #endif
1105 struct lance_rx_head *head = &(MEM->rx_head[entry]);
1106 #ifdef NORMAL_MEM_ACCESS
1107 int status = head->flag;
1108 #else
1109 int status = GET_FLAG(head);
1110 #endif
1111
1112 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
1113 /* There is a tricky error noted by John Murphy,
1114 <murf@perftech.com> to Russ Nelson: Even with full-sized
1115 buffers it's possible for a jabber packet to use two
1116 buffers, with only the last correctly noting the error. */
1117 if (status & RMD1_ENP) /* Only count a general error at the */
1118 lp->stats.rx_errors++; /* end of a packet.*/
1119 if (status & RMD1_FRAM) lp->stats.rx_frame_errors++;
1120 if (status & RMD1_OFLO) lp->stats.rx_over_errors++;
1121 if (status & RMD1_CRC) lp->stats.rx_crc_errors++;
1122 if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++;
1123 #ifdef NORMAL_MEM_ACCESS
1124 head->flag &= (RMD1_ENP|RMD1_STP);
1125 #else
1126 SET_FLAG(head,GET_FLAG(head) & (RMD1_ENP|RMD1_STP));
1127 #endif
1128 } else {
1129 /* Malloc up new buffer, compatible with net-3. */
1130 short pkt_len = head->msg_length & 0xfff;
1131 struct sk_buff *skb;
1132
1133 if (pkt_len < 60) {
1134 printk( "%s: Runt packet!\n", dev->name );
1135 lp->stats.rx_errors++;
1136 }
1137 else {
1138 skb = dev_alloc_skb( pkt_len+2 );
1139 if (skb == NULL) {
1140 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
1141 dev->name ));
1142 for( i = 0; i < RX_RING_SIZE; i++ )
1143 #ifdef NORMAL_MEM_ACCESS
1144 if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag &
1145 #else
1146 if (GET_FLAG(&MEM->rx_head[(entry+i) & \
1147 RX_RING_MOD_MASK]) &
1148 #endif
1149 RMD1_OWN_CHIP)
1150 break;
1151
1152 if (i > RX_RING_SIZE - 2) {
1153 lp->stats.rx_dropped++;
1154 #ifdef NORMAL_MEM_ACCESS
1155 head->flag |= RMD1_OWN_CHIP;
1156 #else
1157 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1158 #endif
1159 lp->cur_rx++;
1160 }
1161 break;
1162 }
1163
1164 if (lance_debug >= 3) {
1165 u_char *data = PKTBUF_ADDR(head), *p;
1166 printk( "%s: RX pkt type 0x%04x from ", dev->name,
1167 ((u_short *)data)[6]);
1168 for( p = &data[6], i = 0; i < 6; i++ )
1169 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1170 printk(" to ");
1171 for( p = data, i = 0; i < 6; i++ )
1172 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1173 printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
1174 "len %d\n",
1175 data[15], data[16], data[17], data[18],
1176 data[19], data[20], data[21], data[22],
1177 pkt_len );
1178 }
1179
1180 skb->dev = dev;
1181 skb_reserve( skb, 2 ); /* 16 byte align */
1182 skb_put( skb, pkt_len ); /* Make room */
1183 lp->memcpy_f( skb->data, PKTBUF_ADDR(head), pkt_len );
1184 skb->protocol = eth_type_trans( skb, dev );
1185 netif_rx( skb );
1186 lp->stats.rx_packets++;
1187 lp->stats.rx_bytes += skb->len;
1188 }
1189 }
1190
1191 #ifdef NORMAL_MEM_ACCESS
1192 head->flag |= RMD1_OWN_CHIP;
1193 #else
1194 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1195 #endif
1196 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1197 }
1198 lp->cur_rx &= RX_RING_MOD_MASK;
1199
1200 /* From lance.c (Donald Becker): */
1201 /* We should check that at least two ring entries are free. If not,
1202 we should free one and mark stats->rx_dropped++. */
1203
1204 return 0;
1205 }
1206
1207
1208 static int lance_close( struct net_device *dev )
1209
1210 { struct lance_private *lp = (struct lance_private *)dev->priv;
1211 struct lance_ioreg *IO = lp->iobase;
1212
1213 dev->start = 0;
1214 dev->tbusy = 1;
1215
1216 AREG = CSR0;
1217
1218 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
1219 dev->name, DREG ));
1220
1221 /* We stop the LANCE here -- it occasionally polls
1222 memory if we don't. */
1223 DREG = CSR0_STOP;
1224
1225 MOD_DEC_USE_COUNT;
1226 return 0;
1227 }
1228
1229
1230 static struct net_device_stats *lance_get_stats( struct net_device *dev )
1231
1232 {
1233 struct lance_private *lp = (struct lance_private *)dev->priv;
1234 return &lp->stats;
1235 }
1236
1237
1238 /* Set or clear the multicast filter for this adaptor.
1239 num_addrs == -1 Promiscuous mode, receive all packets
1240 num_addrs == 0 Normal mode, clear multicast list
1241 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1242 best-effort filtering.
1243 */
1244
1245 static void set_multicast_list( struct net_device *dev )
1246
1247 { struct lance_private *lp = (struct lance_private *)dev->priv;
1248 struct lance_ioreg *IO = lp->iobase;
1249
1250 if (!dev->start)
1251 /* Only possible if board is already started */
1252 return;
1253
1254 /* We take the simple way out and always enable promiscuous mode. */
1255 DREG = CSR0_STOP; /* Temporarily stop the lance. */
1256
1257 if (dev->flags & IFF_PROMISC) {
1258 /* Log any net taps. */
1259 DPRINTK( 1, ( "%s: Promiscuous mode enabled.\n", dev->name ));
1260 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
1261 } else {
1262 short multicast_table[4];
1263 int num_addrs = dev->mc_count;
1264 int i;
1265 /* We don't use the multicast table, but rely on upper-layer
1266 * filtering. */
1267 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
1268 sizeof(multicast_table) );
1269 for( i = 0; i < 4; i++ )
1270 REGA( CSR8+i ) = multicast_table[i];
1271 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
1272 }
1273
1274 /*
1275 * Always set BSWP after a STOP as STOP puts it back into
1276 * little endian mode.
1277 */
1278 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
1279
1280 /* Resume normal operation and reset AREG to CSR0 */
1281 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
1282 }
1283
1284
1285 /* This is needed for old RieblCards and possible for new RieblCards */
1286
1287 static int lance_set_mac_address( struct net_device *dev, void *addr )
1288
1289 { struct lance_private *lp = (struct lance_private *)dev->priv;
1290 struct sockaddr *saddr = addr;
1291 int i;
1292
1293 if (lp->cardtype != OLD_RIEBL && lp->cardtype != NEW_RIEBL)
1294 return( -EOPNOTSUPP );
1295
1296 if (dev->start) {
1297 /* Only possible while card isn't started */
1298 DPRINTK( 1, ( "%s: hwaddr can be set only while card isn't open.\n",
1299 dev->name ));
1300 return( -EIO );
1301 }
1302
1303 slow_memcpy( dev->dev_addr, saddr->sa_data, dev->addr_len );
1304
1305 {
1306 unsigned char hwaddr[6];
1307 for( i = 0; i < 6; i++ )
1308 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
1309 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
1310 }
1311
1312 lp->memcpy_f( RIEBL_HWADDR_ADDR, dev->dev_addr, 6 );
1313 /* set also the magic for future sessions */
1314 #ifdef NORMAL_MEM_ACCESS
1315 *RIEBL_MAGIC_ADDR = RIEBL_MAGIC;
1316 #else
1317 {
1318 unsigned long magic = RIEBL_MAGIC;
1319 slow_memcpy(RIEBL_MAGIC_ADDR, &magic, sizeof(*RIEBL_MAGIC_ADDR));
1320 }
1321 #endif
1322 return( 0 );
1323 }
1324
1325
1326 #ifdef MODULE
1327 static char devicename[9] = { 0, };
1328
1329 static struct net_device bagetlance_dev =
1330 {
1331 devicename, /* filled in by register_netdev() */
1332 0, 0, 0, 0, /* memory */
1333 0, 0, /* base, irq */
1334 0, 0, 0, NULL, bagetlance_probe,
1335 };
1336
1337 int init_module(void)
1338
1339 { int err;
1340
1341 if ((err = register_netdev( &bagetlance_dev ))) {
1342 if (err == -EIO) {
1343 printk( "No Vme Lance board found. Module not loaded.\n");
1344 }
1345 return( err );
1346 }
1347 return( 0 );
1348 }
1349
1350 void cleanup_module(void)
1351
1352 {
1353 unregister_netdev( &bagetlance_dev );
1354 }
1355
1356 #endif /* MODULE */
1357
1358 /*
1359 * Local variables:
1360 * c-indent-level: 4
1361 * tab-width: 4
1362 * End:
1363 */
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