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Import 2.3.18pre1
[davej-history.git] / drivers / block / ide-pci.c
blob3ba39f600f3b3174a51ab3e08ee61bf1f8dbf1a0
1 /*
2 * linux/drivers/block/ide-pci.c Version 1.04 July 27, 1999
3 *
4 * Copyright (c) 1998-1999 Andre Hedrick
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
8 */
9
10 /*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
33 #define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
34 #define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
35 #define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
36 #define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
37 #define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
38 #define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
39 #define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
40 #define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
41 #define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
42 #define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
43 #define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
44 #define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
45 #define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
46 #define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
47 #define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
48 #define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
49 #define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
50 #define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
51 #define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
52 #define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
53 #define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
54 #define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
55 #define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
56 #define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
57 #define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
58 #define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
59 #define DEVID_CX5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
60
61 #define IDE_IGNORE ((void *)-1)
62
63 #ifdef CONFIG_BLK_DEV_TRM290
64 extern void ide_init_trm290(ide_hwif_t *);
65 #define INIT_TRM290 &ide_init_trm290
66 #else
67 #define INIT_TRM290 IDE_IGNORE
68 #endif
69
70 #ifdef CONFIG_BLK_DEV_OPTI621
71 extern void ide_init_opti621(ide_hwif_t *);
72 #define INIT_OPTI621 &ide_init_opti621
73 #else
74 #define INIT_OPTI621 NULL
75 #endif
76
77 #ifdef CONFIG_BLK_DEV_NS87415
78 extern void ide_init_ns87415(ide_hwif_t *);
79 #define INIT_NS87415 &ide_init_ns87415
80 #else
81 #define INIT_NS87415 IDE_IGNORE
82 #endif
83
84 #ifdef CONFIG_BLK_DEV_CMD646
85 extern void ide_init_cmd646(ide_hwif_t *);
86 #define INIT_CMD646 &ide_init_cmd646
87 #else
88 #ifdef __sparc_v9__
89 #define INIT_CMD646 IDE_IGNORE
90 #else
91 #define INIT_CMD646 NULL
92 #endif
93 #endif
94
95 #ifdef CONFIG_BLK_DEV_SL82C105
96 extern void ide_init_sl82c105(ide_hwif_t *);
97 #define INIT_W82C105 &ide_init_sl82c105
98 #else
99 #define INIT_W82C105 IDE_IGNORE
100 #endif
101
102 #ifdef CONFIG_BLK_DEV_RZ1000
103 extern void ide_init_rz1000(ide_hwif_t *);
104 #define INIT_RZ1000 &ide_init_rz1000
105 #else
106 #define INIT_RZ1000 IDE_IGNORE
107 #endif
108
109 #ifdef CONFIG_BLK_DEV_VIA82C586
110 extern unsigned int pci_init_via82c568(struct pci_dev *, const char *);
111 extern void ide_init_via82c586(ide_hwif_t *);
112 extern void ide_dmacapable_via82c586(ide_hwif_t *, unsigned long dmabase);
113 #define PCI_VIA82C586 &pci_init_via82c568
114 #define INIT_VIA82C586 &ide_init_via82c586
115 #define DMA_VIA82C586 &ide_dmacapable_via82c586
116 #else
117 #define PCI_VIA82C586 NULL
118 #define INIT_VIA82C586 NULL
119 #define DMA_VIA82C586 NULL
120 #endif
121
122 #ifdef CONFIG_BLK_DEV_ALI15X3
123 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
124 extern void ide_init_ali15x3(ide_hwif_t *);
125 #define PCI_ALI15X3 &pci_init_ali15x3
126 #define INIT_ALI15X3 &ide_init_ali15x3
127 #else
128 #define PCI_ALI15X3 NULL
129 #define INIT_ALI15X3 NULL
130 #endif
131
132 #ifdef CONFIG_BLK_DEV_CY82C693
133 extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
134 extern void ide_init_cy82c693(ide_hwif_t *);
135 #define PCI_CY82C693 &pci_init_cy82c693
136 #define INIT_CY82C693 &ide_init_cy82c693
137 #else
138 #define PCI_CY82C693 NULL
139 #define INIT_CY82C693 NULL
140 #endif
141
142 #ifdef CONFIG_BLK_DEV_PDC202XX
143 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
144 extern void ide_init_pdc202xx(ide_hwif_t *);
145 #define PCI_PDC202XX &pci_init_pdc202xx
146 #define INIT_PDC202XX &ide_init_pdc202xx
147 #else
148 #define PCI_PDC202XX NULL
149 #define INIT_PDC202XX NULL
150 #endif
151
152 #ifdef CONFIG_BLK_DEV_PIIX
153 extern void ide_init_piix(ide_hwif_t *);
154 #define INIT_PIIX &ide_init_piix
155 #else
156 #define INIT_PIIX NULL
157 #endif
158
159 #ifdef CONFIG_BLK_DEV_AEC6210
160 extern unsigned int pci_init_aec6210(struct pci_dev *, const char *);
161 #define PCI_AEC6210 &pci_init_aec6210
162 #else
163 #define PCI_AEC6210 NULL
164 #endif
165
166 #ifdef CONFIG_BLK_DEV_HPT34X
167 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
168 extern void ide_init_hpt34x(ide_hwif_t *);
169 #define PCI_HPT34X &pci_init_hpt34x
170 #define INIT_HPT34X &ide_init_hpt34x
171 #else
172 #define PCI_HPT34X NULL
173 #define INIT_HPT34X NULL
174 #endif
175
176 #ifdef CONFIG_BLK_DEV_HPT366
177 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
178 extern void ide_init_hpt366(ide_hwif_t *);
179 #define PCI_HPT366 &pci_init_hpt366
180 #define INIT_HPT366 &ide_init_hpt366
181 #else
182 #define PCI_HPT366 NULL
183 #define INIT_HPT366 IDE_IGNORE
184 #endif
185
186 #ifdef CONFIG_BLK_DEV_SIS5513
187 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
188 extern void ide_init_sis5513(ide_hwif_t *);
189 #define PCI_SIS5513 &pci_init_sis5513
190 #define INIT_SIS5513 &ide_init_sis5513
191 #else
192 #define PCI_SIS5513 NULL
193 #define INIT_SIS5513 NULL
194 #endif
195
196 #define INIT_SAMURAI NULL
197 #define INIT_CX5530 NULL
198
199 typedef struct ide_pci_enablebit_s {
200 byte reg; /* byte pci reg holding the enable-bit */
201 byte mask; /* mask to isolate the enable-bit */
202 byte val; /* value of masked reg when "enabled" */
203 } ide_pci_enablebit_t;
204
205 typedef struct ide_pci_device_s {
206 ide_pci_devid_t devid;
207 const char *name;
208 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
209 void (*init_hwif)(ide_hwif_t *hwif);
210 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
211 ide_pci_enablebit_t enablebits[2];
212 byte bootable;
213 byte sixtysix;
214 unsigned int extra;
215 } ide_pci_device_t;
216
217 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
218 {DEVID_PIIXa, "PIIX", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
219 {DEVID_PIIXb, "PIIX", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
220 {DEVID_PIIX3, "PIIX3", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
221 {DEVID_PIIX4, "PIIX4", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
222 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
223 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82C586, INIT_VIA82C586, DMA_VIA82C586, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0, 0 },
224 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 0, 16 },
225 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 1, 48 },
226 {DEVID_RZ1000, "RZ1000", NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
227 {DEVID_RZ1001, "RZ1001", NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
228 {DEVID_SAMURAI, "SAMURAI", NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
229 {DEVID_CMD640, "CMD640", NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
230 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0, 0 },
231 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 1, 0 },
232 {DEVID_CMD643, "CMD643", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
233 {DEVID_CMD646, "CMD646", NULL, INIT_CMD646, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0, 0 },
234 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
235 {DEVID_OPTI621, "OPTI621", NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
236 {DEVID_OPTI621X,"OPTI621X", NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
237 {DEVID_TRM290, "TRM290", NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
238 {DEVID_NS87415, "NS87415", NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
239 {DEVID_AEC6210, "AEC6210", PCI_AEC6210, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, 0 },
240 {DEVID_W82C105, "W82C105", NULL, INIT_W82C105, NULL, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0, 0 },
241 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
242 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
243 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0, 16 },
244 {DEVID_HPT366, "HPT366", PCI_HPT366, INIT_HPT366, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 1, 256 },
245 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, INIT_ALI15X3, NULL, {{0x09,0x20,0x20}, {0x09,0x10,0x10}}, ON_BOARD, 0, 0 },
246 {DEVID_CY82C693,"CY82C693", PCI_CY82C693, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
247 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
248 {DEVID_CX5530, "CX5530", NULL, INIT_CX5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
249 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 }};
250
251 static byte hpt363_shared_irq = 0;
252
253 /*
254 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
255 * settings of split-mirror pci-config space, place chipset into init-mode,
256 * and/or preserve an interrupt if the card is not native ide support.
257 */
258 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
259 {
260 switch(dev->device) {
261 case PCI_DEVICE_ID_TTI_HPT343:
262 {
263 unsigned short pcicmd = 0;
264
265 pci_write_config_byte(dev, 0x80, 0x00);
266 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
267 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
268 int i;
269 unsigned long hpt34xIoBase = dev->resource[4].start;
270
271 dev->resource[0].start = (hpt34xIoBase + 0x20);
272 dev->resource[1].start = (hpt34xIoBase + 0x34);
273 dev->resource[2].start = (hpt34xIoBase + 0x28);
274 dev->resource[3].start = (hpt34xIoBase + 0x3c);
275 for(i=0; i<4; i++)
276 dev->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
277 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
278 } else {
279 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
280 }
281 }
282 case PCI_DEVICE_ID_TTI_HPT366:
283 case PCI_DEVICE_ID_PROMISE_20246:
284 case PCI_DEVICE_ID_PROMISE_20262:
285 case PCI_DEVICE_ID_ARTOP_ATP850UF:
286 return dev->irq;
287 default:
288 break;
289 }
290 return 0;
291 }
292
293 /*
294 * Match a PCI IDE port against an entry in ide_hwifs[],
295 * based on io_base port if possible.
296 */
297 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
298 {
299 int h;
300 ide_hwif_t *hwif;
301
302 /*
303 * Look for a hwif with matching io_base specified using
304 * parameters to ide_setup().
305 */
306 for (h = 0; h < MAX_HWIFS; ++h) {
307 hwif = &ide_hwifs[h];
308 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
309 if (hwif->chipset == ide_generic)
310 return hwif; /* a perfect match */
311 }
312 }
313 /*
314 * Look for a hwif with matching io_base default value.
315 * If chipset is "ide_unknown", then claim that hwif slot.
316 * Otherwise, some other chipset has already claimed it.. :(
317 */
318 for (h = 0; h < MAX_HWIFS; ++h) {
319 hwif = &ide_hwifs[h];
320 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
321 if (hwif->chipset == ide_unknown)
322 return hwif; /* match */
323 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
324 return NULL; /* already claimed */
325 }
326 }
327 /*
328 * Okay, there is no hwif matching our io_base,
329 * so we'll just claim an unassigned slot.
330 * Give preference to claiming other slots before claiming ide0/ide1,
331 * just in case there's another interface yet-to-be-scanned
332 * which uses ports 1f0/170 (the ide0/ide1 defaults).
333 *
334 * Unless there is a bootable card that does not use the standard
335 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
336 */
337 if (bootable) {
338 for (h = 0; h < MAX_HWIFS; ++h) {
339 hwif = &ide_hwifs[h];
340 if (hwif->chipset == ide_unknown)
341 return hwif; /* pick an unused entry */
342 }
343 } else {
344 for (h = 2; h < MAX_HWIFS; ++h) {
345 hwif = ide_hwifs + h;
346 if (hwif->chipset == ide_unknown)
347 return hwif; /* pick an unused entry */
348 }
349 }
350 for (h = 0; h < 2; ++h) {
351 hwif = ide_hwifs + h;
352 if (hwif->chipset == ide_unknown)
353 return hwif; /* pick an unused entry */
354 }
355 printk("%s: too many IDE interfaces, no room in table\n", name);
356 return NULL;
357 }
358
359 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
360 {
361 byte reg, progif = 0;
362
363 /*
364 * Place both IDE interfaces into PCI "native" mode:
365 */
366 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
367 if ((progif & 0xa) != 0xa) {
368 printk("%s: device not capable of full native PCI mode\n", name);
369 return 1;
370 }
371 printk("%s: placing both ports into native PCI mode\n", name);
372 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
373 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
374 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
375 return 1;
376 }
377 }
378 /*
379 * Setup base registers for IDE command/control spaces for each interface:
380 */
381 for (reg = 0; reg < 4; reg++) {
382 struct resource *res = dev->resource + reg;
383 if (!(res->flags & PCI_BASE_ADDRESS_SPACE_IO))
384 continue;
385 if (!res->start) {
386 printk("%s: Missing I/O address #%d\n", name, reg);
387 return 1;
388 }
389 }
390 return 0;
391 }
392
393 /*
394 * ide_setup_pci_device() looks at the primary/secondary interfaces
395 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
396 * for use with them. This generic code works for most PCI chipsets.
397 *
398 * One thing that is not standardized is the location of the
399 * primary/secondary interface "enable/disable" bits. For chipsets that
400 * we "know" about, this information is in the ide_pci_device_t struct;
401 * for all other chipsets, we just assume both interfaces are enabled.
402 */
403 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
404 {
405 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
406 unsigned short pcicmd = 0, tried_config = 0;
407 byte tmp = 0;
408 ide_hwif_t *hwif, *mate = NULL;
409
410 #ifdef CONFIG_IDEDMA_AUTO
411 autodma = 1;
412 #endif
413 check_if_enabled:
414 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
415 printk("%s: error accessing PCI regs\n", d->name);
416 return;
417 }
418 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
419 /*
420 * PnP BIOS was *supposed* to have set this device up for us,
421 * but we can do it ourselves, so long as the BIOS has assigned an IRQ
422 * (or possibly the device is using a "legacy header" for IRQs).
423 * Maybe the user deliberately *disabled* the device,
424 * but we'll eventually ignore it again if no drives respond.
425 */
426 if (tried_config++
427 || ide_setup_pci_baseregs(dev, d->name)
428 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
429 printk("%s: device disabled (BIOS)\n", d->name);
430 return;
431 }
432 autodma = 0; /* default DMA off if we had to configure it here */
433 goto check_if_enabled;
434 }
435 if (tried_config)
436 printk("%s: device enabled (Linux)\n", d->name);
437 /*
438 * Can we trust the reported IRQ?
439 */
440 pciirq = dev->irq;
441 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
442 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
443 /*
444 * This allows offboard ide-pci cards the enable a BIOS,
445 * verify interrupt settings of split-mirror pci-config
446 * space, place chipset into init-mode, and/or preserve
447 * an interrupt if the card is not native ide support.
448 */
449 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
450 } else if (tried_config) {
451 printk("%s: will probe irqs later\n", d->name);
452 pciirq = 0;
453 } else if (!pciirq) {
454 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
455 pciirq = 0;
456 } else {
457 #ifdef __sparc__
458 printk("%s: 100%% native mode on irq %s\n",
459 d->name, __irq_itoa(pciirq));
460 #else
461 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
462 #endif
463 }
464 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
465 /*
466 * Since there are two cards that report almost identically,
467 * the only discernable difference is the values
468 * reported in pcicmd.
469 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
470 * Non-bootable card or HPT343 :: pcicmd == 0x05
471 */
472 if (pcicmd & PCI_COMMAND_MEMORY) {
473 printk("%s: is IDE Express HPT363.\n", d->name);
474 d->bootable = OFF_BOARD;
475 }
476 }
477 /*
478 * Set up the IDE ports
479 */
480 for (port = 0; port <= 1; ++port) {
481 unsigned long base = 0, ctl = 0;
482 ide_pci_enablebit_t *e = &(d->enablebits[port]);
483 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
484 continue; /* port not enabled */
485 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port))
486 return;
487 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
488 ctl = dev->resource[(2*port)+1].start;
489 base = dev->resource[2*port].start;
490 if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
491 !(base & PCI_BASE_ADDRESS_IO_MASK)) {
492 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@suse.com>.\n", d->name);
493 #if 0
494 /* FIXME! This really should check that it really gets the IO/MEM part right! */
495 continue;
496 #endif
497 }
498 }
499 if ((ctl && !base) || (base && !ctl)) {
500 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
501 continue;
502 }
503 if (!ctl)
504 ctl = port ? 0x374 : 0x3f4; /* use default value */
505 if (!base)
506 base = port ? 0x170 : 0x1f0; /* use default value */
507 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
508 continue; /* no room in ide_hwifs[] */
509 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
510 ide_init_hwif_ports(&hwif->hw, base, (ctl + 2), NULL);
511 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
512 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
513 }
514 hwif->chipset = ide_pci;
515 hwif->pci_dev = dev;
516 hwif->pci_devid = d->devid;
517 hwif->channel = port;
518 if (!hwif->irq)
519 hwif->irq = pciirq;
520 if (mate) {
521 hwif->mate = mate;
522 mate->mate = hwif;
523 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
524 hwif->serialized = 1;
525 mate->serialized = 1;
526 }
527 }
528 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
529 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF)) {
530 hwif->irq = hwif->channel ? 15 : 14;
531 goto bypass_umc_dma;
532 }
533 if ((!d->sixtysix) && (hwif->udma_four))
534 hwif->udma_four = 0;
535 #ifdef CONFIG_BLK_DEV_IDEDMA
536 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
537 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
538 autodma = 0;
539 if (autodma)
540 hwif->autodma = 1;
541 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
542 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
543 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
544 #ifdef CONFIG_BLK_DEV_HPT34X
545 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
546 #endif /* CONFIG_BLK_DEV_HPT34X */
547 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
548 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
549 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
550 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
551 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
552 /*
553 * Set up BM-DMA capability (PnP BIOS should have done this)
554 */
555 hwif->autodma = 0; /* default DMA off if we had to configure it here */
556 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
557 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
558 printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
559 dma_base = 0;
560 }
561 }
562 if (dma_base) {
563 if (d->dma_init) {
564 d->dma_init(hwif, dma_base);
565 } else {
566 ide_setup_dma(hwif, dma_base, 8);
567 }
568 } else {
569 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
570 }
571 }
572 #endif /* CONFIG_BLK_DEV_IDEDMA */
573 bypass_umc_dma:
574 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
575 d->init_hwif(hwif);
576 mate = hwif;
577 at_least_one_hwif_enabled = 1;
578 }
579 if (!at_least_one_hwif_enabled)
580 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
581 }
582
583 static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
584 {
585 struct pci_dev *dev2;
586 ide_pci_device_t *d2;
587 unsigned char pin1 = 0, pin2 = 0;
588
589 d2 = d;
590 if (PCI_FUNC(dev->devfn) & 1)
591 return;
592
593 for (dev2=pci_devices; dev2; dev2=dev2->next) {
594 if ((dev2->vendor == dev->vendor) &&
595 (dev2->device == dev->device) &&
596 (PCI_FUNC(dev2->devfn) & 1))
597 break;
598 }
599 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
600 if (dev2) {
601 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
602 hpt363_shared_irq = (pin1 != pin2) ? 1 : 0;
603 }
604
605 if (hpt363_shared_irq) {
606 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
607 d->name, pin1, pin2);
608 }
609
610 printk("%s: IDE controller on PCI bus %02x dev %02x\n",
611 d->name, dev->bus->number, dev->devfn);
612 ide_setup_pci_device(dev, d);
613
614 if (dev2 && !hpt363_shared_irq) {
615 printk("%s: IDE controller on PCI bus %02x dev %02x\n",
616 d2->name, dev2->bus->number, dev2->devfn);
617 ide_setup_pci_device(dev2, d2);
618 }
619 }
620
621 /*
622 * ide_scan_pcibus() gets invoked at boot time from ide.c.
623 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
624 */
625 void __init ide_scan_pcibus (void)
626 {
627 struct pci_dev *dev;
628 ide_pci_devid_t devid;
629 ide_pci_device_t *d;
630
631 if (!pci_present())
632 return;
633 for(dev = pci_devices; dev; dev=dev->next) {
634 devid.vid = dev->vendor;
635 devid.did = dev->device;
636 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
637 if (d->init_hwif == IDE_IGNORE)
638 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
639 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
640 continue; /* OPTI Viper-M uses same devid for functions 0 and 1 */
641 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
642 continue; /* CY82C693 is more than only a IDE controller */
643 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
644 continue; /* UM8886A/BF pair */
645 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
646 hpt366_device_order_fixup(dev, d);
647 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
648 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
649 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n",
650 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did);
651 else
652 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
653 ide_setup_pci_device(dev, d);
654 }
655 }
656 }
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