drivers/block/cmd646.c

   1 /* $Id: cmd646.c,v 1.15 1999/07/23 01:48:37 davem Exp $
   2  * cmd646.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Note, this driver is not used at all on other systems because
   4  *           there the "BIOS" has done all of the following already.
   5  *           Due to massive hardware bugs, UltraDMA is only supported
   6  *           on the 646U2 and not on the 646U.
   7  *
   8  * Copyright (C) 1998       Eddie C. Dost  (ecd@skynet.be)
   9  * Copyright (C) 1998       David S. Miller (davem@dm.cobaltmicro.com)
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <linux/delay.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17
  18 #include <asm/io.h>
  19
  20 static int cmd646_config_drive_for_dma(ide_drive_t *drive)
  21 {
  22         struct hd_driveid *id = drive->id;
  23         ide_hwif_t *hwif = HWIF(drive);
  24
  25         /* Even if the drive is not _currently_ in a DMA
  26          * mode, we succeed, and we'll enable it manually
  27          * below in cmd646_dma_onoff.
  28          *
  29          * This is done for disks only, CDROMs and other
  30          * IDE devices are just too quirky.
  31          */
  32         if((id != NULL) &&
  33            ((id->capability & 1) != 0) &&
  34            hwif->autodma &&
  35            (drive->media == ide_disk)) {
  36                 if(id->field_valid & 0x0004) {
  37                         if(id->dma_ultra & 0x0007)
  38                                 return hwif->dmaproc(ide_dma_on, drive);
  39                 }
  40                 if(id->field_valid & 0x0002)
  41                         if((id->dma_mword & 0x0004) || (id->dma_1word & 0x0004))
  42                                 return hwif->dmaproc(ide_dma_on, drive);
  43         }
  44         return hwif->dmaproc(ide_dma_off_quietly, drive);
  45 }
  46
  47 /* This is fun.  -DaveM */
  48 #define IDE_SETXFER             SETFEATURES_XFER
  49 #define IDE_SETFEATURE          WIN_SETFEATURES
  50 #define IDE_DMA2_ENABLE         XFER_MW_DMA_2
  51 #define IDE_DMA1_ENABLE         XFER_MW_DMA_1
  52 #define IDE_DMA0_ENABLE         XFER_MW_DMA_0
  53 #define IDE_UDMA2_ENABLE        XFER_UDMA_2
  54 #define IDE_UDMA1_ENABLE        XFER_UDMA_1
  55 #define IDE_UDMA0_ENABLE        XFER_UDMA_0
  56
  57 static __inline__ unsigned char dma2_bits_to_command(unsigned char bits)
  58 {
  59         if(bits & 0x04)
  60                 return IDE_DMA2_ENABLE;
  61         if(bits & 0x02)
  62                 return IDE_DMA1_ENABLE;
  63         return IDE_DMA0_ENABLE;
  64 }
  65
  66 static __inline__ unsigned char udma2_bits_to_command(unsigned char bits)
  67 {
  68         if(bits & 0x04)
  69                 return IDE_UDMA2_ENABLE;
  70         if(bits & 0x02)
  71                 return IDE_UDMA1_ENABLE;
  72         return IDE_UDMA0_ENABLE;
  73 }
  74
  75 static __inline__ int wait_for_ready(ide_drive_t *drive)
  76 {
  77         int timeout = 100;
  78         byte stat;
  79
  80         while(--timeout) {
  81                 stat = GET_STAT();
  82
  83                 printk("STAT(%2x) ", stat);
  84                 if(!(stat & BUSY_STAT)) {
  85                         if((stat & READY_STAT) || (stat & ERR_STAT))
  86                                 break;
  87                 }
  88                 udelay(100);
  89         }
  90         if((stat & ERR_STAT) || timeout <= 0)
  91                 return 1;
  92         return 0;
  93 }
  94
  95 static void cmd646_do_setfeature(ide_drive_t *drive, byte command)
  96 {
  97 #if 0
  98         (void) ide_config_drive_speed(drive, command);
  99 #else
 100         unsigned long flags;
 101         byte old_select;
 102
 103         save_flags(flags);
 104         cli();
 105         printk("SELECT ");
 106         old_select = IN_BYTE(IDE_SELECT_REG);
 107         OUT_BYTE(drive->select.all, IDE_SELECT_REG);
 108         printk("SETXFER ");
 109         OUT_BYTE(IDE_SETXFER, IDE_FEATURE_REG);
 110         printk("CMND ");
 111         OUT_BYTE(command, IDE_NSECTOR_REG);
 112         printk("wait ");
 113         if(wait_for_ready(drive))
 114                 goto out;
 115         printk("SETFEATURE ");
 116         OUT_BYTE(IDE_SETFEATURE, IDE_COMMAND_REG);
 117         printk("wait ");
 118         (void) wait_for_ready(drive);
 119 out:
 120         OUT_BYTE(old_select, IDE_SELECT_REG);
 121         restore_flags(flags);
 122 #endif
 123 }
 124
 125 static void cmd646_dma2_enable(ide_drive_t *drive, unsigned long dma_base)
 126 {
 127         byte unit = (drive->select.b.unit & 0x01);
 128         byte bits = (drive->id->dma_mword | drive->id->dma_1word) & 0x07;
 129
 130         printk("CMD646: MDMA enable [");
 131         if((((drive->id->dma_mword & 0x0007) << 8) !=
 132             (drive->id->dma_mword & 0x0700)))
 133                 cmd646_do_setfeature(drive, dma2_bits_to_command(bits));
 134         printk("DMA_CAP ");
 135         outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
 136         printk("DONE]\n");
 137 }
 138
 139 static void cmd646_udma_enable(ide_drive_t *drive, unsigned long dma_base)
 140 {
 141         byte unit = (drive->select.b.unit & 0x01);
 142         byte udma_ctrl, bits = drive->id->dma_ultra & 0x07;
 143         byte udma_timing_bits;
 144
 145         printk("CMD646: UDMA enable [");
 146         if(((drive->id->dma_ultra & 0x0007) << 8) !=
 147            (drive->id->dma_ultra & 0x0700))
 148                 cmd646_do_setfeature(drive, udma2_bits_to_command(bits));
 149
 150         /* Enable DMA and UltraDMA */
 151         printk("DMA_CAP ");
 152         outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
 153
 154         udma_ctrl = inb(dma_base + 3);
 155
 156         /* Put this channel into UDMA mode. */
 157         printk("UDMA_CTRL ");
 158         udma_ctrl |= (1 << unit);
 159
 160         /* Set UDMA2 usable timings. */
 161         if(bits & 0x04)
 162                 udma_timing_bits = 0x10;
 163         else if(bits & 0x02)
 164                 udma_timing_bits = 0x20;
 165         else
 166                 udma_timing_bits = 0x30;
 167         udma_ctrl &= ~(0x30 << (unit * 2));
 168         udma_ctrl |=  (udma_timing_bits << (unit * 2));
 169
 170         outb(udma_ctrl, dma_base+3);
 171         printk("DONE]\n");
 172 }
 173
 174 static int cmd646_dma_onoff(ide_drive_t *drive, int enable)
 175 {
 176         if(enable) {
 177                 ide_hwif_t *hwif = HWIF(drive);
 178                 unsigned long dma_base = hwif->dma_base;
 179                 struct hd_driveid *id = drive->id;
 180                 unsigned int class_rev;
 181
 182                 /* UltraDMA only supported on PCI646U and PCI646U2,
 183                  * which correspond to revisions 0x03 and 0x05 respectively.
 184                  * Actually, although the CMD tech support people won't
 185                  * tell me the details, the 0x03 revision cannot support
 186                  * UDMA correctly without hardware modifications, and even
 187                  * then it only works with Quantum disks due to some
 188                  * hold time assumptions in the 646U part which are fixed
 189                  * in the 646U2.
 190                  * So we only do UltraDMA on revision 0x05 chipsets.
 191                  */
 192                 pci_read_config_dword(hwif->pci_dev,
 193                                       PCI_CLASS_REVISION,
 194                                       &class_rev);
 195                 class_rev &= 0xff;
 196                 if((class_rev == 0x05) &&
 197                    (id->field_valid & 0x0004) &&
 198                    (id->dma_ultra & 0x07)) {
 199                         /* UltraDMA modes. */
 200                         cmd646_udma_enable(drive, dma_base);
 201                 } else {
 202                         /* Normal MultiWord DMA modes. */
 203                         cmd646_dma2_enable(drive, dma_base);
 204                 }
 205         }
 206         drive->using_dma = enable;
 207         return 0;
 208 }
 209
 210 static int cmd646_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 211 {
 212         if(func == ide_dma_check)
 213                 return cmd646_config_drive_for_dma(drive);
 214         else if(func == ide_dma_on || func == ide_dma_off || func == ide_dma_off_quietly)
 215                 return cmd646_dma_onoff(drive, (func == ide_dma_on));
 216
 217         /* Other cases are done by generic IDE-DMA code. */
 218         return ide_dmaproc(func, drive);
 219 }
 220
 221 /*
 222  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 223  * event order for DMA transfers.
 224  */
 225 static int cmd646_1_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 226 {
 227         ide_hwif_t *hwif = HWIF(drive);
 228         unsigned long dma_base = hwif->dma_base;
 229         byte dma_stat;
 230
 231         if (func == ide_dma_end) {
 232                 drive->waiting_for_dma = 0;
 233                 dma_stat = inb(dma_base+2);             /* get DMA status */
 234                 outb(inb(dma_base)&~1, dma_base);       /* stop DMA */
 235                 outb(dma_stat|6, dma_base+2);   /* clear the INTR & ERROR bits */
 236                 return (dma_stat & 7) != 4;     /* verify good DMA status */
 237         }
 238
 239         /* Other cases are done by generic IDE-DMA code. */
 240         return cmd646_dmaproc(func, drive);
 241 }
 242
 243 void __init ide_init_cmd646 (ide_hwif_t *hwif)
 244 {
 245         struct pci_dev *dev = hwif->pci_dev;
 246         unsigned char mrdmode;
 247         unsigned int class_rev;
 248
 249         pci_read_config_dword(hwif->pci_dev, PCI_CLASS_REVISION, &class_rev);
 250         class_rev &= 0xff;
 251
 252         hwif->chipset = ide_cmd646;
 253
 254         /* Set a good latency timer and cache line size value. */
 255         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 256 #ifdef __sparc_v9__
 257         (void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10);
 258 #endif
 259
 260         /* Setup interrupts. */
 261         (void) pci_read_config_byte(dev, 0x71, &mrdmode);
 262         mrdmode &= ~(0x30);
 263         (void) pci_write_config_byte(dev, 0x71, mrdmode);
 264
 265         /* Use MEMORY READ LINE for reads.
 266          * NOTE: Although not mentioned in the PCI0646U specs,
 267          *       these bits are write only and won't be read
 268          *       back as set or not.  The PCI0646U2 specs clarify
 269          *       this point.
 270          */
 271         (void) pci_write_config_byte(dev, 0x71, mrdmode | 0x02);
 272
 273         /* Set reasonable active/recovery/address-setup values. */
 274         (void) pci_write_config_byte(dev, 0x53, 0x40);
 275         (void) pci_write_config_byte(dev, 0x54, 0x3f);
 276         (void) pci_write_config_byte(dev, 0x55, 0x40);
 277         (void) pci_write_config_byte(dev, 0x56, 0x3f);
 278         (void) pci_write_config_byte(dev, 0x57, 0x5c);
 279         (void) pci_write_config_byte(dev, 0x58, 0x3f);
 280         (void) pci_write_config_byte(dev, 0x5b, 0x3f);
 281
 282         if (hwif->dma_base) {
 283                 if (class_rev == 0x01) {
 284                         hwif->dmaproc = &cmd646_1_dmaproc;
 285                 } else {
 286                         hwif->dmaproc = &cmd646_dmaproc;
 287                 }
 288         }
 289 }