drivers/atm/ambassador.h

   1 /*
   2   Madge Ambassador ATM Adapter driver.
   3   Copyright (C) 1995-1999  Madge Networks Ltd.
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18
  19   The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
  20   system and in the file COPYING in the Linux kernel source.
  21 */
  22
  23 #ifndef AMBASSADOR_H
  24 #define AMBASSADOR_H
  25
  26 #include <linux/config.h>
  27
  28 #ifdef CONFIG_ATM_AMBASSADOR_DEBUG
  29 #define DEBUG_AMBASSADOR
  30 #endif
  31
  32 #define DEV_LABEL                          "amb"
  33
  34 #ifndef PCI_VENDOR_ID_MADGE
  35 #define PCI_VENDOR_ID_MADGE                0x10B6
  36 #endif
  37 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR
  38 #define PCI_DEVICE_ID_MADGE_AMBASSADOR     0x1001
  39 #endif
  40 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD
  41 #define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002
  42 #endif
  43
  44 // diagnostic output
  45
  46 #define PRINTK(severity,format,args...) \
  47   printk(severity DEV_LABEL ": " format "\n" , ## args)
  48
  49 #ifdef DEBUG_AMBASSADOR
  50
  51 #define DBG_ERR  0x0001
  52 #define DBG_WARN 0x0002
  53 #define DBG_INFO 0x0004
  54 #define DBG_INIT 0x0008
  55 #define DBG_LOAD 0x0010
  56 #define DBG_VCC  0x0020
  57 #define DBG_QOS  0x0040
  58 #define DBG_CMD  0x0080
  59 #define DBG_TX   0x0100
  60 #define DBG_RX   0x0200
  61 #define DBG_SKB  0x0400
  62 #define DBG_POOL 0x0800
  63 #define DBG_IRQ  0x1000
  64 #define DBG_FLOW 0x2000
  65 #define DBG_REGS 0x4000
  66 #define DBG_DATA 0x8000
  67 #define DBG_MASK 0xffff
  68
  69 /* the ## prevents the annoying double expansion of the macro arguments */
  70 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
  71 #define PRINTDB(bits,format,args...) \
  72   ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
  73 #define PRINTDM(bits,format,args...) \
  74   ( (debug & (bits)) ? printk (format , ## args) : 1 )
  75 #define PRINTDE(bits,format,args...) \
  76   ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
  77 #define PRINTD(bits,format,args...) \
  78   ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
  79
  80 #else
  81
  82 #define PRINTD(bits,format,args...)
  83 #define PRINTDB(bits,format,args...)
  84 #define PRINTDM(bits,format,args...)
  85 #define PRINTDE(bits,format,args...)
  86
  87 #endif
  88
  89 #define PRINTDD(bits,format,args...)
  90 #define PRINTDDB(sec,fmt,args...)
  91 #define PRINTDDM(sec,fmt,args...)
  92 #define PRINTDDE(sec,fmt,args...)
  93
  94 // tunable values (?)
  95
  96 /* MUST be powers of two -- why ? */
  97 #define COM_Q_ENTRIES        8
  98 #define TX_Q_ENTRIES        32
  99 #define RX_Q_ENTRIES        64
 100
 101 // fixed values
 102
 103 // guessing
 104 #define AMB_EXTENT         0x80
 105
 106 // Minimum allowed size for an Ambassador queue
 107 #define MIN_QUEUE_SIZE     2
 108
 109 // Ambassador microcode allows 1 to 4 pools, we use 4 (simpler)
 110 #define NUM_RX_POOLS       4
 111
 112 // minimum RX buffers required to cope with replenishing delay
 113 #define MIN_RX_BUFFERS     1
 114
 115 // minimum PCI latency we will tolerate (32 IS TOO SMALL)
 116 #define MIN_PCI_LATENCY   64 // 255
 117
 118 // VCs supported by card (VPI always 0)
 119 #define NUM_VPI_BITS       0
 120 #define NUM_VCI_BITS      10
 121 #define NUM_VCS         1024
 122
 123 /* The status field bits defined so far. */
 124 #define RX_ERR          0x8000 // always present if there is an error (hmm)
 125 #define CRC_ERR         0x4000 // AAL5 CRC error
 126 #define LEN_ERR         0x2000 // overlength frame
 127 #define ABORT_ERR       0x1000 // zero length field in received frame
 128 #define UNUSED_ERR      0x0800 // buffer returned unused
 129
 130 // Adaptor commands
 131
 132 #define SRB_OPEN_VC             0
 133 /* par_0: dwordswap(VC_number) */
 134 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
 135 /* flags:               */
 136
 137 /* LANE:        0x0004          */
 138 /* NOT_UBR:     0x0008          */
 139 /* ABR:         0x0010          */
 140
 141 /* RxPool0:     0x0000          */
 142 /* RxPool1:     0x0020          */
 143 /* RxPool2:     0x0040          */
 144 /* RxPool3:     0x0060          */
 145
 146 /* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
 147
 148 #define SRB_CLOSE_VC            1
 149 /* par_0: dwordswap(VC_number) */
 150
 151 #define SRB_GET_BIA             2
 152 /* returns              */
 153 /* par_0: dwordswap(half BIA) */
 154 /* par_1: dwordswap(half BIA) */
 155
 156 #define SRB_GET_SUNI_STATS      3
 157 /* par_0: dwordswap(physical_host_address) */
 158
 159 #define SRB_SET_BITS_8          4
 160 #define SRB_SET_BITS_16         5
 161 #define SRB_SET_BITS_32         6
 162 #define SRB_CLEAR_BITS_8        7
 163 #define SRB_CLEAR_BITS_16       8
 164 #define SRB_CLEAR_BITS_32       9
 165 /* par_0: dwordswap(ATMizer address)    */
 166 /* par_1: dwordswap(mask) */
 167
 168 #define SRB_SET_8               10
 169 #define SRB_SET_16              11
 170 #define SRB_SET_32              12
 171 /* par_0: dwordswap(ATMizer address)    */
 172 /* par_1: dwordswap(data) */
 173
 174 #define SRB_GET_32              13
 175 /* par_0: dwordswap(ATMizer address)    */
 176 /* returns                      */
 177 /* par_1: dwordswap(ATMizer data) */
 178
 179 #define SRB_GET_VERSION         14
 180 /* returns              */
 181 /* par_0: dwordswap(Major Version) */
 182 /* par_1: dwordswap(Minor Version) */
 183
 184 #define SRB_FLUSH_BUFFER_Q      15
 185 /* Only flags to define which buffer pool; all others must be zero */
 186 /* par_0: dwordswap(flags<<16) or wordswap(flags)*/
 187
 188 #define SRB_GET_DMA_SPEEDS      16
 189 /* returns              */
 190 /* par_0: dwordswap(Read speed (bytes/sec)) */
 191 /* par_1: dwordswap(Write speed (bytes/sec)) */
 192
 193 #define SRB_MODIFY_VC_RATE      17
 194 /* par_0: dwordswap(VC_number) */
 195 /* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
 196
 197 #define SRB_MODIFY_VC_FLAGS     18
 198 /* par_0: dwordswap(VC_number) */
 199 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
 200
 201 /* flags:               */
 202
 203 /* LANE:        0x0004          */
 204 /* NOT_UBR:     0x0008          */
 205 /* ABR:         0x0010          */
 206
 207 /* RxPool0:     0x0000          */
 208 /* RxPool1:     0x0020          */
 209 /* RxPool2:     0x0040          */
 210 /* RxPool3:     0x0060          */
 211
 212 #define SRB_RATE_SHIFT          16
 213 #define SRB_POOL_SHIFT          (SRB_FLAGS_SHIFT+5)
 214 #define SRB_FLAGS_SHIFT         16
 215
 216 #define SRB_STOP_TASKING        19
 217 #define SRB_START_TASKING       20
 218 #define SRB_SHUT_DOWN           21
 219 #define MAX_SRB                 21
 220
 221 #define SRB_COMPLETE            0xffffffff
 222
 223 #define TX_FRAME                0x80000000
 224
 225 // number of types of SRB MUST be a power of two -- why?
 226 #define NUM_OF_SRB      32
 227
 228 // number of bits of period info for rate
 229 #define MAX_RATE_BITS   6
 230
 231 #define TX_UBR          0x0000
 232 #define TX_UBR_CAPPED   0x0008
 233 #define TX_ABR          0x0018
 234 #define TX_FRAME_NOTCAP 0x0000
 235 #define TX_FRAME_CAPPED 0x8000
 236
 237 #define FP_155_RATE     0x24b1
 238 #define FP_25_RATE      0x1f9d
 239
 240 #define AMB_RESET       0x40
 241
 242 /* #define VERSION_NUMBER 0x01000000 // initial release */
 243 /* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */
 244 /* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */
 245
 246 /* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */
 247 /* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */
 248 /* remove race conditions on basic interface */
 249 /* indicate to the host that diagnostics */
 250 /* have finished; if failed, how and what  */
 251 /* failed */
 252 /* fix host memory test to fix PLX bug */
 253 /* allow flash upgrade and BIA upgrade directly */
 254 /*  */
 255 #define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */
 256 /* Change in download algorithm */
 257
 258 #define DMA_VALID 0xb728e149 /* completely random */
 259
 260 #define FLASH_BASE 0xa0c00000
 261 #define FLASH_SIZE 0x00020000                   /* 128K */
 262 #define BIA_BASE (FLASH_BASE+0x0001c000)        /* Flash Sector 7 */
 263 #define BIA_ADDRESS ((void *)0xa0c1c000)
 264 #define PLX_BASE 0xe0000000
 265
 266 typedef enum {
 267   host_memory_test = 1,
 268   read_adapter_memory,
 269   write_adapter_memory,
 270   adapter_start,
 271   get_version_number,
 272   interrupt_host,
 273   flash_erase_sector,
 274   adap_download_block = 0x20,
 275   adap_erase_flash,
 276   adap_run_in_iram,
 277   adap_end_download
 278 } loader_command;
 279
 280 #define BAD_COMMAND                     (-1)
 281 #define COMMAND_IN_PROGRESS             1
 282 #define COMMAND_PASSED_TEST             2
 283 #define COMMAND_FAILED_TEST             3
 284 #define COMMAND_READ_DATA_OK            4
 285 #define COMMAND_READ_BAD_ADDRESS        5
 286 #define COMMAND_WRITE_DATA_OK           6
 287 #define COMMAND_WRITE_BAD_ADDRESS       7
 288 #define COMMAND_WRITE_FLASH_FAILURE     8
 289 #define COMMAND_COMPLETE                9
 290 #define COMMAND_FLASH_ERASE_FAILURE     10
 291 #define COMMAND_WRITE_BAD_DATA          11
 292
 293 /* bit fields for mailbox[0] return values */
 294
 295 #define GPINT_TST_FAILURE               0x00000001
 296 #define SUNI_DATA_PATTERN_FAILURE       0x00000002
 297 #define SUNI_DATA_BITS_FAILURE          0x00000004
 298 #define SUNI_UTOPIA_FAILURE             0x00000008
 299 #define SUNI_FIFO_FAILURE               0x00000010
 300 #define SRAM_FAILURE                    0x00000020
 301 #define SELF_TEST_FAILURE               0x0000003f
 302
 303 /* mailbox[1] = 0 in progress, -1 on completion */
 304 /* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */
 305 /* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */
 306 /* mailbox[4],mailbox[5],mailbox[6] random failure values */
 307
 308 /* PLX/etc. memory map including command structure */
 309
 310 /* These registers may also be memory mapped in PCI memory */
 311
 312 #define UNUSED_LOADER_MAILBOXES 6
 313
 314 typedef struct {
 315   u32 stuff[16];
 316   union {
 317     struct {
 318       u32 result;
 319       u32 ready;
 320       u32 stuff[UNUSED_LOADER_MAILBOXES];
 321     } loader;
 322     struct {
 323       u32 cmd_address;
 324       u32 tx_address;
 325       u32 rx_address[NUM_RX_POOLS];
 326       u32 gen_counter;
 327       u32 spare;
 328     } adapter;
 329   } mb;
 330   u32 doorbell;
 331   u32 interrupt;
 332   u32 interrupt_control;
 333   u32 reset_control;
 334 } amb_mem;
 335
 336 /* IRQ (card to host) and doorbell (host to card) enable bits */
 337 #define AMB_INTERRUPT_BITS 0x00030000
 338 #define AMB_DOORBELL_BITS  0x00000300
 339
 340 /* loader commands */
 341
 342 #define MAX_COMMAND_DATA 13
 343 #define MAX_TRANSFER_DATA 11
 344
 345 typedef struct {
 346   u32 address;
 347   u32 count;
 348   u32 data[MAX_TRANSFER_DATA];
 349 } transfer_block;
 350
 351 typedef struct {
 352   u32 result;
 353   u32 command;
 354   union {
 355     transfer_block transfer;
 356     u32 version;
 357     u32 start;
 358     u32 data[MAX_COMMAND_DATA];
 359   } payload;
 360   u32 valid;
 361 } loader_block;
 362
 363 /* command queue */
 364
 365 /* Again all data are BIG ENDIAN */
 366
 367 typedef struct {
 368   union {
 369     struct {
 370       u32 vc;
 371       u32 flags;
 372       u32 rate;
 373     } open;
 374     struct {
 375       u32 vc;
 376       u32 rate;
 377     } modify_rate;
 378     struct {
 379       u32 vc;
 380       u32 flags;
 381     } modify_flags;
 382     struct {
 383       u32 vc;
 384     } close;
 385     struct {
 386       u32 lower4;
 387       u32 upper2;
 388     } bia;
 389     struct {
 390       u32 address;
 391     } suni;
 392     struct {
 393       u32 major;
 394       u32 minor;
 395     } version;
 396     struct {
 397       u32 read;
 398       u32 write;
 399     } speed;
 400     struct {
 401       u32 flags;
 402     } flush;
 403     struct {
 404       u32 address;
 405       u32 data;
 406     } memory;
 407     u32 par[3];
 408   } args;
 409   u32 request;
 410 } command;
 411
 412 /* transmit queues and associated structures */
 413
 414 /* The hosts transmit structure. All BIG ENDIAN; host address
 415    restricted to first 1GByte, but address passed to the card must
 416    have the top MS bit or'ed in. -- check this */
 417
 418 /* TX is described by 1+ tx_frags followed by a tx_frag_end */
 419
 420 typedef struct {
 421   u32 bytes;
 422   u32 address;
 423 } tx_frag;
 424
 425 /* apart from handle the fields here are for the adapter to play with
 426    and should be set to zero */
 427
 428 typedef struct {
 429   u32   handle;
 430   u16   vc;
 431   u16   next_descriptor_length;
 432   u32   next_descriptor;
 433 #ifdef AMB_NEW_MICROCODE
 434   u8    cpcs_uu;
 435   u8    cpi;
 436   u16   pad;
 437 #endif
 438 } tx_frag_end;
 439
 440 typedef struct {
 441   tx_frag tx_frag;
 442   tx_frag_end tx_frag_end;
 443   struct sk_buff * skb;
 444 } tx_simple;
 445
 446 #if 0
 447 typedef union {
 448   tx_frag       fragment;
 449   tx_frag_end   end_of_list;
 450 } tx_descr;
 451 #endif
 452
 453 /* this "points" to the sequence of fragments and trailer */
 454
 455 typedef struct {
 456   u16   vc;
 457   u16   tx_descr_length;
 458   u32   tx_descr_addr;
 459 } tx_in;
 460
 461 /* handle is the handle from tx_in */
 462
 463 typedef struct {
 464   u32 handle;
 465 } tx_out;
 466
 467 /* receive frame structure */
 468
 469 /* All BIG ENDIAN; handle is as passed from host; length is zero for
 470    aborted frames, and frames with errors. Header is actually VC
 471    number, lec-id is NOT yet supported. */
 472
 473 typedef struct {
 474   u32  handle;
 475   u16  vc;
 476   u16  lec_id; // unused
 477   u16  status;
 478   u16  length;
 479 } rx_out;
 480
 481 /* buffer supply structure */
 482
 483 typedef struct {
 484   u32 handle;
 485   u32 host_address;
 486 } rx_in;
 487
 488 /* This first structure is the area in host memory where the adapter
 489    writes its pointer values. These pointer values are BIG ENDIAN and
 490    reside in the same 4MB 'page' as this structure. The host gives the
 491    adapter the address of this block by sending a doorbell interrupt
 492    to the adapter after downloading the code and setting it going. The
 493    addresses have the top 10 bits set to 1010000010b -- really?
 494
 495    The host must initialise these before handing the block to the
 496    adapter. */
 497
 498 typedef struct {
 499   u32 command_start;            /* SRB commands completions */
 500   u32 command_end;              /* SRB commands completions */
 501   u32 tx_start;
 502   u32 tx_end;
 503   u32 txcom_start;              /* tx completions */
 504   u32 txcom_end;                /* tx completions */
 505   struct {
 506     u32 buffer_start;
 507     u32 buffer_end;
 508     u32 buffer_q_get;
 509     u32 buffer_q_end;
 510     u32 buffer_aptr;
 511     u32 rx_start;               /* rx completions */
 512     u32 rx_end;
 513     u32 rx_ptr;
 514     u32 buffer_size;            /* size of host buffer */
 515   } rec_struct[NUM_RX_POOLS];
 516 #ifdef AMB_NEW_MICROCODE
 517   u16 init_flags;
 518   u16 talk_block_spare;
 519 #endif
 520 } adap_talk_block;
 521
 522 /* This structure must be kept in line with the vcr image in sarmain.h
 523
 524    This is the structure in the host filled in by the adapter by
 525    GET_SUNI_STATS */
 526
 527 typedef struct {
 528   u8    racp_chcs;
 529   u8    racp_uhcs;
 530   u16   spare;
 531   u32   racp_rcell;
 532   u32   tacp_tcell;
 533   u32   flags;
 534   u32   dropped_cells;
 535   u32   dropped_frames;
 536 } suni_stats;
 537
 538 typedef enum {
 539   dead
 540 } amb_flags;
 541
 542 #define NEXTQ(current,start,limit) \
 543   ( (current)+1 < (limit) ? (current)+1 : (start) )
 544
 545 typedef struct {
 546   spinlock_t lock;
 547   unsigned int pending;
 548   unsigned int high;
 549   unsigned int maximum; // size - 1 (q implementation)
 550   command * start;
 551   command * in;
 552   command * out;
 553   command * limit;
 554 } amb_cq;
 555
 556 typedef struct {
 557   spinlock_t lock;
 558   unsigned int pending;
 559   unsigned int high;
 560   unsigned int filled;
 561   unsigned int maximum; // size - 1 (q implementation)
 562   struct {
 563     tx_in * start;
 564     tx_in * ptr;
 565     tx_in * limit;
 566   } in;
 567   struct {
 568     tx_out * start;
 569     tx_out * ptr;
 570     tx_out * limit;
 571   } out;
 572 } amb_txq;
 573
 574 typedef struct {
 575   spinlock_t lock;
 576   unsigned int pending;
 577   unsigned int low;
 578   unsigned int emptied;
 579   unsigned int maximum; // size - 1 (q implementation)
 580   struct {
 581     rx_in * start;
 582     rx_in * ptr;
 583     rx_in * limit;
 584   } in;
 585   struct {
 586     rx_out * start;
 587     rx_out * ptr;
 588     rx_out * limit;
 589   } out;
 590   unsigned int buffers_wanted;
 591   unsigned int buffer_size;
 592 } amb_rxq;
 593
 594 typedef struct {
 595   unsigned long tx_ok;
 596   struct {
 597     unsigned long ok;
 598     unsigned long error;
 599     unsigned long badcrc;
 600     unsigned long toolong;
 601     unsigned long aborted;
 602     unsigned long unused;
 603   } rx;
 604 } amb_stats;
 605
 606 // a single struct pointed to by atm_vcc->dev_data
 607
 608 typedef struct {
 609   u8               tx_vc_bits:7;
 610   u8               tx_present:1;
 611 } amb_tx_info;
 612
 613 typedef struct {
 614   unsigned char    pool;
 615 } amb_rx_info;
 616
 617 typedef struct {
 618   amb_rx_info      rx_info;
 619   u16              tx_frame_bits;
 620   unsigned int     tx_rate;
 621   unsigned int     rx_rate;
 622 } amb_vcc;
 623
 624 struct amb_dev {
 625   u8               irq;
 626   u8               flags;
 627   u32              iobase;
 628   u32 *            membase;
 629
 630 #if 0
 631   struct tq_struct bh;
 632 #endif
 633
 634   amb_cq           cq;
 635   amb_txq          txq;
 636   amb_rxq          rxq[NUM_RX_POOLS];
 637
 638   struct semaphore vcc_sf;
 639   amb_tx_info      txer[NUM_VCS];
 640   struct atm_vcc * rxer[NUM_VCS];
 641   unsigned int     tx_avail;
 642   unsigned int     rx_avail;
 643
 644   amb_stats        stats;
 645
 646   struct atm_dev * atm_dev;
 647   struct pci_dev * pci_dev;
 648   struct amb_dev * prev;
 649 };
 650
 651 typedef struct amb_dev amb_dev;
 652
 653 #define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data)
 654 #define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data)
 655
 656 /* the microcode */
 657
 658 typedef struct {
 659   u32 start;
 660   unsigned int count;
 661 } region;
 662
 663 extern const region ucode_regions[];
 664 extern const u32 ucode_data[];
 665 extern const u32 ucode_start;
 666
 667 /* rate rounding */
 668
 669 typedef enum {
 670   round_up,
 671   round_down,
 672   round_nearest
 673 } rounding;
 674
 675 #endif