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Import 2.3.18pre1
[davej-history.git] / arch / i386 / kernel / bios32.c
blobf0c63c93807d45e826fd399bb6e3525b6ec5bfa6
1 /*
2 * bios32.c - Low-Level PCI Access
3 *
4 * $Id: bios32.c,v 1.48 1998/09/26 08:06:55 mj Exp $
5 *
6 * Copyright 1993, 1994 Drew Eckhardt
7 * Visionary Computing
8 * (Unix and Linux consulting and custom programming)
9 * Drew@Colorado.EDU
10 * +1 (303) 786-7975
11 *
12 * Drew's work was sponsored by:
13 * iX Multiuser Multitasking Magazine
14 * Hannover, Germany
15 * hm@ix.de
16 *
17 * Copyright 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
18 *
19 * For more information, please consult the following manuals (look at
20 * http://www.pcisig.com/ for how to get them):
21 *
22 * PCI BIOS Specification
23 * PCI Local Bus Specification
24 * PCI to PCI Bridge Specification
25 * PCI System Design Guide
26 *
27 *
28 * CHANGELOG :
29 * Jun 17, 1994 : Modified to accommodate the broken pre-PCI BIOS SPECIFICATION
30 * Revision 2.0 present on <thys@dennis.ee.up.ac.za>'s ASUS mainboard.
31 *
32 * Jan 5, 1995 : Modified to probe PCI hardware at boot time by Frederic
33 * Potter, potter@cao-vlsi.ibp.fr
34 *
35 * Jan 10, 1995 : Modified to store the information about configured pci
36 * devices into a list, which can be accessed via /proc/pci by
37 * Curtis Varner, cvarner@cs.ucr.edu
38 *
39 * Jan 12, 1995 : CPU-PCI bridge optimization support by Frederic Potter.
40 * Alpha version. Intel & UMC chipset support only.
41 *
42 * Apr 16, 1995 : Source merge with the DEC Alpha PCI support. Most of the code
43 * moved to drivers/pci/pci.c.
44 *
45 * Dec 7, 1996 : Added support for direct configuration access of boards
46 * with Intel compatible access schemes (tsbogend@alpha.franken.de)
47 *
48 * Feb 3, 1997 : Set internal functions to static, save/restore flags
49 * avoid dead locks reading broken PCI BIOS, werner@suse.de
50 *
51 * Apr 26, 1997 : Fixed case when there is BIOS32, but not PCI BIOS
52 * (mj@atrey.karlin.mff.cuni.cz)
53 *
54 * May 7, 1997 : Added some missing cli()'s. [mj]
55 *
56 * Jun 20, 1997 : Corrected problems in "conf1" type accesses.
57 * (paubert@iram.es)
58 *
59 * Aug 2, 1997 : Split to PCI BIOS handling and direct PCI access parts
60 * and cleaned it up... Martin Mares <mj@atrey.karlin.mff.cuni.cz>
61 *
62 * Feb 6, 1998 : No longer using BIOS to find devices and device classes. [mj]
63 *
64 * May 1, 1998 : Support for peer host bridges. [mj]
65 *
66 * Jun 19, 1998 : Changed to use spinlocks, so that PCI configuration space
67 * can be accessed from interrupts even on SMP systems. [mj]
68 *
69 * August 1998 : Better support for peer host bridges and more paranoid
70 * checks for direct hardware access. Ugh, this file starts to look as
71 * a large gallery of common hardware bug workarounds (watch the comments)
72 * -- the PCI specs themselves are sane, but most implementors should be
73 * hit hard with \hammer scaled \magstep5. [mj]
74 *
75 * Jan 23, 1999 : More improvements to peer host bridge logic. i450NX fixup. [mj]
76 *
77 * Feb 8, 1999 : Added UM8886BF I/O address fixup. [mj]
78 *
79 * August 1999 : New resource management and configuration access stuff. [mj]
80 */
81
82 #include <linux/config.h>
83 #include <linux/types.h>
84 #include <linux/kernel.h>
85 #include <linux/pci.h>
86 #include <linux/init.h>
87 #include <linux/ioport.h>
88 #include <linux/malloc.h>
89 #include <linux/smp_lock.h>
90 #include <linux/irq.h>
91 #include <linux/spinlock.h>
92
93 #include <asm/page.h>
94 #include <asm/segment.h>
95 #include <asm/system.h>
96 #include <asm/io.h>
97 #include <asm/smp.h>
98
99 #undef DEBUG
100
101 #ifdef DEBUG
102 #define DBG(x...) printk(x)
103 #else
104 #define DBG(x...)
105 #endif
106
107 #define PCI_PROBE_BIOS 1
108 #define PCI_PROBE_CONF1 2
109 #define PCI_PROBE_CONF2 4
110 #define PCI_NO_SORT 0x100
111 #define PCI_BIOS_SORT 0x200
112 #define PCI_NO_CHECKS 0x400
113 #define PCI_NO_PEER_FIXUP 0x800
114 #define PCI_ASSIGN_ROMS 0x1000
115
116 static unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
117
118 /*
119 * Direct access to PCI hardware...
120 */
121
122 #ifdef CONFIG_PCI_DIRECT
123
124 /*
125 * Functions for accessing PCI configuration space with type 1 accesses
126 */
127
128 #define CONFIG_CMD(dev, where) (0x80000000 | (dev->bus->number << 16) | (dev->devfn << 8) | (where & ~3))
129
130 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
131 {
132 outl(CONFIG_CMD(dev,where), 0xCF8);
133 *value = inb(0xCFC + (where&3));
134 return PCIBIOS_SUCCESSFUL;
135 }
136
137 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
138 {
139 outl(CONFIG_CMD(dev,where), 0xCF8);
140 *value = inw(0xCFC + (where&2));
141 return PCIBIOS_SUCCESSFUL;
142 }
143
144 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
145 {
146 outl(CONFIG_CMD(dev,where), 0xCF8);
147 *value = inl(0xCFC);
148 return PCIBIOS_SUCCESSFUL;
149 }
150
151 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
152 {
153 outl(CONFIG_CMD(dev,where), 0xCF8);
154 outb(value, 0xCFC + (where&3));
155 return PCIBIOS_SUCCESSFUL;
156 }
157
158 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
159 {
160 outl(CONFIG_CMD(dev,where), 0xCF8);
161 outw(value, 0xCFC + (where&2));
162 return PCIBIOS_SUCCESSFUL;
163 }
164
165 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
166 {
167 outl(CONFIG_CMD(dev,where), 0xCF8);
168 outl(value, 0xCFC);
169 return PCIBIOS_SUCCESSFUL;
170 }
171
172 #undef CONFIG_CMD
173
174 static struct pci_ops pci_direct_conf1 = {
175 pci_conf1_read_config_byte,
176 pci_conf1_read_config_word,
177 pci_conf1_read_config_dword,
178 pci_conf1_write_config_byte,
179 pci_conf1_write_config_word,
180 pci_conf1_write_config_dword
181 };
182
183 /*
184 * Functions for accessing PCI configuration space with type 2 accesses
185 */
186
187 #define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
188 #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
189 #define SET(dev) if (dev->devfn) return PCIBIOS_DEVICE_NOT_FOUND; \
190 outb(FUNC(dev->devfn), 0xCF8); \
191 outb(dev->bus->number, 0xCFA);
192
193 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
194 {
195 SET(dev);
196 *value = inb(IOADDR(dev->devfn,where));
197 outb (0, 0xCF8);
198 return PCIBIOS_SUCCESSFUL;
199 }
200
201 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
202 {
203 SET(dev);
204 *value = inw(IOADDR(dev->devfn,where));
205 outb (0, 0xCF8);
206 return PCIBIOS_SUCCESSFUL;
207 }
208
209 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
210 {
211 SET(dev);
212 *value = inl (IOADDR(dev->devfn,where));
213 outb (0, 0xCF8);
214 return PCIBIOS_SUCCESSFUL;
215 }
216
217 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
218 {
219 SET(dev);
220 outb (value, IOADDR(dev->devfn,where));
221 outb (0, 0xCF8);
222 return PCIBIOS_SUCCESSFUL;
223 }
224
225 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
226 {
227 SET(dev);
228 outw (value, IOADDR(dev->devfn,where));
229 outb (0, 0xCF8);
230 return PCIBIOS_SUCCESSFUL;
231 }
232
233 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
234 {
235 SET(dev);
236 outl (value, IOADDR(dev->devfn,where));
237 outb (0, 0xCF8);
238 return PCIBIOS_SUCCESSFUL;
239 }
240
241 #undef SET
242 #undef IOADDR
243 #undef FUNC
244
245 static struct pci_ops pci_direct_conf2 = {
246 pci_conf2_read_config_byte,
247 pci_conf2_read_config_word,
248 pci_conf2_read_config_dword,
249 pci_conf2_write_config_byte,
250 pci_conf2_write_config_word,
251 pci_conf2_write_config_dword
252 };
253
254 /*
255 * Before we decide to use direct hardware access mechanisms, we try to do some
256 * trivial checks to ensure it at least _seems_ to be working -- we just test
257 * whether bus 00 contains a host bridge (this is similar to checking
258 * techniques used in XFree86, but ours should be more reliable since we
259 * attempt to make use of direct access hints provided by the PCI BIOS).
260 *
261 * This should be close to trivial, but it isn't, because there are buggy
262 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
263 */
264 static int __init pci_sanity_check(struct pci_ops *o)
265 {
266 u16 x;
267 struct pci_bus bus; /* Fake bus and device */
268 struct pci_dev dev;
269
270 #ifdef CONFIG_VISWS
271 return 1; /* Lithium PCI Bridges are non-standard */
272 #endif
273
274 if (pci_probe & PCI_NO_CHECKS)
275 return 1;
276 bus.number = 0;
277 dev.bus = &bus;
278 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
279 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
280 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
281 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
282 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
283 return 1;
284 DBG("PCI: Sanity check failed\n");
285 return 0;
286 }
287
288 static struct pci_ops * __init pci_check_direct(void)
289 {
290 unsigned int tmp;
291 unsigned long flags;
292
293 __save_flags(flags); __cli();
294
295 /*
296 * Check if configuration type 1 works.
297 */
298 if (pci_probe & PCI_PROBE_CONF1) {
299 outb (0x01, 0xCFB);
300 tmp = inl (0xCF8);
301 outl (0x80000000, 0xCF8);
302 if (inl (0xCF8) == 0x80000000 &&
303 pci_sanity_check(&pci_direct_conf1)) {
304 outl (tmp, 0xCF8);
305 __restore_flags(flags);
306 printk("PCI: Using configuration type 1\n");
307 return &pci_direct_conf1;
308 }
309 outl (tmp, 0xCF8);
310 }
311
312 /*
313 * Check if configuration type 2 works.
314 */
315 if (pci_probe & PCI_PROBE_CONF2) {
316 outb (0x00, 0xCFB);
317 outb (0x00, 0xCF8);
318 outb (0x00, 0xCFA);
319 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
320 pci_sanity_check(&pci_direct_conf2)) {
321 __restore_flags(flags);
322 printk("PCI: Using configuration type 2\n");
323 return &pci_direct_conf2;
324 }
325 }
326
327 __restore_flags(flags);
328 return NULL;
329 }
330
331 #endif
332
333 /*
334 * BIOS32 and PCI BIOS handling.
335 */
336
337 #ifdef CONFIG_PCI_BIOS
338
339 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
340 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
341 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
342 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
343 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
344 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
345 #define PCIBIOS_READ_CONFIG_WORD 0xb109
346 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
347 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
348 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
349 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
350
351 /* BIOS32 signature: "_32_" */
352 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
353
354 /* PCI signature: "PCI " */
355 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
356
357 /* PCI service signature: "$PCI" */
358 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
359
360 /* PCI BIOS hardware mechanism flags */
361 #define PCIBIOS_HW_TYPE1 0x01
362 #define PCIBIOS_HW_TYPE2 0x02
363 #define PCIBIOS_HW_TYPE1_SPEC 0x10
364 #define PCIBIOS_HW_TYPE2_SPEC 0x20
365
366 /*
367 * This is the standard structure used to identify the entry point
368 * to the BIOS32 Service Directory, as documented in
369 * Standard BIOS 32-bit Service Directory Proposal
370 * Revision 0.4 May 24, 1993
371 * Phoenix Technologies Ltd.
372 * Norwood, MA
373 * and the PCI BIOS specification.
374 */
375
376 union bios32 {
377 struct {
378 unsigned long signature; /* _32_ */
379 unsigned long entry; /* 32 bit physical address */
380 unsigned char revision; /* Revision level, 0 */
381 unsigned char length; /* Length in paragraphs should be 01 */
382 unsigned char checksum; /* All bytes must add up to zero */
383 unsigned char reserved[5]; /* Must be zero */
384 } fields;
385 char chars[16];
386 };
387
388 /*
389 * Physical address of the service directory. I don't know if we're
390 * allowed to have more than one of these or not, so just in case
391 * we'll make pcibios_present() take a memory start parameter and store
392 * the array there.
393 */
394
395 static struct {
396 unsigned long address;
397 unsigned short segment;
398 } bios32_indirect = { 0, __KERNEL_CS };
399
400 /*
401 * Returns the entry point for the given service, NULL on error
402 */
403
404 static unsigned long bios32_service(unsigned long service)
405 {
406 unsigned char return_code; /* %al */
407 unsigned long address; /* %ebx */
408 unsigned long length; /* %ecx */
409 unsigned long entry; /* %edx */
410 unsigned long flags;
411
412 __save_flags(flags); __cli();
413 __asm__("lcall (%%edi)"
414 : "=a" (return_code),
415 "=b" (address),
416 "=c" (length),
417 "=d" (entry)
418 : "0" (service),
419 "1" (0),
420 "D" (&bios32_indirect));
421 __restore_flags(flags);
422
423 switch (return_code) {
424 case 0:
425 return address + entry;
426 case 0x80: /* Not present */
427 printk("bios32_service(0x%lx): not present\n", service);
428 return 0;
429 default: /* Shouldn't happen */
430 printk("bios32_service(0x%lx): returned 0x%x, report to <mj@ucw.cz>.\n",
431 service, return_code);
432 return 0;
433 }
434 }
435
436 static struct {
437 unsigned long address;
438 unsigned short segment;
439 } pci_indirect = { 0, __KERNEL_CS };
440
441 static int pci_bios_present;
442
443 static int __init check_pcibios(void)
444 {
445 u32 signature, eax, ebx, ecx;
446 u8 status, major_ver, minor_ver, hw_mech, last_bus;
447 unsigned long flags, pcibios_entry;
448
449 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
450 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
451
452 __save_flags(flags); __cli();
453 __asm__(
454 "lcall (%%edi)\n\t"
455 "jc 1f\n\t"
456 "xor %%ah, %%ah\n"
457 "1:"
458 : "=d" (signature),
459 "=a" (eax),
460 "=b" (ebx),
461 "=c" (ecx)
462 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
463 "D" (&pci_indirect)
464 : "memory");
465 __restore_flags(flags);
466
467 status = (eax >> 8) & 0xff;
468 hw_mech = eax & 0xff;
469 major_ver = (ebx >> 8) & 0xff;
470 minor_ver = ebx & 0xff;
471 last_bus = ecx & 0xff;
472 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
473 status, hw_mech, major_ver, minor_ver, last_bus);
474 if (status || signature != PCI_SIGNATURE) {
475 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found, report to <mj@ucw.cz>\n",
476 status, signature);
477 return 0;
478 }
479 printk("PCI: PCI BIOS revision %x.%02x entry at 0x%lx\n",
480 major_ver, minor_ver, pcibios_entry);
481 #ifdef CONFIG_PCI_DIRECT
482 if (!(hw_mech & PCIBIOS_HW_TYPE1))
483 pci_probe &= ~PCI_PROBE_CONF1;
484 if (!(hw_mech & PCIBIOS_HW_TYPE2))
485 pci_probe &= ~PCI_PROBE_CONF2;
486 #endif
487 return 1;
488 }
489 return 0;
490 }
491
492 #if 0 /* Not used */
493
494 static int pci_bios_find_class (unsigned int class_code, unsigned short index,
495 unsigned char *bus, unsigned char *device_fn)
496 {
497 unsigned long bx;
498 unsigned long ret;
499
500 __asm__ ("lcall (%%edi)\n\t"
501 "jc 1f\n\t"
502 "xor %%ah, %%ah\n"
503 "1:"
504 : "=b" (bx),
505 "=a" (ret)
506 : "1" (PCIBIOS_FIND_PCI_CLASS_CODE),
507 "c" (class_code),
508 "S" ((int) index),
509 "D" (&pci_indirect));
510 *bus = (bx >> 8) & 0xff;
511 *device_fn = bx & 0xff;
512 return (int) (ret & 0xff00) >> 8;
513 }
514
515 #endif
516
517 static int __init pci_bios_find_device (unsigned short vendor, unsigned short device_id,
518 unsigned short index, unsigned char *bus, unsigned char *device_fn)
519 {
520 unsigned short bx;
521 unsigned short ret;
522
523 __asm__("lcall (%%edi)\n\t"
524 "jc 1f\n\t"
525 "xor %%ah, %%ah\n"
526 "1:"
527 : "=b" (bx),
528 "=a" (ret)
529 : "1" (PCIBIOS_FIND_PCI_DEVICE),
530 "c" (device_id),
531 "d" (vendor),
532 "S" ((int) index),
533 "D" (&pci_indirect));
534 *bus = (bx >> 8) & 0xff;
535 *device_fn = bx & 0xff;
536 return (int) (ret & 0xff00) >> 8;
537 }
538
539 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
540 {
541 unsigned long ret;
542 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
543
544 __asm__("lcall (%%esi)\n\t"
545 "jc 1f\n\t"
546 "xor %%ah, %%ah\n"
547 "1:"
548 : "=c" (*value),
549 "=a" (ret)
550 : "1" (PCIBIOS_READ_CONFIG_BYTE),
551 "b" (bx),
552 "D" ((long) where),
553 "S" (&pci_indirect));
554 return (int) (ret & 0xff00) >> 8;
555 }
556
557 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
558 {
559 unsigned long ret;
560 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
561
562 __asm__("lcall (%%esi)\n\t"
563 "jc 1f\n\t"
564 "xor %%ah, %%ah\n"
565 "1:"
566 : "=c" (*value),
567 "=a" (ret)
568 : "1" (PCIBIOS_READ_CONFIG_WORD),
569 "b" (bx),
570 "D" ((long) where),
571 "S" (&pci_indirect));
572 return (int) (ret & 0xff00) >> 8;
573 }
574
575 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
576 {
577 unsigned long ret;
578 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
579
580 __asm__("lcall (%%esi)\n\t"
581 "jc 1f\n\t"
582 "xor %%ah, %%ah\n"
583 "1:"
584 : "=c" (*value),
585 "=a" (ret)
586 : "1" (PCIBIOS_READ_CONFIG_DWORD),
587 "b" (bx),
588 "D" ((long) where),
589 "S" (&pci_indirect));
590 return (int) (ret & 0xff00) >> 8;
591 }
592
593 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
594 {
595 unsigned long ret;
596 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
597
598 __asm__("lcall (%%esi)\n\t"
599 "jc 1f\n\t"
600 "xor %%ah, %%ah\n"
601 "1:"
602 : "=a" (ret)
603 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
604 "c" (value),
605 "b" (bx),
606 "D" ((long) where),
607 "S" (&pci_indirect));
608 return (int) (ret & 0xff00) >> 8;
609 }
610
611 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
612 {
613 unsigned long ret;
614 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
615
616 __asm__("lcall (%%esi)\n\t"
617 "jc 1f\n\t"
618 "xor %%ah, %%ah\n"
619 "1:"
620 : "=a" (ret)
621 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
622 "c" (value),
623 "b" (bx),
624 "D" ((long) where),
625 "S" (&pci_indirect));
626 return (int) (ret & 0xff00) >> 8;
627 }
628
629 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
630 {
631 unsigned long ret;
632 unsigned long bx = (dev->bus->number << 8) | dev->devfn;
633
634 __asm__("lcall (%%esi)\n\t"
635 "jc 1f\n\t"
636 "xor %%ah, %%ah\n"
637 "1:"
638 : "=a" (ret)
639 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
640 "c" (value),
641 "b" (bx),
642 "D" ((long) where),
643 "S" (&pci_indirect));
644 return (int) (ret & 0xff00) >> 8;
645 }
646
647 /*
648 * Function table for BIOS32 access
649 */
650
651 static struct pci_ops pci_bios_access = {
652 pci_bios_read_config_byte,
653 pci_bios_read_config_word,
654 pci_bios_read_config_dword,
655 pci_bios_write_config_byte,
656 pci_bios_write_config_word,
657 pci_bios_write_config_dword
658 };
659
660 /*
661 * Try to find PCI BIOS.
662 */
663
664 static struct pci_ops * __init pci_find_bios(void)
665 {
666 union bios32 *check;
667 unsigned char sum;
668 int i, length;
669
670 /*
671 * Follow the standard procedure for locating the BIOS32 Service
672 * directory by scanning the permissible address range from
673 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
674 */
675
676 for (check = (union bios32 *) __va(0xe0000);
677 check <= (union bios32 *) __va(0xffff0);
678 ++check) {
679 if (check->fields.signature != BIOS32_SIGNATURE)
680 continue;
681 length = check->fields.length * 16;
682 if (!length)
683 continue;
684 sum = 0;
685 for (i = 0; i < length ; ++i)
686 sum += check->chars[i];
687 if (sum != 0)
688 continue;
689 if (check->fields.revision != 0) {
690 printk("PCI: unsupported BIOS32 revision %d at 0x%p, report to <mj@ucw.cz>\n",
691 check->fields.revision, check);
692 continue;
693 }
694 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
695 if (check->fields.entry >= 0x100000) {
696 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
697 return NULL;
698 } else {
699 unsigned long bios32_entry = check->fields.entry;
700 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
701 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
702 if (check_pcibios())
703 return &pci_bios_access;
704 }
705 break; /* Hopefully more than one BIOS32 cannot happen... */
706 }
707
708 return NULL;
709 }
710
711 /*
712 * Sort the device list according to PCI BIOS. Nasty hack, but since some
713 * fool forgot to define the `correct' device order in the PCI BIOS specs
714 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
715 * which used BIOS ordering, we are bound to do this...
716 */
717
718 static void __init pcibios_sort(void)
719 {
720 struct pci_dev *dev = pci_devices;
721 struct pci_dev **last = &pci_devices;
722 struct pci_dev *d, **dd, *e;
723 int idx;
724 unsigned char bus, devfn;
725
726 DBG("PCI: Sorting device list...\n");
727 while ((e = dev)) {
728 idx = 0;
729 while (pci_bios_find_device(e->vendor, e->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
730 idx++;
731 for(dd=&dev; (d = *dd); dd = &d->next) {
732 if (d->bus->number == bus && d->devfn == devfn) {
733 *dd = d->next;
734 *last = d;
735 last = &d->next;
736 break;
737 }
738 }
739 if (!d) {
740 printk("PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
741 /*
742 * We must not continue scanning as several buggy BIOSes
743 * return garbage after the last device. Grr.
744 */
745 break;
746 }
747 }
748 if (e == dev) {
749 printk("PCI: Device %02x:%02x not found by BIOS\n",
750 dev->bus->number, dev->devfn);
751 d = dev;
752 dev = dev->next;
753 *last = d;
754 last = &d->next;
755 }
756 }
757 *last = NULL;
758 }
759
760 #endif
761
762 /*
763 * Several BIOS'es forget to assign addresses to I/O ranges. Try to fix it.
764 */
765
766 static void __init pcibios_fixup_io_addr(struct pci_dev *dev, int idx)
767 {
768 unsigned int reg = PCI_BASE_ADDRESS_0 + 4*idx;
769 struct resource *r = &dev->resource[idx];
770 unsigned int size = r->end - r->start + 1;
771
772 if (((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && idx < 4) ||
773 (dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
774 /*
775 * In case the BIOS didn't assign an address 0--3 to an IDE
776 * controller, we don't try to fix it as it means "use default
777 * addresses" at least with several broken chips and the IDE
778 * driver needs the original settings to recognize which devices
779 * correspond to the primary controller.
780 *
781 * We don't assign VGA I/O ranges as well.
782 */
783 return;
784 }
785 /*
786 * We need to avoid collisions with `mirrored' VGA ports and other strange
787 * ISA hardware, so we always want the addresses kilobyte aligned.
788 */
789 if (!size || size > 256) {
790 printk(KERN_ERR "PCI: Cannot assign I/O space to device %s, %d bytes are too much.\n", dev->name, size);
791 return;
792 } else {
793 u32 try;
794
795 r->start = 0;
796 r->end = size - 1;
797 if (pci_assign_resource(dev, idx)) {
798 printk(KERN_ERR "PCI: Unable to find free %d bytes of I/O space for device %s.\n", size, dev->name);
799 return;
800 }
801 printk("PCI: Assigned I/O space %04lx-%04lx to device %s\n", r->start, r->end, dev->name);
802 pci_read_config_dword(dev, reg, &try);
803 if ((try & PCI_BASE_ADDRESS_IO_MASK) != r->start) {
804 r->start = 0;
805 pci_write_config_dword(dev, reg, 0);
806 printk(KERN_ERR "PCI: I/O address setup failed, got %04x\n", try);
807 }
808 }
809 }
810
811 /*
812 * Assign address to expansion ROM. This is a highly experimental feature
813 * and you must enable it by "pci=rom". It's even not guaranteed to work
814 * with all cards since the PCI specs allow address decoders to be shared
815 * between the ROM space and one of the standard regions (sigh!).
816 */
817 static void __init pcibios_fixup_rom_addr(struct pci_dev *dev)
818 {
819 int reg = (dev->hdr_type == 1) ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
820 struct resource *r = &dev->resource[PCI_ROM_RESOURCE];
821 unsigned long rom_size = r->end - r->start + 1;
822
823 r->start = 0;
824 r->end = rom_size - 1;
825 if (pci_assign_resource(dev, PCI_ROM_RESOURCE))
826 printk(KERN_ERR "PCI: Unable to find free space for expansion ROM of device %s (0x%lx bytes)\n",
827 dev->name, rom_size);
828 else {
829 DBG("PCI: Assigned address %08lx to expansion ROM of %s (0x%lx bytes)\n", r->start, dev->name, rom_size);
830 pci_write_config_dword(dev, reg, r->start | PCI_ROM_ADDRESS_ENABLE);
831 r->flags |= PCI_ROM_ADDRESS_ENABLE;
832 }
833 }
834
835 /*
836 * Several buggy motherboards address only 16 devices and mirror
837 * them to next 16 IDs. We try to detect this `feature' on all
838 * primary busses (those containing host bridges as they are
839 * expected to be unique) and remove the ghost devices.
840 */
841
842 static void __init pcibios_fixup_ghosts(struct pci_bus *b)
843 {
844 struct pci_dev *d, *e, **z;
845 int mirror = PCI_DEVFN(16,0);
846 int seen_host_bridge = 0;
847 int i;
848
849 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
850 for(d=b->devices; d && d->devfn < mirror; d=d->sibling) {
851 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
852 seen_host_bridge++;
853 for(e=d->next; e; e=e->sibling) {
854 if (e->devfn != d->devfn + mirror ||
855 e->vendor != d->vendor ||
856 e->device != d->device ||
857 e->class != d->class)
858 continue;
859 for(i=0; i<PCI_NUM_RESOURCES; i++)
860 if (e->resource[i].start != d->resource[i].start ||
861 e->resource[i].end != d->resource[i].end ||
862 e->resource[i].flags != d->resource[i].flags)
863 continue;
864 break;
865 }
866 if (!e)
867 return;
868 }
869 if (!seen_host_bridge)
870 return;
871 printk("PCI: Ignoring ghost devices on bus %d\n", b->number);
872 for(e=b->devices; e->sibling != d; e=e->sibling);
873 e->sibling = NULL;
874 for(z=&pci_devices; (d=*z);)
875 if (d->bus == b && d->devfn >= mirror) {
876 *z = d->next;
877 kfree_s(d, sizeof(*d));
878 } else
879 z = &d->next;
880 }
881
882 /*
883 * In case there are peer host bridges, scan bus behind each of them.
884 * Although several sources claim that the host bridges should have
885 * header type 1 and be assigned a bus number as for PCI2PCI bridges,
886 * the reality doesn't pass this test and the bus number is usually
887 * set by BIOS to the first free value.
888 */
889 static void __init pcibios_fixup_peer_bridges(void)
890 {
891 struct pci_bus *b = pci_root;
892 int n, cnt=-1;
893 struct pci_dev *d;
894 struct pci_ops *ops = pci_root->ops;
895
896 #ifdef CONFIG_VISWS
897 pci_scan_bus(1, ops, NULL);
898 return;
899 #endif
900
901 #ifdef CONFIG_PCI_DIRECT
902 /*
903 * Don't search for peer host bridges if we use config type 2
904 * since it reads bogus values for non-existent busses and
905 * chipsets supporting multiple primary busses use conf1 anyway.
906 */
907 if (ops == &pci_direct_conf2)
908 return;
909 #endif
910
911 for(d=b->devices; d; d=d->sibling)
912 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
913 cnt++;
914 n = b->subordinate + 1;
915 while (n <= 0xff) {
916 int found = 0;
917 u16 l;
918 struct pci_bus bus;
919 struct pci_dev dev;
920 bus.number = n;
921 bus.ops = ops;
922 dev.bus = &bus;
923 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
924 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
925 l != 0x0000 && l != 0xffff) {
926 #ifdef CONFIG_PCI_BIOS
927 if (pci_bios_present) {
928 int err, idx = 0;
929 u8 bios_bus, bios_dfn;
930 u16 d;
931 pci_read_config_word(&dev, PCI_DEVICE_ID, &d);
932 DBG("BIOS test for %02x:%02x (%04x:%04x)\n", n, dev.devfn, l, d);
933 while (!(err = pci_bios_find_device(l, d, idx, &bios_bus, &bios_dfn)) &&
934 (bios_bus != n || bios_dfn != dev.devfn))
935 idx++;
936 if (err)
937 break;
938 }
939 #endif
940 DBG("Found device at %02x:%02x\n", n, dev.devfn);
941 found++;
942 if (!pci_read_config_word(&dev, PCI_CLASS_DEVICE, &l) &&
943 l == PCI_CLASS_BRIDGE_HOST)
944 cnt++;
945 }
946 if (cnt-- <= 0)
947 break;
948 if (found) {
949 printk("PCI: Discovered primary peer bus %02x\n", n);
950 b = pci_scan_bus(n, ops, NULL);
951 if (b)
952 n = b->subordinate;
953 }
954 n++;
955 }
956 }
957
958 /*
959 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
960 */
961
962 static void __init pci_fixup_i450nx(struct pci_dev *d)
963 {
964 /*
965 * i450NX -- Find and scan all secondary buses on all PXB's.
966 */
967 int pxb, reg;
968 u8 busno, suba, subb;
969 printk("PCI: Searching for i450NX host bridges on %s\n", d->name);
970 reg = 0xd0;
971 for(pxb=0; pxb<2; pxb++) {
972 pci_read_config_byte(d, reg++, &busno);
973 pci_read_config_byte(d, reg++, &suba);
974 pci_read_config_byte(d, reg++, &subb);
975 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
976 if (busno)
977 pci_scan_bus(busno, pci_root->ops, NULL); /* Bus A */
978 if (suba < subb)
979 pci_scan_bus(suba+1, pci_root->ops, NULL); /* Bus B */
980 }
981 pci_probe |= PCI_NO_PEER_FIXUP;
982 }
983
984 static void __init pci_fixup_umc_ide(struct pci_dev *d)
985 {
986 /*
987 * UM8886BF IDE controller sets region type bits incorrectly,
988 * therefore they look like memory despite of them being I/O.
989 */
990 int i;
991
992 printk("PCI: Fixing base address flags for device %s\n", d->name);
993 for(i=0; i<4; i++)
994 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
995 }
996
997 struct pci_fixup pcibios_fixups[] = {
998 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
999 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
1000 { 0 }
1001 };
1002
1003 /*
1004 * Allocate resources for all PCI devices. We need to do that before
1005 * we try to fix up anything.
1006 */
1007
1008 static void __init pcibios_claim_resources(struct pci_bus *bus)
1009 {
1010 struct pci_dev *dev;
1011 int idx;
1012
1013 while (bus) {
1014 for (dev=bus->devices; dev; dev=dev->sibling)
1015 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
1016 struct resource *r = &dev->resource[idx];
1017 struct resource *pr;
1018 if (!r->start)
1019 continue;
1020 pr = pci_find_parent_resource(dev, r);
1021 if (!pr || request_resource(pr, r) < 0) {
1022 printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", idx, dev->name);
1023 /* We probably should disable the region, shouldn't we? */
1024 }
1025 }
1026 if (bus->children)
1027 pcibios_claim_resources(bus->children);
1028 bus = bus->next;
1029 }
1030 }
1031
1032 /*
1033 * Fix base addresses, I/O and memory enables and IRQ's (mostly work-arounds
1034 * for buggy PCI BIOS'es :-[).
1035 */
1036
1037 extern int skip_ioapic_setup;
1038
1039 static void __init pcibios_fixup_devices(void)
1040 {
1041 struct pci_dev *dev;
1042 int i, has_io, has_mem;
1043 unsigned short cmd;
1044
1045 for(dev = pci_devices; dev; dev=dev->next) {
1046 /*
1047 * There are buggy BIOSes that forget to enable I/O and memory
1048 * access to PCI devices. We try to fix this, but we need to
1049 * be sure that the BIOS didn't forget to assign an address
1050 * to the device. [mj]
1051 */
1052 has_io = has_mem = 0;
1053 for(i=0; i<6; i++) {
1054 struct resource *r = &dev->resource[i];
1055 if (r->flags & PCI_BASE_ADDRESS_SPACE_IO) {
1056 has_io = 1;
1057 if (!r->start || r->start == PCI_BASE_ADDRESS_IO_MASK)
1058 pcibios_fixup_io_addr(dev, i);
1059 } else if (r->start)
1060 has_mem = 1;
1061 }
1062 /*
1063 * Don't enable VGA-compatible cards since they have
1064 * fixed I/O and memory space.
1065 *
1066 * Don't enabled disabled IDE interfaces either because
1067 * some BIOSes may reallocate the same address when they
1068 * find that no devices are attached.
1069 */
1070 if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) &&
1071 ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)) {
1072 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1073 if (has_io && !(cmd & PCI_COMMAND_IO)) {
1074 printk("PCI: Enabling I/O for device %s\n", dev->name);
1075 cmd |= PCI_COMMAND_IO;
1076 pci_write_config_word(dev, PCI_COMMAND, cmd);
1077 }
1078 if (has_mem && !(cmd & PCI_COMMAND_MEMORY)) {
1079 printk("PCI: Enabling memory for device %s\n", dev->name);
1080 cmd |= PCI_COMMAND_MEMORY;
1081 pci_write_config_word(dev, PCI_COMMAND, cmd);
1082 }
1083 }
1084 /*
1085 * Assign address to expansion ROM if requested.
1086 */
1087 if ((pci_probe & PCI_ASSIGN_ROMS) && dev->resource[PCI_ROM_RESOURCE].end)
1088 pcibios_fixup_rom_addr(dev);
1089 #if defined(CONFIG_X86_IO_APIC)
1090 /*
1091 * Recalculate IRQ numbers if we use the I/O APIC
1092 */
1093 if(!skip_ioapic_setup)
1094 {
1095 int irq;
1096 unsigned char pin;
1097
1098 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1099 if (pin) {
1100 pin--; /* interrupt pins are numbered starting from 1 */
1101 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1102 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1103 struct pci_dev * bridge = dev->bus->self;
1104
1105 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1106 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1107 PCI_SLOT(bridge->devfn), pin);
1108 if (irq >= 0)
1109 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
1110 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
1111 }
1112 if (irq >= 0) {
1113 printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
1114 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
1115 dev->irq = irq;
1116 }
1117 }
1118 }
1119 #endif
1120 /*
1121 * Fix out-of-range IRQ numbers
1122 */
1123 if (dev->irq >= NR_IRQS)
1124 dev->irq = 0;
1125 }
1126 }
1127
1128 /*
1129 * Called after each bus is probed, but before its children
1130 * are examined.
1131 */
1132
1133 void __init pcibios_fixup_bus(struct pci_bus *b)
1134 {
1135 pcibios_fixup_ghosts(b);
1136 }
1137
1138 /*
1139 * Initialization. Try all known PCI access methods. Note that we support
1140 * using both PCI BIOS and direct access: in such cases, we use I/O ports
1141 * to access config space, but we still keep BIOS order of cards to be
1142 * compatible with 2.0.X. This should go away some day.
1143 */
1144
1145 void __init pcibios_init(void)
1146 {
1147 struct pci_ops *bios = NULL;
1148 struct pci_ops *dir = NULL;
1149 struct pci_ops *ops;
1150
1151 #ifdef CONFIG_PCI_BIOS
1152 if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) {
1153 pci_probe |= PCI_BIOS_SORT;
1154 pci_bios_present = 1;
1155 }
1156 #endif
1157 #ifdef CONFIG_PCI_DIRECT
1158 if (pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
1159 dir = pci_check_direct();
1160 #endif
1161 if (dir)
1162 ops = dir;
1163 else if (bios)
1164 ops = bios;
1165 else {
1166 printk("PCI: No PCI bus detected\n");
1167 return;
1168 }
1169
1170 printk("PCI: Probing PCI hardware\n");
1171 pci_scan_bus(0, ops, NULL);
1172
1173 if (!(pci_probe & PCI_NO_PEER_FIXUP))
1174 pcibios_fixup_peer_bridges();
1175 pcibios_claim_resources(pci_root);
1176 pcibios_fixup_devices();
1177
1178 #ifdef CONFIG_PCI_BIOS
1179 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
1180 pcibios_sort();
1181 #endif
1182 }
1183
1184 char * __init pcibios_setup(char *str)
1185 {
1186 if (!strcmp(str, "off")) {
1187 pci_probe = 0;
1188 return NULL;
1189 }
1190 #ifdef CONFIG_PCI_BIOS
1191 else if (!strcmp(str, "bios")) {
1192 pci_probe = PCI_PROBE_BIOS;
1193 return NULL;
1194 } else if (!strcmp(str, "nobios")) {
1195 pci_probe &= ~PCI_PROBE_BIOS;
1196 return NULL;
1197 } else if (!strcmp(str, "nosort")) {
1198 pci_probe |= PCI_NO_SORT;
1199 return NULL;
1200 }
1201 #endif
1202 #ifdef CONFIG_PCI_DIRECT
1203 else if (!strcmp(str, "conf1")) {
1204 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1205 return NULL;
1206 }
1207 else if (!strcmp(str, "conf2")) {
1208 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1209 return NULL;
1210 }
1211 #endif
1212 else if (!strcmp(str, "nopeer")) {
1213 pci_probe |= PCI_NO_PEER_FIXUP;
1214 return NULL;
1215 } else if (!strcmp(str, "rom")) {
1216 pci_probe |= PCI_ASSIGN_ROMS;
1217 return NULL;
1218 }
1219 return str;
1220 }
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