arch/alpha/kernel/pci_impl.h

   1 /*
   2  *      linux/arch/alpha/kernel/pci_impl.h
   3  *
   4  * This file contains declarations and inline functions for interfacing
   5  * with the PCI initialization routines.
   6  */
   7
   8 struct pci_dev;
   9 struct pci_controler;
  10
  11
  12 /*
  13  * We can't just blindly use 64K for machines with EISA busses; they
  14  * may also have PCI-PCI bridges present, and then we'd configure the
  15  * bridge incorrectly.
  16  *
  17  * Also, we start at 0x8000 or 0x9000, in hopes to get all devices'
  18  * IO space areas allocated *before* 0xC000; this is because certain
  19  * BIOSes (Millennium for one) use PCI Config space "mechanism #2"
  20  * accesses to probe the bus. If a device's registers appear at 0xC000,
  21  * it may see an INx/OUTx at that address during BIOS emulation of the
  22  * VGA BIOS, and some cards, notably Adaptec 2940UW, take mortal offense.
  23  */
  24
  25 #define EISA_DEFAULT_IO_BASE    0x9000  /* start above 8th slot */
  26 #define DEFAULT_IO_BASE         0x8000  /* start at 8th slot */
  27
  28 /*
  29  * We try to make the DEFAULT_MEM_BASE addresses *always* have more than
  30  * a single bit set. This is so that devices like the broken Myrinet card
  31  * will always have a PCI memory address that will never match a IDSEL
  32  * address in PCI Config space, which can cause problems with early rev cards.
  33  */
  34
  35 /*
  36  * An XL is AVANTI (APECS) family, *but* it has only 27 bits of ISA address
  37  * that get passed through the PCI<->ISA bridge chip. Although this causes
  38  * us to set the PCI->Mem window bases lower than normal, we still allocate
  39  * PCI bus devices' memory addresses *below* the low DMA mapping window,
  40  * and hope they fit below 64Mb (to avoid conflicts), and so that they can
  41  * be accessed via SPARSE space.
  42  *
  43  * We accept the risk that a broken Myrinet card will be put into a true XL
  44  * and thus can more easily run into the problem described below.
  45  */
  46 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
  47
  48 /*
  49  * APECS and LCA have only 34 bits for physical addresses, thus limiting PCI
  50  * bus memory addresses for SPARSE access to be less than 128Mb.
  51  */
  52 #define APECS_AND_LCA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
  53
  54 /*
  55  * Because the MCPCIA core logic supports more bits for physical addresses,
  56  * it should allow an expanded range of SPARSE memory addresses.
  57  * However, we do not use them all, in order to avoid the HAE manipulation
  58  * that would be needed.
  59  */
  60 #define MCPCIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
  61
  62 /*
  63  * Because CIA and PYXIS and T2 have more bits for physical addresses,
  64  * they support an expanded range of SPARSE memory addresses.
  65  */
  66 #define DEFAULT_MEM_BASE ((128+16)*1024*1024)
  67
  68 /* ??? Experimenting with no HAE for CIA.  */
  69 #define CIA_DEFAULT_MEM_BASE ((32+2)*1024*1024)
  70
  71
  72 /*
  73  * A small note about bridges and interrupts.  The DECchip 21050 (and
  74  * later) adheres to the PCI-PCI bridge specification.  This says that
  75  * the interrupts on the other side of a bridge are swizzled in the
  76  * following manner:
  77  *
  78  * Dev    Interrupt   Interrupt
  79  *        Pin on      Pin on
  80  *        Device      Connector
  81  *
  82  *   4    A           A
  83  *        B           B
  84  *        C           C
  85  *        D           D
  86  *
  87  *   5    A           B
  88  *        B           C
  89  *        C           D
  90  *        D           A
  91  *
  92  *   6    A           C
  93  *        B           D
  94  *        C           A
  95  *        D           B
  96  *
  97  *   7    A           D
  98  *        B           A
  99  *        C           B
 100  *        D           C
 101  *
 102  *   Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
 103  *   Thus, each swizzle is ((pin-1) + (device#-4)) % 4
 104  *
 105  *   The following code swizzles for exactly one bridge.  The routine
 106  *   common_swizzle below handles multiple bridges.  But there are a
 107  *   couple boards that do strange things, so we define this here.
 108  */
 109
 110 static inline u8 bridge_swizzle(u8 pin, u8 slot)
 111 {
 112         return (((pin-1) + slot) % 4) + 1;
 113 }
 114
 115
 116 /* The following macro is used to implement the table-based irq mapping
 117    function for all single-bus Alphas.  */
 118
 119 #define COMMON_TABLE_LOOKUP                                             \
 120 ({ long _ctl_ = -1;                                                     \
 121    if (slot >= min_idsel && slot <= max_idsel && pin < irqs_per_slot)   \
 122      _ctl_ = irq_tab[slot - min_idsel][pin];                            \
 123    _ctl_; })
 124
 125
 126 /* The hose list.  */
 127 extern struct pci_controler *hose_head, **hose_tail;
 128 extern struct pci_controler *probing_hose;
 129
 130 extern void common_init_pci(void);
 131 extern u8 common_swizzle(struct pci_dev *, u8 *);
 132 extern struct pci_controler *alloc_pci_controler(unsigned long *);
 133 extern struct resource *alloc_resource(unsigned long *);
 134
 135 extern const char *const pci_io_names[];
 136 extern const char *const pci_mem_names[];
 137 extern const char pci_hae0_name[];